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authorAaron Durbin <adurbin@chromium.org>2014-07-15 13:13:51 -0500
committerMarc Jones <marc.jones@se-eng.com>2015-03-13 00:01:14 +0100
commitb397f011497e9ea3fa06ed8d3bf29947e55a2677 (patch)
tree03b86cd214ae09533007f96b33611f85e9e74f6c
parentc20ff482a73ddb752fa32fa9d4b3e89420d1fee9 (diff)
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tegra132: split memory range querying to above/below 4GiB
The address map code was originally assuming all carveouts would be packed together in the upper end of the physical memory address space. However, the trust zone carveout is always in the 32-bit address space. Therefore, one needs to query memory ranges by above and below 4GiB with the assumption of carveouts being packed at the top of *each* resulting range. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and ran through coreboot on rush. Original-Change-Id: Iab134a049f3726f1ec41fc6626b1a6683d9f5362 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208101 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 8d5795fbff36e91906384e10774a32541d358324) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If15ff48d5a4c81731eb364980b30c8086deb1cca Reviewed-on: http://review.coreboot.org/8641 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/nvidia/tegra132/addressmap.c36
-rw-r--r--src/soc/nvidia/tegra132/include/soc/addressmap.h13
-rw-r--r--src/soc/nvidia/tegra132/ramstage.c2
3 files changed, 35 insertions, 16 deletions
diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c
index 7f6d7c3d7..7dbab556e 100644
--- a/src/soc/nvidia/tegra132/addressmap.c
+++ b/src/soc/nvidia/tegra132/addressmap.c
@@ -102,7 +102,7 @@ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib)
}
}
-void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib)
+static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib)
{
uintptr_t base;
uintptr_t end;
@@ -111,11 +111,21 @@ void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib)
base = CONFIG_SYS_SDRAM_BASE / MiB;
end = base + sdram_size_mb();
- if (bits == ADDRESS_SPACE_32_BIT)
- end = MIN(end, 4096);
+ /* Requested limits out of range. */
+ if (*end_mib <= base || *base_mib >= end) {
+ *end_mib = *base_mib = 0;
+ return;
+ }
+
+ /* Clip region to passed in limits. */
+ if (*end_mib < end)
+ end = *end_mib;
+ if (*base_mib > base)
+ base = *base_mib;
for (i = 0; i < CARVEOUT_NUM; i++) {
uintptr_t carveout_base;
+ uintptr_t carveout_end;
size_t carveout_size;
carveout_range(i, &carveout_base, &carveout_size);
@@ -123,8 +133,10 @@ void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib)
if (carveout_size == 0)
continue;
+ carveout_end = carveout_base + carveout_size;
+
/* Bypass carveouts out of requested range. */
- if (carveout_base >= end)
+ if (carveout_base >= end || carveout_end <= base)
continue;
/*
@@ -139,13 +151,27 @@ void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib)
*end_mib = end;
}
+void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib)
+{
+ *base_mib = 0;
+ *end_mib = 4096;
+ memory_in_range(base_mib, end_mib);
+}
+
+void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib)
+{
+ *base_mib = 4096;
+ *end_mib = ~0UL;
+ memory_in_range(base_mib, end_mib);
+}
+
uintptr_t framebuffer_attributes(size_t *size_mib)
{
uintptr_t begin;
uintptr_t end;
/* Place the framebuffer just below the 32-bit addressable limit. */
- memory_range_by_bits(ADDRESS_SPACE_32_BIT, &begin, &end);
+ memory_in_range_below_4gb(&begin, &end);
/*
* Need to take into account that the Trust Zone region is not able to
diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h
index 2c6dc5efc..3d0fc5990 100644
--- a/src/soc/nvidia/tegra132/include/soc/addressmap.h
+++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h
@@ -84,16 +84,9 @@ enum {
/* Return total size of DRAM memory configured on the platform. */
int sdram_size_mb(void);
-enum {
- ADDRESS_SPACE_32_BIT = 32,
- ADDRESS_SPACE_64_BIT = 64,
-};
-
-/*
- * Return the address range of memory for provided address width. The base
- * and end parameters in 1MiB units with end being exclusive to the range.
- */
-void memory_range_by_bits(int bits, uintptr_t *base_mib, uintptr_t *end_mib);
+/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */
+void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib);
+void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib);
enum {
CARVEOUT_TZ,
diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c
index 7b2f4e8c3..8d64c3e11 100644
--- a/src/soc/nvidia/tegra132/ramstage.c
+++ b/src/soc/nvidia/tegra132/ramstage.c
@@ -38,7 +38,7 @@ void arm64_soc_init(void)
* Therefore configure the region early. Also, the TZ region can only
* live in 32-bit space.
*/
- memory_range_by_bits(ADDRESS_SPACE_32_BIT, &base, &end);
+ memory_in_range_below_4gb(&base, &end);
/* Place the TZ area just below current carveout regions. */
end -= tz_size_mib;