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authorFurquan Shaikh <furquan@google.com>2014-07-23 13:46:13 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-03-17 16:40:21 +0100
commit64352a7c1b50819828cffdeacd93c757ee91c3ba (patch)
treeb3c3afd280f81421ccea8833ba14a3d898d72a82
parentaa228d08e9b67bd36dd9952e9e0eadc8dbe3a8d9 (diff)
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rush: Pull in chromeos.c from nyan into rush
Hardcoded values are set for developer,recovery mode. Change as per requirements BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles succesfully for rush Original-Change-Id: Ied506a9d1c4e0ba8ee06d57c6ca8c726220998b5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209974 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 2e6934d47c5b4bb98e60486202b230bae79d927b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I36e384b0d331fdd9e3f47954decfddaf4f31aed3 Reviewed-on: http://review.coreboot.org/8678 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/google/rush/Kconfig1
-rw-r--r--src/mainboard/google/rush/Makefile.inc2
-rw-r--r--src/mainboard/google/rush/chromeos.c90
3 files changed, 93 insertions, 0 deletions
diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
index b3dd3de3f..ebcde6368 100644
--- a/src/mainboard/google/rush/Kconfig
+++ b/src/mainboard/google/rush/Kconfig
@@ -21,6 +21,7 @@ if BOARD_GOOGLE_RUSH
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
+ select CHROMEOS
select SOC_NVIDIA_TEGRA132
select MAINBOARD_HAS_BOOTBLOCK_INIT
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index 3c2b5da30..b66cd555f 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -35,5 +35,7 @@ bootblock-y += reset.c
romstage-y += reset.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/rush/chromeos.c b/src/mainboard/google/rush/chromeos.c
new file mode 100644
index 000000000..91cb9d832
--- /dev/null
+++ b/src/mainboard/google/rush/chromeos.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/nvidia/tegra132/gpio.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ int count = 0;
+
+ /* Write Protect: active low */
+ gpios->gpios[count].port = GPIO_R1_INDEX;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = gpio_get_in_value(GPIO(R1));
+ strncpy((char *)gpios->gpios[count].name, "write protect",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Recovery: active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = 1;
+ strncpy((char *)gpios->gpios[count].name, "recovery",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Lid: active high */
+ gpios->gpios[count].port = GPIO_R4_INDEX;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = 1;
+ strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Power: active low */
+ gpios->gpios[count].port = GPIO_Q0_INDEX;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = 1;
+ strncpy((char *)gpios->gpios[count].name, "power",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Developer: virtual GPIO active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "developer",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+ gpios->count = count;
+
+ printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ return 0;
+}
+
+int get_write_protect_state(void)
+{
+ return !gpio_get_in_value(GPIO(R1));
+}