aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDaisuke Nojiri <dnojiri@chromium.org>2014-12-29 16:04:23 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-17 09:20:50 +0200
commit55cb84b244732dc93a096aadb2d324a1a05801db (patch)
tree77a0b00cff78f030280b0707926da2dbe222e49f
parent53b74f6868cab51d6c8640ece3502297e3396e4b (diff)
downloadcoreboot-55cb84b244732dc93a096aadb2d324a1a05801db.tar.gz
coreboot-55cb84b244732dc93a096aadb2d324a1a05801db.tar.xz
coreboot-55cb84b244732dc93a096aadb2d324a1a05801db.zip
bg4cd: define custom romstage entry
this change defines a custom romstage entry for bg4cd. the entry code stalls subcores, sets up the stack, and clears the bss before jumping to main. BUG=none BRANCH=tot TEST=built all current boards. booted cosmos p1 Change-Id: Idde43f94555bec7804a16928c58ce673956a39e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a35e12eb29b351cc0baaea24344f00d2ba905f6 Original-Change-Id: I9172e873a43847f3ea82cd1d9fd0841f0db83994 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238022 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/soc/marvell/bg4cd/Makefile.inc1
-rw-r--r--src/soc/marvell/bg4cd/romstage.S79
2 files changed, 80 insertions, 0 deletions
diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc
index 18f9d8ddf..4cbca0002 100644
--- a/src/soc/marvell/bg4cd/Makefile.inc
+++ b/src/soc/marvell/bg4cd/Makefile.inc
@@ -26,6 +26,7 @@ verstage-y += i2c.c
verstage-y += monotonic_timer.c
verstage-$(CONFIG_SPI_FLASH) += spi.c
+romstage-y += romstage.S
romstage-y += cbmem.c
romstage-y += i2c.c
romstage-y += monotonic_timer.c
diff --git a/src/soc/marvell/bg4cd/romstage.S b/src/soc/marvell/bg4cd/romstage.S
new file mode 100644
index 000000000..9a7a68e28
--- /dev/null
+++ b/src/soc/marvell/bg4cd/romstage.S
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <arch/asm.h>
+
+.arm
+ENTRY(stage_entry)
+ /*
+ * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
+ * aborts may happen early and crash before the abort handlers are
+ * installed, but at least the problem will show up near the code that
+ * causes it.
+ */
+ msr cpsr_cxf, #0xdf
+ bl _thumb_start
+ENDPROC(stage_entry)
+
+.thumb
+ENTRY(_thumb_start)
+ bl arm_init_caches
+
+ /*
+ * From Cortex-A Series Programmer's Guide:
+ * Only CPU 0 performs initialization. Other CPUs go into WFI
+ * to do this, first work out which CPU this is
+ * this code typically is run before any other initialization step
+ */
+ mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register
+ and r1, r1, #0x3 @ Extract CPU ID bits
+ cmp r1, #0
+ bne wait_for_interrupt @ If this is not core0, wait
+
+ /*
+ * Initialize the stack to a known value. This is used to check for
+ * stack overflow later in the boot process.
+ */
+ ldr r0, =_stack
+ ldr r1, =_estack
+ ldr r2, =0xdeadbeef
+init_stack_loop:
+ str r2, [r0]
+ add r0, #4
+ cmp r0, r1
+ bne init_stack_loop
+
+ ldr sp, =_estack /* Set up stack pointer */
+ bl main
+
+wait_for_interrupt:
+ wfi
+ mov pc, lr @ back to my caller
+ENDPROC(_thumb_start)