aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2011-04-11 20:17:22 +0000
committerStefan Reinauer <stepan@openbios.org>2011-04-11 20:17:22 +0000
commit5005bb06c17461ef75cd1fef55c24dffaa05e580 (patch)
tree2c38986a89152225ad56cb44227f5bc6ddbecd06
parent1fa61ebb3344105ae633ed7eb1be05cc574b666c (diff)
downloadcoreboot-5005bb06c17461ef75cd1fef55c24dffaa05e580.tar.gz
coreboot-5005bb06c17461ef75cd1fef55c24dffaa05e580.tar.xz
coreboot-5005bb06c17461ef75cd1fef55c24dffaa05e580.zip
Unify use of post_code
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/arch/x86/init/crt0_romcc_epilogue.inc5
-rw-r--r--src/arch/x86/init/prologue.inc2
-rw-r--r--src/arch/x86/lib/c_start.S6
-rw-r--r--src/boot/hardwaremain.c12
-rw-r--r--src/boot/selfboot.c2
-rw-r--r--src/cpu/amd/model_gx2/cache_as_ram.inc5
-rw-r--r--src/cpu/amd/model_lx/cache_as_ram.inc5
-rw-r--r--src/cpu/amd/sc520/raminit.c6
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc5
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram.inc5
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc5
-rw-r--r--src/cpu/intel/model_6fx/cache_as_ram.inc5
-rw-r--r--src/cpu/via/car/cache_as_ram.inc5
-rw-r--r--src/cpu/x86/32bit/entry32.inc3
-rw-r--r--src/include/console/console.h1
-rw-r--r--src/include/console/post_codes.h351
-rw-r--r--src/include/cpu/amd/geode_post_code.h182
-rw-r--r--src/include/cpu/x86/post_code.h1
-rw-r--r--src/mainboard/amd/db800/romstage.c2
-rw-r--r--src/mainboard/amd/norwich/romstage.c2
-rw-r--r--src/mainboard/amd/rumba/romstage.c1
-rw-r--r--src/mainboard/artecgroup/dbe61/romstage.c2
-rw-r--r--src/mainboard/digitallogic/msm800sev/romstage.c3
-rw-r--r--src/mainboard/iei/pcisa-lx-800-r10/romstage.c2
-rw-r--r--src/mainboard/lippert/frontrunner/romstage.c1
-rw-r--r--src/mainboard/lippert/hurricane-lx/romstage.c2
-rw-r--r--src/mainboard/lippert/literunner-lx/romstage.c2
-rw-r--r--src/mainboard/lippert/roadrunner-lx/romstage.c2
-rw-r--r--src/mainboard/lippert/spacerunner-lx/romstage.c2
-rw-r--r--src/mainboard/pcengines/alix1c/romstage.c3
-rw-r--r--src/mainboard/pcengines/alix2d/romstage.c3
-rw-r--r--src/mainboard/traverse/geos/romstage.c3
-rw-r--r--src/mainboard/winent/pl6064/romstage.c2
-rw-r--r--src/mainboard/wyse/s50/romstage.c1
-rw-r--r--src/northbridge/amd/gx1/raminit.c12
-rw-r--r--src/northbridge/via/cx700/early_serial.c4
-rw-r--r--src/northbridge/via/vx800/early_serial.c4
-rw-r--r--src/southbridge/amd/cs5535/chipsetinit.c3
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c1
-rw-r--r--src/southbridge/via/vt8231/early_serial.c7
40 files changed, 408 insertions, 262 deletions
diff --git a/src/arch/x86/init/crt0_romcc_epilogue.inc b/src/arch/x86/init/crt0_romcc_epilogue.inc
index 3bd1b3699..b19f9687e 100644
--- a/src/arch/x86/init/crt0_romcc_epilogue.inc
+++ b/src/arch/x86/init/crt0_romcc_epilogue.inc
@@ -5,11 +5,12 @@
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*/
+#include <cpu/x86/post_code.h>
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* clear direction flag */
movl %ebp, %esi
@@ -20,7 +21,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/arch/x86/init/prologue.inc b/src/arch/x86/init/prologue.inc
index 8947f20de..b85c5c0fa 100644
--- a/src/arch/x86/init/prologue.inc
+++ b/src/arch/x86/init/prologue.inc
@@ -25,5 +25,5 @@
/* This is the entry code. The code in the .reset section jumps here. */
- post_code(0x01)
+ post_code(POST_RESET_VECTOR_CORRECT)
diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S
index 94ce4a70c..005ac33ee 100644
--- a/src/arch/x86/lib/c_start.S
+++ b/src/arch/x86/lib/c_start.S
@@ -14,7 +14,7 @@ _start:
movl %eax, %fs
movl %eax, %gs
- post_code(0x13) /* post 13 */
+ post_code(POST_ENTRY_C_START) /* post 13 */
/** clear stack */
cld
@@ -73,7 +73,7 @@ _start:
* bss is cleared. Now we call the main routine and
* let it do the rest.
*/
- post_code(0xfe) /* post fe */
+ post_code(POST_PRE_HARDWAREMAIN) /* post fe */
/* Restore the stack location */
movl %ebp, %esp
@@ -82,7 +82,7 @@ _start:
call hardwaremain
/* NOTREACHED */
.Lhlt:
- post_code(0xee) /* post ee */
+ post_code(POST_DEAD_CODE) /* post ee */
hlt
jmp .Lhlt
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 061bffdad..3d15b551c 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -57,18 +57,18 @@ void hardwaremain(int boot_complete)
{
struct lb_memory *lb_mem;
- post_code(0x80);
+ post_code(POST_ENTRY_RAMSTAGE);
/* console_init() MUST PRECEDE ALL printk()! */
console_init();
- post_code(0x39);
+ post_code(POST_CONSOLE_READY);
printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n",
coreboot_version, coreboot_extra_version, coreboot_build,
(boot_complete)?"rebooting":"booting");
- post_code(0x40);
+ post_code(POST_CONSOLE_BOOT_MSG);
/* If we have already booted attempt a hard reboot */
if (boot_complete) {
@@ -80,15 +80,15 @@ void hardwaremain(int boot_complete)
/* Find the devices we don't have hard coded knowledge about. */
dev_enumerate();
- post_code(0x66);
+ post_code(POST_DEVICE_ENUMERATION_COMPLETE);
/* Now compute and assign the bus resources. */
dev_configure();
- post_code(0x88);
+ post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
/* Now actually enable devices on the bus */
dev_enable();
/* And of course initialize devices on the bus */
dev_initialize();
- post_code(0x89);
+ post_code(POST_DEVICES_ENABLED);
#if CONFIG_WRITE_HIGH_TABLES == 1
cbmem_initialize();
diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index ac43e4aba..f8be72c77 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -553,7 +553,7 @@ static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
boot_successful();
printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry);
- post_code(0xfe);
+ post_code(POST_ENTER_ELF_BOOT);
/* Jump to kernel */
jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size);
diff --git a/src/cpu/amd/model_gx2/cache_as_ram.inc b/src/cpu/amd/model_gx2/cache_as_ram.inc
index 433576c73..0af2fdf48 100644
--- a/src/cpu/amd/model_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/model_gx2/cache_as_ram.inc
@@ -27,6 +27,7 @@
#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
#include <cpu/amd/gx2def.h>
+#include <cpu/x86/post_code.h>
/***************************************************************************
/**
/** DCacheSetup
@@ -184,7 +185,7 @@ done_cache_as_ram_main:
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
/* TODO For suspend/resume the cache will have to live between
* CONFIG_RAMBASE and CONFIG_RAMTOP
@@ -201,7 +202,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
index a2e8f87e6..a1d775d6d 100644
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -26,6 +26,7 @@
#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
#include <cpu/amd/lxdef.h>
+#include <cpu/x86/post_code.h>
/***************************************************************************
/**
/** DCacheSetup
@@ -210,7 +211,7 @@ done_cache_as_ram_main:
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
/* TODO For suspend/resume the cache will have to live between
* CONFIG_RAMBASE and CONFIG_RAMTOP
@@ -227,7 +228,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index e6232a8eb..2f7adae19 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -144,13 +144,13 @@ void setupsc520(void)
/* the 0x80 led should now be working*/
- outb(0xaa, 0x80);
+ post_code(0xaa);
#if 0
- /* wtf are 680 leds ... */
+ /* wtf are 680 leds ... *//* <-- WTF is this comment? */
par = (unsigned long *) 0xfffef0c4;
*par = 0x28000680;
/* well? */
- outb(0x55, 0x80);
+ post_code(0x55);
#endif
/* set the uart baud rate clocks to the normal 1.8432 MHz.*/
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 99c159977..3949a567c 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -24,6 +24,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
+#include <cpu/x86/post_code.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
@@ -364,7 +365,7 @@ lout:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@@ -375,7 +376,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index d7dba8bf1..e9820c9ae 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -229,7 +230,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@@ -240,7 +241,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index b077ff9a4..fc4947600 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -229,7 +230,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@@ -240,7 +241,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 373742932..a1b82675f 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -243,7 +244,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@@ -254,7 +255,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index fcd6c45e5..6303162cf 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -27,6 +27,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
+#include <console/post_codes.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE
@@ -261,7 +262,7 @@ testok:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@@ -272,7 +273,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index de3b6cdfa..740ea47bc 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -1,6 +1,7 @@
/* For starting coreboot in protected mode */
#include <arch/rom_segs.h>
+#include <cpu/x86/post_code.h>
.code32
@@ -51,7 +52,7 @@ __protected_start:
/* Save the BIST value */
movl %eax, %ebp
- post_code(0x10)
+ post_code(POST_ENTER_PROTECTED_MODE)
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 004ff44bc..d1797d760 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -22,6 +22,7 @@
#include <stdint.h>
#include <console/loglevel.h>
+#include <console/post_codes.h>
#ifndef __PRE_RAM__
void console_tx_byte(unsigned char byte);
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
new file mode 100644
index 000000000..f1c12b38e
--- /dev/null
+++ b/src/include/console/post_codes.h
@@ -0,0 +1,351 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file post_codes.h
+ *
+ * This aims to be a central point for POST codes used throughout coreboot.
+ * All POST codes should be declared here as macros, and post_code() should
+ * be used with the macros instead of hardcoded values. This allows us to
+ * quicly reference POST codes when nothing is working
+ *
+ * The format for a POST code macro is
+ * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED
+ * Lets's keep it at POST_* instead of POST_CODE_*
+ *
+ * This file is also included by early assembly files. Only use #define s;
+ * no function prototypes allowed here
+ *
+ * DOCUMENTATION:
+ * Please document any and all post codes using Doxygen style comments. We
+ * want to be able to generate a verbose enough documentation that is useful
+ * during debugging. Failure to do so will result in your patch being rejected
+ * without any explanation or effort on part of the maintainers.
+ *
+ */
+#ifndef POST_CODES_H
+#define POST_CODES_H
+
+/**
+ * \brief Entry into 'crt0.s'. reset code jumps to here
+ *
+ * First instruction that gets executed after the reset vector jumps.
+ * This indicates that the reset vector points to the correct code segment.
+ */
+#define POST_RESET_VECTOR_CORRECT 0x01
+
+/**
+ * \brief Entry into protected mode
+ *
+ * Preparing to enter protected mode. This is POSTed right before changing to
+ * protected mode.
+ */
+#define POST_ENTER_PROTECTED_MODE 0x10
+
+/**
+ * \brief Start copying coreboot to RAM with decompression if compressed
+ *
+ * POSTed before ramstage is about to be loaded into memory
+ */
+#define POST_PREPARE_RAMSTAGE 0x11
+
+/**
+ * \brief Copy/decompression finished; jumping to RAM
+ *
+ * This is called after ramstage is loaded in memory, and before
+ * the code jumps there. This represents the end of romstage.
+ */
+#define POST_RAMSTAGE_IS_PREPARED 0x12
+
+
+/**
+ * \brief Entry into c_start
+ *
+ * c_start.S is the first code executing in ramstage.
+ */
+#define POST_ENTRY_C_START 0x13
+
+/**
+ * \brief Entry into coreboot in hardwaremain (RAM)
+ *
+ * This is the first call in hardwaremain.c. If this code is POSTed, then
+ * ramstage has succesfully loaded and started executing.
+ */
+#define POST_ENTRY_RAMSTAGE 0x80
+
+/**
+ * \brief Console is initialized
+ *
+ * The console is initialized and is ready for usage
+ */
+#define POST_CONSOLE_READY 0x39
+
+/**
+ * \brief Console boot message succeeded
+ *
+ * First console message has been succesfully sent through the console backend
+ * driver.
+ */
+#define POST_CONSOLE_BOOT_MSG 0x40
+
+/**
+ * \brief Devices have been enumerated
+ *
+ * Bus scan, and device enumeration has completed.
+ */
+#define POST_DEVICE_ENUMERATION_COMPLETE 0x66
+
+/**
+ * \brief Devices have been configured
+ *
+ * Device confgration has completed.
+ */
+#define POST_DEVICE_CONFIGURATION_COMPLETE 0x88
+
+/**
+ * \brief Devices have been enabled
+ *
+ * Devices have been enabled.
+ */
+#define POST_DEVICES_ENABLED 0x89
+
+/**
+ * \brief Entry into elf boot
+ *
+ * This POST code is called right before invoking jmp_to_elf_entry()
+ * jmp_to_elf_entry() invokes the payload, and should never return
+ */
+#define POST_ENTER_ELF_BOOT 0xf8
+
+/**
+ * \brief Jumping to payload
+ *
+ * Called right before jumping to a payload. If the boot sequence stops with
+ * this code, chances are the payload freezes.
+ */
+#define POST_JUMPING_TO_PAYLOAD 0xf3
+
+/**
+ * \brief Not supposed to get here
+ *
+ * A function that should not have returned, returned
+ *
+ * Check the console output for details.
+ */
+#define POST_DEAD_CODE 0xee
+
+/**
+ * \brief Pre call to hardwaremain()
+ *
+ * POSTed right before hardwaremain is called from c_start.S
+ * TODO: Change this code to a lower number
+ */
+#define POST_PRE_HARDWAREMAIN 0xfe
+
+/**
+ * \brief Elfload fail or die() called
+ *
+ * Coreboot was not able to load the payload, no payload was detected
+ * or die() was called.
+ * \n
+ * If this code appears before entering ramstage, then most likely
+ * ramstage is corrupted, and reflashing of the ROM chip is needed.
+ * \n
+ * If this code appears after ramstage, there is a problem with the payload
+ * If the payload was built out-of-tree, check that it was compiled as
+ * a coreboot payload
+ * \n
+ * Check the console output to see exactly where the failure occured.
+ */
+#define POST_DIE 0xff
+
+
+/*
+ * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h
+ * They overlap with previous codes, and most are not even used
+ * Some maiboards still require them, but they are deprecated. We want to consolidate
+ * our own POST code structure with the codes above.
+ *
+ * standard AMD post definitions for the AMD Geode
+ */
+#define POST_Output_Port (0x080) /* port to write post codes to*/
+
+#define POST_preSioInit (0x000)
+#define POST_clockInit (0x001)
+#define POST_CPURegInit (0x002)
+#define POST_UNREAL (0x003)
+#define POST_CPUMemRegInit (0x004)
+#define POST_CPUTest (0x005)
+#define POST_memSetup (0x006)
+#define POST_memSetUpStack (0x007)
+#define POST_memTest (0x008)
+#define POST_shadowRom (0x009)
+#define POST_memRAMoptimize (0x00A)
+#define POST_cacheInit (0x00B)
+#define POST_northBridgeInit (0x00C)
+#define POST_chipsetInit (0x00D)
+#define POST_sioTest (0x00E)
+#define POST_pcATjunk (0x00F)
+
+#define POST_intTable (0x010)
+#define POST_memInfo (0x011)
+#define POST_romCopy (0x012)
+#define POST_PLLCheck (0x013)
+#define POST_keyboardInit (0x014)
+#define POST_cpuCacheOff (0x015)
+#define POST_BDAInit (0x016)
+#define POST_pciScan (0x017)
+#define POST_optionRomInit (0x018)
+#define POST_ResetLimits (0x019)
+#define POST_summary_screen (0x01A)
+#define POST_Boot (0x01B)
+#define POST_SystemPreInit (0x01C)
+#define POST_ClearRebootFlag (0x01D)
+#define POST_GLIUInit (0x01E)
+#define POST_BootFailed (0x01F)
+
+#define POST_CPU_ID (0x020)
+#define POST_COUNTERBROKEN (0x021)
+#define POST_DIFF_DIMMS (0x022)
+#define POST_WIGGLE_MEM_LINES (0x023)
+#define POST_NO_GLIU_DESC (0x024)
+#define POST_CPU_LCD_CHECK (0x025)
+#define POST_CPU_LCD_PASS (0x026)
+#define POST_CPU_LCD_FAIL (0x027)
+#define POST_CPU_STEPPING (0x028)
+#define POST_CPU_DM_BIST_FAILURE (0x029)
+#define POST_CPU_FLAGS (0x02A)
+#define POST_CHIPSET_ID (0x02B)
+#define POST_CHIPSET_ID_PASS (0x02C)
+#define POST_CHIPSET_ID_FAIL (0x02D)
+#define POST_CPU_ID_GOOD (0x02E)
+#define POST_CPU_ID_FAIL (0x02F)
+
+/* PCI config*/
+#define P80_PCICFG (0x030)
+
+/* PCI io*/
+#define P80_PCIIO (0x040)
+
+/* PCI memory*/
+#define P80_PCIMEM (0x050)
+
+/* SIO*/
+#define P80_SIO (0x060)
+
+/* Memory Setp*/
+#define P80_MEM_SETUP (0x070)
+#define POST_MEM_SETUP (0x070)
+#define ERROR_32BIT_DIMMS (0x071)
+#define POST_MEM_SETUP2 (0x072)
+#define POST_MEM_SETUP3 (0x073)
+#define POST_MEM_SETUP4 (0x074)
+#define POST_MEM_SETUP5 (0x075)
+#define POST_MEM_ENABLE (0x076)
+#define ERROR_NO_DIMMS (0x077)
+#define ERROR_DIFF_DIMMS (0x078)
+#define ERROR_BAD_LATENCY (0x079)
+#define ERROR_SET_PAGE (0x07A)
+#define ERROR_DENSITY_DIMM (0x07B)
+#define ERROR_UNSUPPORTED_DIMM (0x07C)
+#define ERROR_BANK_SET (0x07D)
+#define POST_MEM_SETUP_GOOD (0x07E)
+#define POST_MEM_SETUP_FAIL (0x07F)
+
+#define POST_UserPreInit (0x080)
+#define POST_UserPostInit (0x081)
+#define POST_Equipment_check (0x082)
+#define POST_InitNVRAMBX (0x083)
+#define POST_NoPIRTable (0x084)
+#define POST_ChipsetFingerPrintPass (0x085)
+#define POST_ChipsetFingerPrintFail (0x086)
+#define POST_CPU_IM_TAG_BIST_FAILURE (0x087)
+#define POST_CPU_IM_DATA_BIST_FAILURE (0x088)
+#define POST_CPU_FPU_BIST_FAILURE (0x089)
+#define POST_CPU_BTB_BIST_FAILURE (0x08A)
+#define POST_CPU_EX_BIST_FAILURE (0x08B)
+#define POST_Chipset_PI_Test_Fail (0x08C)
+#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D)
+#define POST_BIT_CLK_Fail (0x08E)
+
+#define POST_STACK_SETUP (0x090)
+#define POST_CPU_PF_BIST_FAILURE (0x091)
+#define POST_CPU_L2_BIST_FAILURE (0x092)
+#define POST_CPU_GLCP_BIST_FAILURE (0x093)
+#define POST_CPU_DF_BIST_FAILURE (0x094)
+#define POST_CPU_VG_BIST_FAILURE (0x095)
+#define POST_CPU_VIP_BIST_FAILURE (0x096)
+#define POST_STACK_SETUP_PASS (0x09E)
+#define POST_STACK_SETUP_FAIL (0x09F)
+
+#define POST_PLL_INIT (0x0A0)
+#define POST_PLL_MANUAL (0x0A1)
+#define POST_PLL_STRAP (0x0A2)
+#define POST_PLL_RESET_FAIL (0x0A3)
+#define POST_PLL_PCI_FAIL (0x0A4)
+#define POST_PLL_MEM_FAIL (0x0A5)
+#define POST_PLL_CPU_VER_FAIL (0x0A6)
+
+#define POST_MEM_TESTMEM (0x0B0)
+#define POST_MEM_TESTMEM1 (0x0B1)
+#define POST_MEM_TESTMEM2 (0x0B2)
+#define POST_MEM_TESTMEM3 (0x0B3)
+#define POST_MEM_TESTMEM4 (0x0B4)
+#define POST_MEM_TESTMEM_PASS (0x0BE)
+#define POST_MEM_TESTMEM_FAIL (0x0BF)
+
+#define POST_SECUROM_SECBOOT_START (0x0C0)
+#define POST_SECUROM_BOOTSRCSETUP (0x0C1)
+#define POST_SECUROM_REMAP_FAIL (0x0C2)
+#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3)
+#define POST_SECUROM_DCACHESETUP (0x0C4)
+#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5)
+#define POST_SECUROM_ICACHESETUP (0x0C6)
+#define POST_SECUROM_DESCRIPTORSETUP (0x0C7)
+#define POST_SECUROM_DCACHESETUPBIOS (0x0C8)
+#define POST_SECUROM_PLATFORMSETUP (0x0C9)
+#define POST_SECUROM_SIGCHECKBIOS (0x0CA)
+#define POST_SECUROM_ICACHESETUPBIOS (0x0CB)
+#define POST_SECUROM_PASS (0x0CC)
+#define POST_SECUROM_FAIL (0x0CD)
+
+#define POST_RCONFInitError (0x0CE)
+#define POST_CacheInitError (0x0CF)
+
+#define POST_ROM_PREUNCOMPRESS (0x0D0)
+#define POST_ROM_UNCOMPRESS (0x0D1)
+#define POST_ROM_SMM_INIT (0x0D2)
+#define POST_ROM_VID_BIOS (0x0D3)
+#define POST_ROM_LCDINIT (0x0D4)
+#define POST_ROM_SPLASH (0x0D5)
+#define POST_ROM_HDDINIT (0x0D6)
+#define POST_ROM_SYS_INIT (0x0D7)
+#define POST_ROM_DMM_INIT (0x0D8)
+#define POST_ROM_TVINIT (0x0D9)
+#define POST_ROM_POSTUNCOMPRESS (0x0DE)
+
+#define P80_CHIPSET_INIT (0x0E0)
+#define POST_PreChipsetInit (0x0E1)
+#define POST_LateChipsetInit (0x0E2)
+#define POST_NORTHB_INIT (0x0E8)
+
+#define POST_INTR_SEG_JUMP (0x0F0)
+
+#endif /* THE_ALMIGHTY_POST_CODES_H */
diff --git a/src/include/cpu/amd/geode_post_code.h b/src/include/cpu/amd/geode_post_code.h
index 5ced316eb..e69de29bb 100644
--- a/src/include/cpu/amd/geode_post_code.h
+++ b/src/include/cpu/amd/geode_post_code.h
@@ -1,182 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* standard AMD post definitions -- might as well use them. */
-#define POST_Output_Port (0x080) /* port to write post codes to*/
-
-#define POST_preSioInit (0x000)
-#define POST_clockInit (0x001)
-#define POST_CPURegInit (0x002)
-#define POST_UNREAL (0x003)
-#define POST_CPUMemRegInit (0x004)
-#define POST_CPUTest (0x005)
-#define POST_memSetup (0x006)
-#define POST_memSetUpStack (0x007)
-#define POST_memTest (0x008)
-#define POST_shadowRom (0x009)
-#define POST_memRAMoptimize (0x00A)
-#define POST_cacheInit (0x00B)
-#define POST_northBridgeInit (0x00C)
-#define POST_chipsetInit (0x00D)
-#define POST_sioTest (0x00E)
-#define POST_pcATjunk (0x00F)
-
-#define POST_intTable (0x010)
-#define POST_memInfo (0x011)
-#define POST_romCopy (0x012)
-#define POST_PLLCheck (0x013)
-#define POST_keyboardInit (0x014)
-#define POST_cpuCacheOff (0x015)
-#define POST_BDAInit (0x016)
-#define POST_pciScan (0x017)
-#define POST_optionRomInit (0x018)
-#define POST_ResetLimits (0x019)
-#define POST_summary_screen (0x01A)
-#define POST_Boot (0x01B)
-#define POST_SystemPreInit (0x01C)
-#define POST_ClearRebootFlag (0x01D)
-#define POST_GLIUInit (0x01E)
-#define POST_BootFailed (0x01F)
-
-#define POST_CPU_ID (0x020)
-#define POST_COUNTERBROKEN (0x021)
-#define POST_DIFF_DIMMS (0x022)
-#define POST_WIGGLE_MEM_LINES (0x023)
-#define POST_NO_GLIU_DESC (0x024)
-#define POST_CPU_LCD_CHECK (0x025)
-#define POST_CPU_LCD_PASS (0x026)
-#define POST_CPU_LCD_FAIL (0x027)
-#define POST_CPU_STEPPING (0x028)
-#define POST_CPU_DM_BIST_FAILURE (0x029)
-#define POST_CPU_FLAGS (0x02A)
-#define POST_CHIPSET_ID (0x02B)
-#define POST_CHIPSET_ID_PASS (0x02C)
-#define POST_CHIPSET_ID_FAIL (0x02D)
-#define POST_CPU_ID_GOOD (0x02E)
-#define POST_CPU_ID_FAIL (0x02F)
-
-/* PCI config*/
-#define P80_PCICFG (0x030)
-
-/* PCI io*/
-#define P80_PCIIO (0x040)
-
-/* PCI memory*/
-#define P80_PCIMEM (0x050)
-
-/* SIO*/
-#define P80_SIO (0x060)
-
-/* Memory Setp*/
-#define P80_MEM_SETUP (0x070)
-#define POST_MEM_SETUP (0x070)
-#define ERROR_32BIT_DIMMS (0x071)
-#define POST_MEM_SETUP2 (0x072)
-#define POST_MEM_SETUP3 (0x073)
-#define POST_MEM_SETUP4 (0x074)
-#define POST_MEM_SETUP5 (0x075)
-#define POST_MEM_ENABLE (0x076)
-#define ERROR_NO_DIMMS (0x077)
-#define ERROR_DIFF_DIMMS (0x078)
-#define ERROR_BAD_LATENCY (0x079)
-#define ERROR_SET_PAGE (0x07A)
-#define ERROR_DENSITY_DIMM (0x07B)
-#define ERROR_UNSUPPORTED_DIMM (0x07C)
-#define ERROR_BANK_SET (0x07D)
-#define POST_MEM_SETUP_GOOD (0x07E)
-#define POST_MEM_SETUP_FAIL (0x07F)
-
-#define POST_UserPreInit (0x080)
-#define POST_UserPostInit (0x081)
-#define POST_Equipment_check (0x082)
-#define POST_InitNVRAMBX (0x083)
-#define POST_NoPIRTable (0x084)
-#define POST_ChipsetFingerPrintPass (0x085)
-#define POST_ChipsetFingerPrintFail (0x086)
-#define POST_CPU_IM_TAG_BIST_FAILURE (0x087)
-#define POST_CPU_IM_DATA_BIST_FAILURE (0x088)
-#define POST_CPU_FPU_BIST_FAILURE (0x089)
-#define POST_CPU_BTB_BIST_FAILURE (0x08A)
-#define POST_CPU_EX_BIST_FAILURE (0x08B)
-#define POST_Chipset_PI_Test_Fail (0x08C)
-#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D)
-#define POST_BIT_CLK_Fail (0x08E)
-
-#define POST_STACK_SETUP (0x090)
-#define POST_CPU_PF_BIST_FAILURE (0x091)
-#define POST_CPU_L2_BIST_FAILURE (0x092)
-#define POST_CPU_GLCP_BIST_FAILURE (0x093)
-#define POST_CPU_DF_BIST_FAILURE (0x094)
-#define POST_CPU_VG_BIST_FAILURE (0x095)
-#define POST_CPU_VIP_BIST_FAILURE (0x096)
-#define POST_STACK_SETUP_PASS (0x09E)
-#define POST_STACK_SETUP_FAIL (0x09F)
-
-#define POST_PLL_INIT (0x0A0)
-#define POST_PLL_MANUAL (0x0A1)
-#define POST_PLL_STRAP (0x0A2)
-#define POST_PLL_RESET_FAIL (0x0A3)
-#define POST_PLL_PCI_FAIL (0x0A4)
-#define POST_PLL_MEM_FAIL (0x0A5)
-#define POST_PLL_CPU_VER_FAIL (0x0A6)
-
-#define POST_MEM_TESTMEM (0x0B0)
-#define POST_MEM_TESTMEM1 (0x0B1)
-#define POST_MEM_TESTMEM2 (0x0B2)
-#define POST_MEM_TESTMEM3 (0x0B3)
-#define POST_MEM_TESTMEM4 (0x0B4)
-#define POST_MEM_TESTMEM_PASS (0x0BE)
-#define POST_MEM_TESTMEM_FAIL (0x0BF)
-
-#define POST_SECUROM_SECBOOT_START (0x0C0)
-#define POST_SECUROM_BOOTSRCSETUP (0x0C1)
-#define POST_SECUROM_REMAP_FAIL (0x0C2)
-#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3)
-#define POST_SECUROM_DCACHESETUP (0x0C4)
-#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5)
-#define POST_SECUROM_ICACHESETUP (0x0C6)
-#define POST_SECUROM_DESCRIPTORSETUP (0x0C7)
-#define POST_SECUROM_DCACHESETUPBIOS (0x0C8)
-#define POST_SECUROM_PLATFORMSETUP (0x0C9)
-#define POST_SECUROM_SIGCHECKBIOS (0x0CA)
-#define POST_SECUROM_ICACHESETUPBIOS (0x0CB)
-#define POST_SECUROM_PASS (0x0CC)
-#define POST_SECUROM_FAIL (0x0CD)
-
-#define POST_RCONFInitError (0x0CE)
-#define POST_CacheInitError (0x0CF)
-
-#define POST_ROM_PREUNCOMPRESS (0x0D0)
-#define POST_ROM_UNCOMPRESS (0x0D1)
-#define POST_ROM_SMM_INIT (0x0D2)
-#define POST_ROM_VID_BIOS (0x0D3)
-#define POST_ROM_LCDINIT (0x0D4)
-#define POST_ROM_SPLASH (0x0D5)
-#define POST_ROM_HDDINIT (0x0D6)
-#define POST_ROM_SYS_INIT (0x0D7)
-#define POST_ROM_DMM_INIT (0x0D8)
-#define POST_ROM_TVINIT (0x0D9)
-#define POST_ROM_POSTUNCOMPRESS (0x0DE)
-
-#define P80_CHIPSET_INIT (0x0E0)
-#define POST_PreChipsetInit (0x0E1)
-#define POST_LateChipsetInit (0x0E2)
-#define POST_NORTHB_INIT (0x0E8)
-
-#define POST_INTR_SEG_JUMP (0x0F0)
diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h
index 0fed2aa05..20b87c6ca 100644
--- a/src/include/cpu/x86/post_code.h
+++ b/src/include/cpu/x86/post_code.h
@@ -1,4 +1,5 @@
+#include <console/post_codes.h>
#define post_code(value) \
movb $value, %al; \
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index a811cd984..60ed7c712 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -28,7 +28,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -56,7 +55,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
void main(unsigned long bist)
{
- post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 7350c440c..d38507477 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -28,7 +28,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -53,7 +52,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
void main(unsigned long bist)
{
- post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index 7da3647c3..b81f386f3 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -8,7 +8,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h>
-#include <cpu/amd/geode_post_code.h>
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 4df61a267..465fb7dd6 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -29,7 +29,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "spd_table.h"
#include <spd.h>
@@ -68,7 +67,6 @@ static int spd_read_byte(unsigned device, unsigned address)
void main(unsigned long bist)
{
- post_code(0x01);
msr_t msr;
static const struct mem_controller memctrl[] = {
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index a68e4fc7f..f043ee857 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -9,7 +9,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -37,7 +36,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void main(unsigned long bist)
{
- post_code(0x01);
static const struct mem_controller memctrl [] = {
{.channel0 = {DIMM0, DIMM1}}
@@ -79,7 +77,6 @@ void main(unsigned long bist)
We use method 1 on Norwich.
*/
post_code(0x02);
- print_err("POST 02\n");
__asm__("wbinvd\n");
print_err("Past wbinvd\n");
/* we are finding the return does not work on this board. Explicitly call the label that is
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index b5dcf22a3..57d51e37a 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -28,7 +28,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -60,7 +59,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
void main(unsigned long bist)
{
- post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index 3047ceb02..413b86aec 100644
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -9,7 +9,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5535/cs5535.h"
#include "southbridge/amd/cs5535/early_smbus.c"
#include "southbridge/amd/cs5535/early_setup.c"
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index e0157abf3..50b49cb37 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -31,7 +31,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -118,7 +117,6 @@ static void mb_gpio_init(void)
void main(unsigned long bist)
{
- post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 8c7d50622..31720f4eb 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -32,7 +32,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
@@ -161,7 +160,6 @@ static void mb_gpio_init(void)
void main(unsigned long bist)
{
int err;
- post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 413e1f04a..94eb28565 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -31,7 +31,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -93,7 +92,6 @@ static void mb_gpio_init(void)
void main(unsigned long bist)
{
- post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index cb2e27db7..bb104e203 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -32,7 +32,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
@@ -158,7 +157,6 @@ static void mb_gpio_init(void)
void main(unsigned long bist)
{
int err;
- post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 68f6f84b9..9806ff427 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -30,7 +30,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -118,8 +117,6 @@ void main(unsigned long bist)
{.channel0 = {DIMM0}},
};
- post_code(0x01);
-
SystemPreInit();
msr_init();
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 1a0acf238..308066dca 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -30,7 +30,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -142,8 +141,6 @@ void main(unsigned long bist)
{.channel0 = {DIMM0}},
};
- post_code(0x01);
-
SystemPreInit();
msr_init();
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index 07962d33f..44623db50 100644
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -29,7 +29,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -54,8 +53,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
void main(unsigned long bist)
{
- post_code(0x01);
-
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index 7efb83ff3..a3c92346d 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -30,7 +30,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -58,7 +57,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
void main(unsigned long bist)
{
- post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index 686587753..a5feddb56 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -29,7 +29,6 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/gx2def.h>
-#include <cpu/amd/geode_post_code.h>
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
diff --git a/src/northbridge/amd/gx1/raminit.c b/src/northbridge/amd/gx1/raminit.c
index 8525ce4d1..aa07f49e8 100644
--- a/src/northbridge/amd/gx1/raminit.c
+++ b/src/northbridge/amd/gx1/raminit.c
@@ -46,12 +46,12 @@ void do_refresh(void)
{
unsigned int tval, i;
- outb(0x71, 0x80);
+ post_code(0x71);
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
tval |= RFSHTST;
for(i=0; i>NUM_REFRESH; i++)
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
- outb(0x72, 0x80);
+ post_code(0x72);
}
@@ -59,7 +59,7 @@ void enable_dimm(void)
{
unsigned int tval, i;
- outb(0x73, 0x80);
+ post_code(0x73);
/* start SDCLCK's */
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
@@ -101,7 +101,7 @@ unsigned int tval, i;
for(i=0; i<2000; i++)
outb(0, 0xed);
- outb(0x74, 0x80);
+ post_code(0x74);
}
static unsigned int size_dimm(int dimm_shift)
@@ -321,7 +321,7 @@ static void sdram_init(void)
unsigned int mem_config = 0x00700070;
print_debug("Setting up default parameters for memory\n");
- outb(0x70, 0x80);
+ post_code(0x70);
setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */
@@ -350,5 +350,5 @@ unsigned int mem_config = 0x00700070;
setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config);
enable_dimm();
- outb(0x7e, 0x80);
+ post_code(0x7e);
}
diff --git a/src/northbridge/via/cx700/early_serial.c b/src/northbridge/via/cx700/early_serial.c
index 503ebbb05..582570772 100644
--- a/src/northbridge/via/cx700/early_serial.c
+++ b/src/northbridge/via/cx700/early_serial.c
@@ -47,7 +47,7 @@ static void cx700_writesioword(u16 reg, u16 val)
static void enable_cx700_serial(void)
{
- outb(6, 0x80);
+ post_code(0x06);
// WTH?
outb(0x03, 0x22);
@@ -98,5 +98,5 @@ static void enable_cx700_serial(void)
// should be done. Dump a char for fun.
cx700_writesiobyte(0x3f8, 48);
- outb(7, 0x80);
+ post_code(0x07);
}
diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c
index f46341ff1..73e51ee81 100644
--- a/src/northbridge/via/vx800/early_serial.c
+++ b/src/northbridge/via/vx800/early_serial.c
@@ -55,7 +55,7 @@ static void vx800_writesioword(uint16_t reg, uint16_t val)
void enable_vx800_serial(void)
{
- outb(6, 0x80);
+ post_code(0x06);
outb(0x03, 0x22);
//pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e);
@@ -97,5 +97,5 @@ void enable_vx800_serial(void)
vx800_writesiobyte(0x3f9, 0xf);
// should be done. Dump a char for fun.
vx800_writesiobyte(0x3f8, 48);
- outb(7, 0x80);
+ post_code(0x07);
}
diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c
index 0e37fcc7e..2fceefa5e 100644
--- a/src/southbridge/amd/cs5535/chipsetinit.c
+++ b/src/southbridge/amd/cs5535/chipsetinit.c
@@ -10,7 +10,6 @@
#include "chip.h"
#include "northbridge/amd/gx2/northbridge.h"
#include <cpu/amd/gx2def.h>
-#include <cpu/amd/geode_post_code.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#include "southbridge/amd/cs5535/cs5535.h"
@@ -277,7 +276,7 @@ chipsetinit(void)
return;
}
- outb( P80_CHIPSET_INIT, 0x80);
+ post_code(P80_CHIPSET_INIT);
ChipsetGeodeLinkInit();
#ifdef UNUSED_CODE
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index a2ac44647..872de3688 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -30,7 +30,6 @@
#include <pc80/i8259.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/vr.h>
-#include <cpu/amd/geode_post_code.h>
#include <stdlib.h>
#include "chip.h"
#include "cs5536.h"
diff --git a/src/southbridge/via/vt8231/early_serial.c b/src/southbridge/via/vt8231/early_serial.c
index af5a7729e..a0aec65f5 100644
--- a/src/southbridge/via/vt8231/early_serial.c
+++ b/src/southbridge/via/vt8231/early_serial.c
@@ -1,3 +1,4 @@
+#include <console/console.h>
/*
* Enable the serial evices on the VIA
*/
@@ -33,11 +34,11 @@ static void enable_vt8231_serial(void)
{
uint8_t c;
device_t dev;
- outb(6, 0x80);
+ post_code(0x06);
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
if (dev == PCI_DEV_INVALID) {
- outb(7, 0x80);
+ post_code(0x07);
die("Serial controller not found\n");
}
@@ -47,7 +48,7 @@ static void enable_vt8231_serial(void)
c = pci_read_config8(dev, 0x50);
c |= 6;
pci_write_config8(dev, 0x50, c);
- outb(2, 0x80);
+ post_code(0x02);
// now go ahead and set up com1.
// set address
vt8231_writesuper(0xf4, 0xfe);