aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTom Warren <twarren@nvidia.com>2014-07-16 09:03:45 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-03-13 00:04:03 +0100
commit31818c98afae06ba77df383bfa013f9ede16430d (patch)
treec24c1dbd7a093bd3d22063f0dcd0f71926f8a3bb
parent01dde90eb9c070018fc11b007159c8d130b2809d (diff)
downloadcoreboot-31818c98afae06ba77df383bfa013f9ede16430d.tar.gz
coreboot-31818c98afae06ba77df383bfa013f9ede16430d.tar.xz
coreboot-31818c98afae06ba77df383bfa013f9ede16430d.zip
ryu: Add support for full LPDDR3 SDRAM BCT init via BootROM
Once LPDDR3 init is supported in the ryu romstage, this can be reverted. Note that this 528MHz BCT has been pre-qualed by NVIDIA AE's, but will be updated as more tuning is done. BUG=none BRANCH=none TEST=Builds, BCT is in binary, but I have no HW here to test on Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe Reviewed-on: http://review.coreboot.org/8643 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/mainboard/google/rush_ryu/bct/Makefile.inc4
-rw-r--r--src/mainboard/google/rush_ryu/bct/sdram-ryu-4GB-528-Micron-full.cfg1388
-rw-r--r--src/soc/nvidia/tegra132/Kconfig6
-rw-r--r--src/soc/nvidia/tegra132/romstage.c6
4 files changed, 1402 insertions, 2 deletions
diff --git a/src/mainboard/google/rush_ryu/bct/Makefile.inc b/src/mainboard/google/rush_ryu/bct/Makefile.inc
index e274fa31d..09aa562b0 100644
--- a/src/mainboard/google/rush_ryu/bct/Makefile.inc
+++ b/src/mainboard/google/rush_ryu/bct/Makefile.inc
@@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
-## Copyright 2013 Google Inc.
+## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -21,6 +21,8 @@ bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_EMMC) += emmc.cfg
bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_SPI) += spi.cfg
bct-cfg-y += odmdata.cfg
bct-cfg-y += jtag.cfg
+#NOTE: When full LPDDR3 SDRAM config is done in bootblock, remove this
+bct-cfg-$(CONFIG_BOOTROM_SDRAM_INIT) += sdram-ryu-4GB-528-Micron-full.cfg
# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg".
diff --git a/src/mainboard/google/rush_ryu/bct/sdram-ryu-4GB-528-Micron-full.cfg b/src/mainboard/google/rush_ryu/bct/sdram-ryu-4GB-528-Micron-full.cfg
new file mode 100644
index 000000000..fb137c1bc
--- /dev/null
+++ b/src/mainboard/google/rush_ryu/bct/sdram-ryu-4GB-528-Micron-full.cfg
@@ -0,0 +1,1388 @@
+# CFG Version 01 Samsung K4E6E304EE-EGCF (using Micron part)
+# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command:
+# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_528MHz_emc_reg.txt 1.89394
+# -o A44_64_528_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6
+# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.89 ns (528.00 MHz)
+# bkv file: A44_528MHz_emc_reg.txt
+SDRAM[0].MemoryType = NvBootMemoryType_LpDdr2;
+SDRAM[0].PllMInputDivider = 0x00000001;
+SDRAM[0].PllMFeedbackDivider = 0x0000002c;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].PllMSetupControl = 0x00000000;
+SDRAM[0].PllMSelectDiv2 = 0x00000000;
+SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
+SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
+SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
+SDRAM[0].PllMKCP = 0x00000000;
+SDRAM[0].PllMKVCO = 0x00000000;
+SDRAM[0].EmcBctSpare0 = 0x00000000;
+SDRAM[0].EmcBctSpare1 = 0x00000000;
+SDRAM[0].EmcBctSpare2 = 0x00000000;
+SDRAM[0].EmcBctSpare3 = 0x00000000;
+SDRAM[0].EmcBctSpare4 = 0x00000000;
+SDRAM[0].EmcBctSpare5 = 0x00000000;
+SDRAM[0].EmcBctSpare6 = 0x00000000;
+SDRAM[0].EmcBctSpare7 = 0x00000000;
+SDRAM[0].EmcBctSpare8 = 0x00000000;
+SDRAM[0].EmcBctSpare9 = 0x00000000;
+SDRAM[0].EmcBctSpare10 = 0x00000000;
+SDRAM[0].EmcBctSpare11 = 0x00000000;
+SDRAM[0].EmcClockSource = 0x80000000;
+SDRAM[0].EmcAutoCalInterval = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig = 0xa1430000;
+SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
+SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
+SDRAM[0].EmcAutoCalWait = 0x00000190;
+SDRAM[0].EmcAdrCfg = 0x00000001;
+SDRAM[0].EmcPinProgramWait = 0x00000000;
+SDRAM[0].EmcPinExtraWait = 0x00000000;
+SDRAM[0].EmcTimingControlWait = 0x00000000;
+SDRAM[0].EmcRc = 0x0000001f;
+SDRAM[0].EmcRfc = 0x00000044;
+SDRAM[0].EmcRfcSlr = 0x00000000;
+SDRAM[0].EmcRas = 0x00000016;
+SDRAM[0].EmcRp = 0x00000009;
+SDRAM[0].EmcR2r = 0x00000000;
+SDRAM[0].EmcW2w = 0x00000000;
+SDRAM[0].EmcR2w = 0x0000000a;
+SDRAM[0].EmcW2r = 0x00000009;
+SDRAM[0].EmcR2p = 0x00000003;
+SDRAM[0].EmcW2p = 0x0000000d;
+SDRAM[0].EmcRdRcd = 0x00000009;
+SDRAM[0].EmcWrRcd = 0x00000009;
+SDRAM[0].EmcRrd = 0x00000005;
+SDRAM[0].EmcRext = 0x00000004;
+SDRAM[0].EmcWext = 0x00000000;
+SDRAM[0].EmcWdv = 0x00000002;
+SDRAM[0].EmcWdvMask = 0x00000002;
+SDRAM[0].EmcQUse = 0x00000008;
+SDRAM[0].EmcQuseWidth = 0x00000003;
+SDRAM[0].EmcIbdly = 0x00000000;
+SDRAM[0].EmcEInput = 0x00000003;
+SDRAM[0].EmcEInputDuration = 0x0000000a;
+SDRAM[0].EmcPutermExtra = 0x00050000;
+SDRAM[0].EmcPutermWidth = 0x00000004;
+SDRAM[0].EmcPutermAdj = 0x00000000;
+SDRAM[0].EmcCdbCntl1 = 0x00000000;
+SDRAM[0].EmcCdbCntl2 = 0x00000000;
+SDRAM[0].EmcCdbCntl3 = 0x00000000;
+SDRAM[0].EmcQRst = 0x00000002;
+SDRAM[0].EmcQSafe = 0x00000011;
+SDRAM[0].EmcRdv = 0x00000015;
+SDRAM[0].EmcRdvMask = 0x00000017;
+SDRAM[0].EmcQpop = 0x0000000d;
+SDRAM[0].EmcCtt = 0x00000000;
+SDRAM[0].EmcCttDuration = 0x00000004;
+SDRAM[0].EmcRefresh = 0x000007cd;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt = 0x000001f3;
+SDRAM[0].EmcPdEx2Wr = 0x00000003;
+SDRAM[0].EmcPdEx2Rd = 0x00000003;
+SDRAM[0].EmcPChg2Pden = 0x00000009;
+SDRAM[0].EmcAct2Pden = 0x00000000;
+SDRAM[0].EmcAr2Pden = 0x00000001;
+SDRAM[0].EmcRw2Pden = 0x00000011;
+SDRAM[0].EmcTxsr = 0x0000004a;
+SDRAM[0].EmcTxsrDll = 0x0000004a;
+SDRAM[0].EmcTcke = 0x00000004;
+SDRAM[0].EmcTckesr = 0x00000008;
+SDRAM[0].EmcTpd = 0x00000004;
+SDRAM[0].EmcTfaw = 0x00000019;
+SDRAM[0].EmcTrpab = 0x0000000c;
+SDRAM[0].EmcTClkStable = 0x00000003;
+SDRAM[0].EmcTClkStop = 0x00000003;
+SDRAM[0].EmcTRefBw = 0x00000895;
+SDRAM[0].EmcFbioCfg5 = 0x1363a096;
+SDRAM[0].EmcFbioCfg6 = 0x00000000;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcCfgRsv = 0xff00ff00;
+SDRAM[0].EmcMrs = 0x00000000;
+SDRAM[0].EmcEmrs = 0x00000000;
+SDRAM[0].EmcEmrs2 = 0x00000000;
+SDRAM[0].EmcEmrs3 = 0x00000000;
+SDRAM[0].EmcMrw1 = 0x000100c3;
+SDRAM[0].EmcMrw2 = 0x00020006;
+SDRAM[0].EmcMrw3 = 0x00030001;
+SDRAM[0].EmcMrw4 = 0x800b0000;
+SDRAM[0].EmcMrwExtra = 0x000100c3;
+SDRAM[0].EmcWarmBootMrwExtra = 0x00020006;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x003f00fc;
+SDRAM[0].EmcMrwResetNInitWait = 0x0000000a;
+SDRAM[0].EmcMrsWaitCnt = 0x02100013;
+SDRAM[0].EmcMrsWaitCnt2 = 0x02100013;
+SDRAM[0].EmcCfg = 0xf3300000;
+SDRAM[0].EmcCfg2 = 0x0000089f;
+SDRAM[0].EmcCfgPipe = 0x000042a0;
+SDRAM[0].EmcDbg = 0x01000c00;
+SDRAM[0].EmcCmdQ = 0x10004408;
+SDRAM[0].EmcMc2EmcQ = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl = 0x800010b3;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[0].EmcCfgDigDll = 0xe01200b9;
+SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[0].EmcDevSelect = 0x00000000;
+SDRAM[0].EmcSelDpdCtrl = 0x0004001c;
+SDRAM[0].EmcDllXformDqs0 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs1 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs2 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs3 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs4 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs5 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs6 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs7 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs8 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs9 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs10 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs11 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs12 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs13 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs14 = 0x007f400a;
+SDRAM[0].EmcDllXformDqs15 = 0x007f400a;
+SDRAM[0].EmcDllXformQUse0 = 0x00000000;
+SDRAM[0].EmcDllXformQUse1 = 0x00000000;
+SDRAM[0].EmcDllXformQUse2 = 0x00000000;
+SDRAM[0].EmcDllXformQUse3 = 0x00000000;
+SDRAM[0].EmcDllXformQUse4 = 0x00000000;
+SDRAM[0].EmcDllXformQUse5 = 0x00000000;
+SDRAM[0].EmcDllXformQUse6 = 0x00000000;
+SDRAM[0].EmcDllXformQUse7 = 0x00000000;
+SDRAM[0].EmcDllXformAddr0 = 0x00024000;
+SDRAM[0].EmcDllXformAddr1 = 0x00024000;
+SDRAM[0].EmcDllXformAddr2 = 0x00000006;
+SDRAM[0].EmcDllXformAddr3 = 0x00024000;
+SDRAM[0].EmcDllXformAddr4 = 0x00024000;
+SDRAM[0].EmcDllXformAddr5 = 0x00000006;
+SDRAM[0].EmcDllXformQUse8 = 0x00000000;
+SDRAM[0].EmcDllXformQUse9 = 0x00000000;
+SDRAM[0].EmcDllXformQUse10 = 0x00000000;
+SDRAM[0].EmcDllXformQUse11 = 0x00000000;
+SDRAM[0].EmcDllXformQUse12 = 0x00000000;
+SDRAM[0].EmcDllXformQUse13 = 0x00000000;
+SDRAM[0].EmcDllXformQUse14 = 0x00000000;
+SDRAM[0].EmcDllXformQUse15 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs0 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs1 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs2 = 0x00000008;
+SDRAM[0].EmcDliTrimTxDqs3 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs4 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs5 = 0x00000008;
+SDRAM[0].EmcDliTrimTxDqs6 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs7 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs8 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs9 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs10 = 0x00000008;
+SDRAM[0].EmcDliTrimTxDqs11 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs12 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs13 = 0x00000008;
+SDRAM[0].EmcDliTrimTxDqs14 = 0x0000000b;
+SDRAM[0].EmcDliTrimTxDqs15 = 0x0000000b;
+SDRAM[0].EmcDllXformDq0 = 0x0000000c;
+SDRAM[0].EmcDllXformDq1 = 0x0000000c;
+SDRAM[0].EmcDllXformDq2 = 0x0000000c;
+SDRAM[0].EmcDllXformDq3 = 0x0000000c;
+SDRAM[0].EmcDllXformDq4 = 0x0000000c;
+SDRAM[0].EmcDllXformDq5 = 0x0000000c;
+SDRAM[0].EmcDllXformDq6 = 0x0000000c;
+SDRAM[0].EmcDllXformDq7 = 0x0000000c;
+SDRAM[0].WarmBootWait = 0x00000001;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalInterval = 0x00064000;
+SDRAM[0].EmcZcalWaitCnt = 0x00000034;
+SDRAM[0].EmcZcalMrwCmd = 0x000a0056;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcZcalInitDev0 = 0x840a00ff;
+SDRAM[0].EmcZcalInitDev1 = 0x440a00ff;
+SDRAM[0].EmcZcalInitWait = 0x00000001;
+SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
+SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcMrsExtra = 0x00000000;
+SDRAM[0].EmcWarmBootMrsExtra = 0x00000000;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[0].EmcDdr2Wait = 0x00000000;
+SDRAM[0].EmcClkenOverride = 0x00000000;
+SDRAM[0].McDisExtraSnapLevels = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[0].PmcVddpSel = 0x00000001;
+SDRAM[0].PmcVddpSelWait = 0x00000002;
+SDRAM[0].PmcDdrPwr = 0x00000003;
+SDRAM[0].PmcDdrCfg = 0x00001000;
+SDRAM[0].PmcIoDpd3Req = 0x4ffefef7;
+SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
+SDRAM[0].PmcRegShort = 0x0000330f;
+SDRAM[0].PmcNoIoPower = 0x00000000;
+SDRAM[0].PmcPorDpdCtrlWait = 0x00000001;
+SDRAM[0].EmcXm2CmdPadCtrl = 0x00000220;
+SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
+SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00100100;
+SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0123123d;
+SDRAM[0].EmcXm2DqsPadCtrl3 = 0x51451420;
+SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514;
+SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514;
+SDRAM[0].EmcXm2DqsPadCtrl6 = 0x51451400;
+SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
+SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc004;
+SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f008;
+SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070000;
+SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x0000003f;
+SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x015ddddd;
+SDRAM[0].EmcAcpdControl = 0x00000000;
+SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00001032;
+SDRAM[0].EmcSwizzleRank0Byte0 = 0x53067142;
+SDRAM[0].EmcSwizzleRank0Byte1 = 0x73025146;
+SDRAM[0].EmcSwizzleRank0Byte2 = 0x20136475;
+SDRAM[0].EmcSwizzleRank0Byte3 = 0x46273150;
+SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003210;
+SDRAM[0].EmcSwizzleRank1Byte0 = 0x73451026;
+SDRAM[0].EmcSwizzleRank1Byte1 = 0x73025146;
+SDRAM[0].EmcSwizzleRank1Byte2 = 0x20641735;
+SDRAM[0].EmcSwizzleRank1Byte3 = 0x42136075;
+SDRAM[0].EmcDsrVttgenDrv = 0x0000003f;
+SDRAM[0].EmcTxdsrvttgen = 0x00000000;
+SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
+SDRAM[0].McEmemAdrCfg = 0x00000001;
+SDRAM[0].McEmemAdrCfgDev0 = 0x00080304;
+SDRAM[0].McEmemAdrCfgDev1 = 0x00080304;
+SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
+SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
+SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
+SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
+SDRAM[0].McEmemCfg = 0x00001000;
+SDRAM[0].McEmemArbCfg = 0x0f000007;
+SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
+SDRAM[0].McEmemArbTimingRcd = 0x00000003;
+SDRAM[0].McEmemArbTimingRp = 0x00000004;
+SDRAM[0].McEmemArbTimingRc = 0x00000010;
+SDRAM[0].McEmemArbTimingRas = 0x0000000a;
+SDRAM[0].McEmemArbTimingFaw = 0x0000000d;
+SDRAM[0].McEmemArbTimingRrd = 0x00000002;
+SDRAM[0].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[0].McEmemArbTimingWap2Pre = 0x00000009;
+SDRAM[0].McEmemArbTimingR2R = 0x00000003;
+SDRAM[0].McEmemArbTimingW2W = 0x00000001;
+SDRAM[0].McEmemArbTimingR2W = 0x00000006;
+SDRAM[0].McEmemArbTimingW2R = 0x00000006;
+SDRAM[0].McEmemArbDaTurns = 0x06060103;
+SDRAM[0].McEmemArbDaCovers = 0x00120b10;
+SDRAM[0].McEmemArbMisc0 = 0x71c81811;
+SDRAM[0].McEmemArbMisc1 = 0x70000f03;
+SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[0].McEmemArbOverride = 0x10000000;
+SDRAM[0].McEmemArbOverride1 = 0x00000000;
+SDRAM[0].McEmemArbRsv = 0xff00ff00;
+SDRAM[0].McClkenOverride = 0x00000000;
+SDRAM[0].McStatControl = 0x00000000;
+SDRAM[0].McDisplaySnapRing = 0x00000003;
+SDRAM[0].McVideoProtectBom = 0xfff00000;
+SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[0].McVideoProtectSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
+SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
+SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[0].McSecCarveoutBom = 0xfff00000;
+SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[0].EmcCaTrainingEnable = 0x00000001;
+SDRAM[0].EmcCaTrainingTimingCntl1 = 0x09257359;
+SDRAM[0].EmcCaTrainingTimingCntl2 = 0x00000017;
+SDRAM[0].SwizzleRankByteEncode = 0x00000008;
+SDRAM[0].BootRomPatchControl = 0x00000000;
+SDRAM[0].BootRomPatchData = 0x00000000;
+SDRAM[0].McMtsCarveoutBom = 0x78000000;
+SDRAM[0].McMtsCarveoutAdrHi = 0x00000001;
+SDRAM[0].McMtsCarveoutSizeMb = 0x00000080;
+SDRAM[0].McMtsCarveoutRegCtrl = 0x00000001;
+#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000000d;
+#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000000fd;
+#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00c10038;
+#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00c10038;
+#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00c1003c;
+#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00c10090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00c10041;
+#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00c10090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00c10041;
+#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
+#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00c10080;
+#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080021;
+#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000c1;
+#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00c10026;
+#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00c1001a;
+#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00c10024;
+#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00c10029;
+#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000c1;
+#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
+#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
+#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00c10065;
+#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00c1002a;
+
+
+# CFG Version 01 Hynix H9CCNNNBLTALAR-NUD (using Micron part)
+# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command:
+# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_528MHz_emc_reg.txt 1.89394
+# -o A44_64_528_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6
+# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.89 ns (528.00 MHz)
+# bkv file: A44_528MHz_emc_reg.txt
+SDRAM[1].MemoryType = NvBootMemoryType_LpDdr2;
+SDRAM[1].PllMInputDivider = 0x00000001;
+SDRAM[1].PllMFeedbackDivider = 0x0000002c;
+SDRAM[1].PllMStableTime = 0x0000012c;
+SDRAM[1].PllMSetupControl = 0x00000000;
+SDRAM[1].PllMSelectDiv2 = 0x00000000;
+SDRAM[1].PllMPDLshiftPh45 = 0x00000001;
+SDRAM[1].PllMPDLshiftPh90 = 0x00000001;
+SDRAM[1].PllMPDLshiftPh135 = 0x00000001;
+SDRAM[1].PllMKCP = 0x00000000;
+SDRAM[1].PllMKVCO = 0x00000000;
+SDRAM[1].EmcBctSpare0 = 0x00000000;
+SDRAM[1].EmcBctSpare1 = 0x00000000;
+SDRAM[1].EmcBctSpare2 = 0x00000000;
+SDRAM[1].EmcBctSpare3 = 0x00000000;
+SDRAM[1].EmcBctSpare4 = 0x00000000;
+SDRAM[1].EmcBctSpare5 = 0x00000000;
+SDRAM[1].EmcBctSpare6 = 0x00000000;
+SDRAM[1].EmcBctSpare7 = 0x00000000;
+SDRAM[1].EmcBctSpare8 = 0x00000000;
+SDRAM[1].EmcBctSpare9 = 0x00000000;
+SDRAM[1].EmcBctSpare10 = 0x00000000;
+SDRAM[1].EmcBctSpare11 = 0x00000000;
+SDRAM[1].EmcClockSource = 0x80000000;
+SDRAM[1].EmcAutoCalInterval = 0x001fffff;
+SDRAM[1].EmcAutoCalConfig = 0xa1430000;
+SDRAM[1].EmcAutoCalConfig2 = 0x00000000;
+SDRAM[1].EmcAutoCalConfig3 = 0x00000000;
+SDRAM[1].EmcAutoCalWait = 0x00000190;
+SDRAM[1].EmcAdrCfg = 0x00000001;
+SDRAM[1].EmcPinProgramWait = 0x00000000;
+SDRAM[1].EmcPinExtraWait = 0x00000000;
+SDRAM[1].EmcTimingControlWait = 0x00000000;
+SDRAM[1].EmcRc = 0x0000001f;
+SDRAM[1].EmcRfc = 0x00000044;
+SDRAM[1].EmcRfcSlr = 0x00000000;
+SDRAM[1].EmcRas = 0x00000016;
+SDRAM[1].EmcRp = 0x00000009;
+SDRAM[1].EmcR2r = 0x00000000;
+SDRAM[1].EmcW2w = 0x00000000;
+SDRAM[1].EmcR2w = 0x0000000a;
+SDRAM[1].EmcW2r = 0x00000009;
+SDRAM[1].EmcR2p = 0x00000003;
+SDRAM[1].EmcW2p = 0x0000000d;
+SDRAM[1].EmcRdRcd = 0x00000009;
+SDRAM[1].EmcWrRcd = 0x00000009;
+SDRAM[1].EmcRrd = 0x00000005;
+SDRAM[1].EmcRext = 0x00000004;
+SDRAM[1].EmcWext = 0x00000000;
+SDRAM[1].EmcWdv = 0x00000002;
+SDRAM[1].EmcWdvMask = 0x00000002;
+SDRAM[1].EmcQUse = 0x00000008;
+SDRAM[1].EmcQuseWidth = 0x00000003;
+SDRAM[1].EmcIbdly = 0x00000000;
+SDRAM[1].EmcEInput = 0x00000003;
+SDRAM[1].EmcEInputDuration = 0x0000000a;
+SDRAM[1].EmcPutermExtra = 0x00050000;
+SDRAM[1].EmcPutermWidth = 0x00000004;
+SDRAM[1].EmcPutermAdj = 0x00000000;
+SDRAM[1].EmcCdbCntl1 = 0x00000000;
+SDRAM[1].EmcCdbCntl2 = 0x00000000;
+SDRAM[1].EmcCdbCntl3 = 0x00000000;
+SDRAM[1].EmcQRst = 0x00000002;
+SDRAM[1].EmcQSafe = 0x00000011;
+SDRAM[1].EmcRdv = 0x00000015;
+SDRAM[1].EmcRdvMask = 0x00000017;
+SDRAM[1].EmcQpop = 0x0000000d;
+SDRAM[1].EmcCtt = 0x00000000;
+SDRAM[1].EmcCttDuration = 0x00000004;
+SDRAM[1].EmcRefresh = 0x000007cd;
+SDRAM[1].EmcBurstRefreshNum = 0x00000000;
+SDRAM[1].EmcPreRefreshReqCnt = 0x000001f3;
+SDRAM[1].EmcPdEx2Wr = 0x00000003;
+SDRAM[1].EmcPdEx2Rd = 0x00000003;
+SDRAM[1].EmcPChg2Pden = 0x00000009;
+SDRAM[1].EmcAct2Pden = 0x00000000;
+SDRAM[1].EmcAr2Pden = 0x00000001;
+SDRAM[1].EmcRw2Pden = 0x00000011;
+SDRAM[1].EmcTxsr = 0x0000004a;
+SDRAM[1].EmcTxsrDll = 0x0000004a;
+SDRAM[1].EmcTcke = 0x00000004;
+SDRAM[1].EmcTckesr = 0x00000008;
+SDRAM[1].EmcTpd = 0x00000004;
+SDRAM[1].EmcTfaw = 0x00000019;
+SDRAM[1].EmcTrpab = 0x0000000c;
+SDRAM[1].EmcTClkStable = 0x00000003;
+SDRAM[1].EmcTClkStop = 0x00000003;
+SDRAM[1].EmcTRefBw = 0x00000895;
+SDRAM[1].EmcFbioCfg5 = 0x1363a096;
+SDRAM[1].EmcFbioCfg6 = 0x00000000;
+SDRAM[1].EmcFbioSpare = 0x00000000;
+SDRAM[1].EmcCfgRsv = 0xff00ff00;
+SDRAM[1].EmcMrs = 0x00000000;
+SDRAM[1].EmcEmrs = 0x00000000;
+SDRAM[1].EmcEmrs2 = 0x00000000;
+SDRAM[1].EmcEmrs3 = 0x00000000;
+SDRAM[1].EmcMrw1 = 0x000100c3;
+SDRAM[1].EmcMrw2 = 0x00020006;
+SDRAM[1].EmcMrw3 = 0x00030001;
+SDRAM[1].EmcMrw4 = 0x800b0000;
+SDRAM[1].EmcMrwExtra = 0x000100c3;
+SDRAM[1].EmcWarmBootMrwExtra = 0x00020006;
+SDRAM[1].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[1].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[1].EmcMrwResetCommand = 0x003f00fc;
+SDRAM[1].EmcMrwResetNInitWait = 0x0000000a;
+SDRAM[1].EmcMrsWaitCnt = 0x02100013;
+SDRAM[1].EmcMrsWaitCnt2 = 0x02100013;
+SDRAM[1].EmcCfg = 0xf3300000;
+SDRAM[1].EmcCfg2 = 0x0000089f;
+SDRAM[1].EmcCfgPipe = 0x000042a0;
+SDRAM[1].EmcDbg = 0x01000c00;
+SDRAM[1].EmcCmdQ = 0x10004408;
+SDRAM[1].EmcMc2EmcQ = 0x06000404;
+SDRAM[1].EmcDynSelfRefControl = 0x800010b3;
+SDRAM[1].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[1].EmcCfgDigDll = 0xe01200b9;
+SDRAM[1].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[1].EmcDevSelect = 0x00000000;
+SDRAM[1].EmcSelDpdCtrl = 0x0004001c;
+SDRAM[1].EmcDllXformDqs0 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs1 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs2 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs3 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs4 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs5 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs6 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs7 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs8 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs9 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs10 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs11 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs12 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs13 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs14 = 0x007f400a;
+SDRAM[1].EmcDllXformDqs15 = 0x007f400a;
+SDRAM[1].EmcDllXformQUse0 = 0x00000000;
+SDRAM[1].EmcDllXformQUse1 = 0x00000000;
+SDRAM[1].EmcDllXformQUse2 = 0x00000000;
+SDRAM[1].EmcDllXformQUse3 = 0x00000000;
+SDRAM[1].EmcDllXformQUse4 = 0x00000000;
+SDRAM[1].EmcDllXformQUse5 = 0x00000000;
+SDRAM[1].EmcDllXformQUse6 = 0x00000000;
+SDRAM[1].EmcDllXformQUse7 = 0x00000000;
+SDRAM[1].EmcDllXformAddr0 = 0x00024000;
+SDRAM[1].EmcDllXformAddr1 = 0x00024000;
+SDRAM[1].EmcDllXformAddr2 = 0x00000006;
+SDRAM[1].EmcDllXformAddr3 = 0x00024000;
+SDRAM[1].EmcDllXformAddr4 = 0x00024000;
+SDRAM[1].EmcDllXformAddr5 = 0x00000006;
+SDRAM[1].EmcDllXformQUse8 = 0x00000000;
+SDRAM[1].EmcDllXformQUse9 = 0x00000000;
+SDRAM[1].EmcDllXformQUse10 = 0x00000000;
+SDRAM[1].EmcDllXformQUse11 = 0x00000000;
+SDRAM[1].EmcDllXformQUse12 = 0x00000000;
+SDRAM[1].EmcDllXformQUse13 = 0x00000000;
+SDRAM[1].EmcDllXformQUse14 = 0x00000000;
+SDRAM[1].EmcDllXformQUse15 = 0x00000000;
+SDRAM[1].EmcDliTrimTxDqs0 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs1 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs2 = 0x00000008;
+SDRAM[1].EmcDliTrimTxDqs3 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs4 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs5 = 0x00000008;
+SDRAM[1].EmcDliTrimTxDqs6 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs7 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs8 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs9 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs10 = 0x00000008;
+SDRAM[1].EmcDliTrimTxDqs11 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs12 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs13 = 0x00000008;
+SDRAM[1].EmcDliTrimTxDqs14 = 0x0000000b;
+SDRAM[1].EmcDliTrimTxDqs15 = 0x0000000b;
+SDRAM[1].EmcDllXformDq0 = 0x0000000c;
+SDRAM[1].EmcDllXformDq1 = 0x0000000c;
+SDRAM[1].EmcDllXformDq2 = 0x0000000c;
+SDRAM[1].EmcDllXformDq3 = 0x0000000c;
+SDRAM[1].EmcDllXformDq4 = 0x0000000c;
+SDRAM[1].EmcDllXformDq5 = 0x0000000c;
+SDRAM[1].EmcDllXformDq6 = 0x0000000c;
+SDRAM[1].EmcDllXformDq7 = 0x0000000c;
+SDRAM[1].WarmBootWait = 0x00000001;
+SDRAM[1].EmcCttTermCtrl = 0x00000802;
+SDRAM[1].EmcOdtWrite = 0x00000000;
+SDRAM[1].EmcOdtRead = 0x00000000;
+SDRAM[1].EmcZcalInterval = 0x00064000;
+SDRAM[1].EmcZcalWaitCnt = 0x00000034;
+SDRAM[1].EmcZcalMrwCmd = 0x000a0056;
+SDRAM[1].EmcMrsResetDll = 0x00000000;
+SDRAM[1].EmcZcalInitDev0 = 0x840a00ff;
+SDRAM[1].EmcZcalInitDev1 = 0x440a00ff;
+SDRAM[1].EmcZcalInitWait = 0x00000001;
+SDRAM[1].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[1].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[1].EmcZqCalDdr3WarmBoot = 0x00000000;
+SDRAM[1].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[1].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[1].EmcMrsResetDllWait = 0x00000000;
+SDRAM[1].EmcMrsExtra = 0x00000000;
+SDRAM[1].EmcWarmBootMrsExtra = 0x00000000;
+SDRAM[1].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[1].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[1].EmcDdr2Wait = 0x00000000;
+SDRAM[1].EmcClkenOverride = 0x00000000;
+SDRAM[1].McDisExtraSnapLevels = 0x00000000;
+SDRAM[1].EmcExtraRefreshNum = 0x00000002;
+SDRAM[1].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[1].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[1].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[1].PmcVddpSel = 0x00000001;
+SDRAM[1].PmcVddpSelWait = 0x00000002;
+SDRAM[1].PmcDdrPwr = 0x00000003;
+SDRAM[1].PmcDdrCfg = 0x00001000;
+SDRAM[1].PmcIoDpd3Req = 0x4ffefef7;
+SDRAM[1].PmcIoDpd3ReqWait = 0x00000000;
+SDRAM[1].PmcRegShort = 0x0000330f;
+SDRAM[1].PmcNoIoPower = 0x00000000;
+SDRAM[1].PmcPorDpdCtrlWait = 0x00000001;
+SDRAM[1].EmcXm2CmdPadCtrl = 0x00000220;
+SDRAM[1].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[1].EmcXm2CmdPadCtrl3 = 0x050c0000;
+SDRAM[1].EmcXm2CmdPadCtrl4 = 0x00000000;
+SDRAM[1].EmcXm2CmdPadCtrl5 = 0x00100100;
+SDRAM[1].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[1].EmcXm2DqsPadCtrl2 = 0x0123123d;
+SDRAM[1].EmcXm2DqsPadCtrl3 = 0x51451420;
+SDRAM[1].EmcXm2DqsPadCtrl4 = 0x00514514;
+SDRAM[1].EmcXm2DqsPadCtrl5 = 0x00514514;
+SDRAM[1].EmcXm2DqsPadCtrl6 = 0x51451400;
+SDRAM[1].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[1].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[1].EmcXm2DqPadCtrl3 = 0x00000000;
+SDRAM[1].EmcXm2ClkPadCtrl = 0x77ffc004;
+SDRAM[1].EmcXm2ClkPadCtrl2 = 0x00000000;
+SDRAM[1].EmcXm2CompPadCtrl = 0x81f1f008;
+SDRAM[1].EmcXm2VttGenPadCtrl = 0x07070000;
+SDRAM[1].EmcXm2VttGenPadCtrl2 = 0x0000003f;
+SDRAM[1].EmcXm2VttGenPadCtrl3 = 0x015ddddd;
+SDRAM[1].EmcAcpdControl = 0x00000000;
+SDRAM[1].EmcSwizzleRank0ByteCfg = 0x00001032;
+SDRAM[1].EmcSwizzleRank0Byte0 = 0x53067142;
+SDRAM[1].EmcSwizzleRank0Byte1 = 0x73025146;
+SDRAM[1].EmcSwizzleRank0Byte2 = 0x20136475;
+SDRAM[1].EmcSwizzleRank0Byte3 = 0x46273150;
+SDRAM[1].EmcSwizzleRank1ByteCfg = 0x00003210;
+SDRAM[1].EmcSwizzleRank1Byte0 = 0x73451026;
+SDRAM[1].EmcSwizzleRank1Byte1 = 0x73025146;
+SDRAM[1].EmcSwizzleRank1Byte2 = 0x20641735;
+SDRAM[1].EmcSwizzleRank1Byte3 = 0x42136075;
+SDRAM[1].EmcDsrVttgenDrv = 0x0000003f;
+SDRAM[1].EmcTxdsrvttgen = 0x00000000;
+SDRAM[1].EmcBgbiasCtl0 = 0x00000000;
+SDRAM[1].McEmemAdrCfg = 0x00000001;
+SDRAM[1].McEmemAdrCfgDev0 = 0x00080304;
+SDRAM[1].McEmemAdrCfgDev1 = 0x00080304;
+SDRAM[1].McEmemAdrCfgBankMask0 = 0x00001248;
+SDRAM[1].McEmemAdrCfgBankMask1 = 0x00002490;
+SDRAM[1].McEmemAdrCfgBankMask2 = 0x00000920;
+SDRAM[1].McEmemAdrCfgBankSwizzle3 = 0x00000001;
+SDRAM[1].McEmemCfg = 0x00001000;
+SDRAM[1].McEmemArbCfg = 0x0f000007;
+SDRAM[1].McEmemArbOutstandingReq = 0x80000040;
+SDRAM[1].McEmemArbTimingRcd = 0x00000003;
+SDRAM[1].McEmemArbTimingRp = 0x00000004;
+SDRAM[1].McEmemArbTimingRc = 0x00000010;
+SDRAM[1].McEmemArbTimingRas = 0x0000000a;
+SDRAM[1].McEmemArbTimingFaw = 0x0000000d;
+SDRAM[1].McEmemArbTimingRrd = 0x00000002;
+SDRAM[1].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[1].McEmemArbTimingWap2Pre = 0x00000009;
+SDRAM[1].McEmemArbTimingR2R = 0x00000003;
+SDRAM[1].McEmemArbTimingW2W = 0x00000001;
+SDRAM[1].McEmemArbTimingR2W = 0x00000006;
+SDRAM[1].McEmemArbTimingW2R = 0x00000006;
+SDRAM[1].McEmemArbDaTurns = 0x06060103;
+SDRAM[1].McEmemArbDaCovers = 0x00120b10;
+SDRAM[1].McEmemArbMisc0 = 0x71c81811;
+SDRAM[1].McEmemArbMisc1 = 0x70000f03;
+SDRAM[1].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[1].McEmemArbOverride = 0x10000000;
+SDRAM[1].McEmemArbOverride1 = 0x00000000;
+SDRAM[1].McEmemArbRsv = 0xff00ff00;
+SDRAM[1].McClkenOverride = 0x00000000;
+SDRAM[1].McStatControl = 0x00000000;
+SDRAM[1].McDisplaySnapRing = 0x00000003;
+SDRAM[1].McVideoProtectBom = 0xfff00000;
+SDRAM[1].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[1].McVideoProtectSizeMb = 0x00000000;
+SDRAM[1].McVideoProtectVprOverride = 0xe4bac743;
+SDRAM[1].McVideoProtectVprOverride1 = 0x00000013;
+SDRAM[1].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[1].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[1].McSecCarveoutBom = 0xfff00000;
+SDRAM[1].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[1].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[1].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[1].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[1].EmcCaTrainingEnable = 0x00000001;
+SDRAM[1].EmcCaTrainingTimingCntl1 = 0x09257359;
+SDRAM[1].EmcCaTrainingTimingCntl2 = 0x00000017;
+SDRAM[1].SwizzleRankByteEncode = 0x00000008;
+SDRAM[1].BootRomPatchControl = 0x00000000;
+SDRAM[1].BootRomPatchData = 0x00000000;
+SDRAM[1].McMtsCarveoutBom = 0x78000000;
+SDRAM[1].McMtsCarveoutAdrHi = 0x00000001;
+SDRAM[1].McMtsCarveoutSizeMb = 0x00000080;
+SDRAM[1].McMtsCarveoutRegCtrl = 0x00000001;
+#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000000d;
+#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000000fd;
+#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00c10038;
+#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00c10038;
+#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00c1003c;
+#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00c10090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00c10041;
+#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00c10090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00c10041;
+#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
+#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00c10080;
+#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080021;
+#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000c1;
+#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00c10026;
+#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00c1001a;
+#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00c10024;
+#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00c10029;
+#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000c1;
+#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
+#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
+#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00c10065;
+#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00c1002a;
+
+# CFG Version 01 Micron EDFA232A2MA-JD-F (using Micron part)
+# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command:
+# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_528MHz_emc_reg.txt 1.89394
+# -o A44_64_528_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6
+# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.89 ns (528.00 MHz)
+# bkv file: A44_528MHz_emc_reg.txt
+SDRAM[2].MemoryType = NvBootMemoryType_LpDdr2;
+SDRAM[2].PllMInputDivider = 0x00000001;
+SDRAM[2].PllMFeedbackDivider = 0x0000002c;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].PllMSetupControl = 0x00000000;
+SDRAM[2].PllMSelectDiv2 = 0x00000000;
+SDRAM[2].PllMPDLshiftPh45 = 0x00000001;
+SDRAM[2].PllMPDLshiftPh90 = 0x00000001;
+SDRAM[2].PllMPDLshiftPh135 = 0x00000001;
+SDRAM[2].PllMKCP = 0x00000000;
+SDRAM[2].PllMKVCO = 0x00000000;
+SDRAM[2].EmcBctSpare0 = 0x00000000;
+SDRAM[2].EmcBctSpare1 = 0x00000000;
+SDRAM[2].EmcBctSpare2 = 0x00000000;
+SDRAM[2].EmcBctSpare3 = 0x00000000;
+SDRAM[2].EmcBctSpare4 = 0x00000000;
+SDRAM[2].EmcBctSpare5 = 0x00000000;
+SDRAM[2].EmcBctSpare6 = 0x00000000;
+SDRAM[2].EmcBctSpare7 = 0x00000000;
+SDRAM[2].EmcBctSpare8 = 0x00000000;
+SDRAM[2].EmcBctSpare9 = 0x00000000;
+SDRAM[2].EmcBctSpare10 = 0x00000000;
+SDRAM[2].EmcBctSpare11 = 0x00000000;
+SDRAM[2].EmcClockSource = 0x80000000;
+SDRAM[2].EmcAutoCalInterval = 0x001fffff;
+SDRAM[2].EmcAutoCalConfig = 0xa1430000;
+SDRAM[2].EmcAutoCalConfig2 = 0x00000000;
+SDRAM[2].EmcAutoCalConfig3 = 0x00000000;
+SDRAM[2].EmcAutoCalWait = 0x00000190;
+SDRAM[2].EmcAdrCfg = 0x00000001;
+SDRAM[2].EmcPinProgramWait = 0x00000000;
+SDRAM[2].EmcPinExtraWait = 0x00000000;
+SDRAM[2].EmcTimingControlWait = 0x00000000;
+SDRAM[2].EmcRc = 0x0000001f;
+SDRAM[2].EmcRfc = 0x00000044;
+SDRAM[2].EmcRfcSlr = 0x00000000;
+SDRAM[2].EmcRas = 0x00000016;
+SDRAM[2].EmcRp = 0x00000009;
+SDRAM[2].EmcR2r = 0x00000000;
+SDRAM[2].EmcW2w = 0x00000000;
+SDRAM[2].EmcR2w = 0x0000000a;
+SDRAM[2].EmcW2r = 0x00000009;
+SDRAM[2].EmcR2p = 0x00000003;
+SDRAM[2].EmcW2p = 0x0000000d;
+SDRAM[2].EmcRdRcd = 0x00000009;
+SDRAM[2].EmcWrRcd = 0x00000009;
+SDRAM[2].EmcRrd = 0x00000005;
+SDRAM[2].EmcRext = 0x00000004;
+SDRAM[2].EmcWext = 0x00000000;
+SDRAM[2].EmcWdv = 0x00000002;
+SDRAM[2].EmcWdvMask = 0x00000002;
+SDRAM[2].EmcQUse = 0x00000008;
+SDRAM[2].EmcQuseWidth = 0x00000003;
+SDRAM[2].EmcIbdly = 0x00000000;
+SDRAM[2].EmcEInput = 0x00000003;
+SDRAM[2].EmcEInputDuration = 0x0000000a;
+SDRAM[2].EmcPutermExtra = 0x00050000;
+SDRAM[2].EmcPutermWidth = 0x00000004;
+SDRAM[2].EmcPutermAdj = 0x00000000;
+SDRAM[2].EmcCdbCntl1 = 0x00000000;
+SDRAM[2].EmcCdbCntl2 = 0x00000000;
+SDRAM[2].EmcCdbCntl3 = 0x00000000;
+SDRAM[2].EmcQRst = 0x00000002;
+SDRAM[2].EmcQSafe = 0x00000011;
+SDRAM[2].EmcRdv = 0x00000015;
+SDRAM[2].EmcRdvMask = 0x00000017;
+SDRAM[2].EmcQpop = 0x0000000d;
+SDRAM[2].EmcCtt = 0x00000000;
+SDRAM[2].EmcCttDuration = 0x00000004;
+SDRAM[2].EmcRefresh = 0x000007cd;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPreRefreshReqCnt = 0x000001f3;
+SDRAM[2].EmcPdEx2Wr = 0x00000003;
+SDRAM[2].EmcPdEx2Rd = 0x00000003;
+SDRAM[2].EmcPChg2Pden = 0x00000009;
+SDRAM[2].EmcAct2Pden = 0x00000000;
+SDRAM[2].EmcAr2Pden = 0x00000001;
+SDRAM[2].EmcRw2Pden = 0x00000011;
+SDRAM[2].EmcTxsr = 0x0000004a;
+SDRAM[2].EmcTxsrDll = 0x0000004a;
+SDRAM[2].EmcTcke = 0x00000004;
+SDRAM[2].EmcTckesr = 0x00000008;
+SDRAM[2].EmcTpd = 0x00000004;
+SDRAM[2].EmcTfaw = 0x00000019;
+SDRAM[2].EmcTrpab = 0x0000000c;
+SDRAM[2].EmcTClkStable = 0x00000003;
+SDRAM[2].EmcTClkStop = 0x00000003;
+SDRAM[2].EmcTRefBw = 0x00000895;
+SDRAM[2].EmcFbioCfg5 = 0x1363a096;
+SDRAM[2].EmcFbioCfg6 = 0x00000000;
+SDRAM[2].EmcFbioSpare = 0x00000000;
+SDRAM[2].EmcCfgRsv = 0xff00ff00;
+SDRAM[2].EmcMrs = 0x00000000;
+SDRAM[2].EmcEmrs = 0x00000000;
+SDRAM[2].EmcEmrs2 = 0x00000000;
+SDRAM[2].EmcEmrs3 = 0x00000000;
+SDRAM[2].EmcMrw1 = 0x000100c3;
+SDRAM[2].EmcMrw2 = 0x00020006;
+SDRAM[2].EmcMrw3 = 0x00030001;
+SDRAM[2].EmcMrw4 = 0x800b0000;
+SDRAM[2].EmcMrwExtra = 0x000100c3;
+SDRAM[2].EmcWarmBootMrwExtra = 0x00020006;
+SDRAM[2].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[2].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x003f00fc;
+SDRAM[2].EmcMrwResetNInitWait = 0x0000000a;
+SDRAM[2].EmcMrsWaitCnt = 0x02100013;
+SDRAM[2].EmcMrsWaitCnt2 = 0x02100013;
+SDRAM[2].EmcCfg = 0xf3300000;
+SDRAM[2].EmcCfg2 = 0x0000089f;
+SDRAM[2].EmcCfgPipe = 0x000042a0;
+SDRAM[2].EmcDbg = 0x01000c00;
+SDRAM[2].EmcCmdQ = 0x10004408;
+SDRAM[2].EmcMc2EmcQ = 0x06000404;
+SDRAM[2].EmcDynSelfRefControl = 0x800010b3;
+SDRAM[2].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[2].EmcCfgDigDll = 0xe01200b9;
+SDRAM[2].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[2].EmcDevSelect = 0x00000000;
+SDRAM[2].EmcSelDpdCtrl = 0x0004001c;
+SDRAM[2].EmcDllXformDqs0 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs1 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs2 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs3 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs4 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs5 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs6 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs7 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs8 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs9 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs10 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs11 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs12 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs13 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs14 = 0x007f400a;
+SDRAM[2].EmcDllXformDqs15 = 0x007f400a;
+SDRAM[2].EmcDllXformQUse0 = 0x00000000;
+SDRAM[2].EmcDllXformQUse1 = 0x00000000;
+SDRAM[2].EmcDllXformQUse2 = 0x00000000;
+SDRAM[2].EmcDllXformQUse3 = 0x00000000;
+SDRAM[2].EmcDllXformQUse4 = 0x00000000;
+SDRAM[2].EmcDllXformQUse5 = 0x00000000;
+SDRAM[2].EmcDllXformQUse6 = 0x00000000;
+SDRAM[2].EmcDllXformQUse7 = 0x00000000;
+SDRAM[2].EmcDllXformAddr0 = 0x00024000;
+SDRAM[2].EmcDllXformAddr1 = 0x00024000;
+SDRAM[2].EmcDllXformAddr2 = 0x00000006;
+SDRAM[2].EmcDllXformAddr3 = 0x00024000;
+SDRAM[2].EmcDllXformAddr4 = 0x00024000;
+SDRAM[2].EmcDllXformAddr5 = 0x00000006;
+SDRAM[2].EmcDllXformQUse8 = 0x00000000;
+SDRAM[2].EmcDllXformQUse9 = 0x00000000;
+SDRAM[2].EmcDllXformQUse10 = 0x00000000;
+SDRAM[2].EmcDllXformQUse11 = 0x00000000;
+SDRAM[2].EmcDllXformQUse12 = 0x00000000;
+SDRAM[2].EmcDllXformQUse13 = 0x00000000;
+SDRAM[2].EmcDllXformQUse14 = 0x00000000;
+SDRAM[2].EmcDllXformQUse15 = 0x00000000;
+SDRAM[2].EmcDliTrimTxDqs0 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs1 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs2 = 0x00000008;
+SDRAM[2].EmcDliTrimTxDqs3 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs4 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs5 = 0x00000008;
+SDRAM[2].EmcDliTrimTxDqs6 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs7 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs8 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs9 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs10 = 0x00000008;
+SDRAM[2].EmcDliTrimTxDqs11 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs12 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs13 = 0x00000008;
+SDRAM[2].EmcDliTrimTxDqs14 = 0x0000000b;
+SDRAM[2].EmcDliTrimTxDqs15 = 0x0000000b;
+SDRAM[2].EmcDllXformDq0 = 0x0000000c;
+SDRAM[2].EmcDllXformDq1 = 0x0000000c;
+SDRAM[2].EmcDllXformDq2 = 0x0000000c;
+SDRAM[2].EmcDllXformDq3 = 0x0000000c;
+SDRAM[2].EmcDllXformDq4 = 0x0000000c;
+SDRAM[2].EmcDllXformDq5 = 0x0000000c;
+SDRAM[2].EmcDllXformDq6 = 0x0000000c;
+SDRAM[2].EmcDllXformDq7 = 0x0000000c;
+SDRAM[2].WarmBootWait = 0x00000001;
+SDRAM[2].EmcCttTermCtrl = 0x00000802;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcOdtRead = 0x00000000;
+SDRAM[2].EmcZcalInterval = 0x00064000;
+SDRAM[2].EmcZcalWaitCnt = 0x00000034;
+SDRAM[2].EmcZcalMrwCmd = 0x000a0056;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcZcalInitDev0 = 0x840a00ff;
+SDRAM[2].EmcZcalInitDev1 = 0x440a00ff;
+SDRAM[2].EmcZcalInitWait = 0x00000001;
+SDRAM[2].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[2].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[2].EmcZqCalDdr3WarmBoot = 0x00000000;
+SDRAM[2].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[2].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcMrsExtra = 0x00000000;
+SDRAM[2].EmcWarmBootMrsExtra = 0x00000000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[2].EmcDdr2Wait = 0x00000000;
+SDRAM[2].EmcClkenOverride = 0x00000000;
+SDRAM[2].McDisExtraSnapLevels = 0x00000000;
+SDRAM[2].EmcExtraRefreshNum = 0x00000002;
+SDRAM[2].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[2].PmcVddpSel = 0x00000001;
+SDRAM[2].PmcVddpSelWait = 0x00000002;
+SDRAM[2].PmcDdrPwr = 0x00000003;
+SDRAM[2].PmcDdrCfg = 0x00001000;
+SDRAM[2].PmcIoDpd3Req = 0x4ffefef7;
+SDRAM[2].PmcIoDpd3ReqWait = 0x00000000;
+SDRAM[2].PmcRegShort = 0x0000330f;
+SDRAM[2].PmcNoIoPower = 0x00000000;
+SDRAM[2].PmcPorDpdCtrlWait = 0x00000001;
+SDRAM[2].EmcXm2CmdPadCtrl = 0x00000220;
+SDRAM[2].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[2].EmcXm2CmdPadCtrl3 = 0x050c0000;
+SDRAM[2].EmcXm2CmdPadCtrl4 = 0x00000000;
+SDRAM[2].EmcXm2CmdPadCtrl5 = 0x00100100;
+SDRAM[2].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[2].EmcXm2DqsPadCtrl2 = 0x0123123d;
+SDRAM[2].EmcXm2DqsPadCtrl3 = 0x51451420;
+SDRAM[2].EmcXm2DqsPadCtrl4 = 0x00514514;
+SDRAM[2].EmcXm2DqsPadCtrl5 = 0x00514514;
+SDRAM[2].EmcXm2DqsPadCtrl6 = 0x51451400;
+SDRAM[2].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[2].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[2].EmcXm2DqPadCtrl3 = 0x00000000;
+SDRAM[2].EmcXm2ClkPadCtrl = 0x77ffc004;
+SDRAM[2].EmcXm2ClkPadCtrl2 = 0x00000000;
+SDRAM[2].EmcXm2CompPadCtrl = 0x81f1f008;
+SDRAM[2].EmcXm2VttGenPadCtrl = 0x07070000;
+SDRAM[2].EmcXm2VttGenPadCtrl2 = 0x0000003f;
+SDRAM[2].EmcXm2VttGenPadCtrl3 = 0x015ddddd;
+SDRAM[2].EmcAcpdControl = 0x00000000;
+SDRAM[2].EmcSwizzleRank0ByteCfg = 0x00001032;
+SDRAM[2].EmcSwizzleRank0Byte0 = 0x53067142;
+SDRAM[2].EmcSwizzleRank0Byte1 = 0x73025146;
+SDRAM[2].EmcSwizzleRank0Byte2 = 0x20136475;
+SDRAM[2].EmcSwizzleRank0Byte3 = 0x46273150;
+SDRAM[2].EmcSwizzleRank1ByteCfg = 0x00003210;
+SDRAM[2].EmcSwizzleRank1Byte0 = 0x73451026;
+SDRAM[2].EmcSwizzleRank1Byte1 = 0x73025146;
+SDRAM[2].EmcSwizzleRank1Byte2 = 0x20641735;
+SDRAM[2].EmcSwizzleRank1Byte3 = 0x42136075;
+SDRAM[2].EmcDsrVttgenDrv = 0x0000003f;
+SDRAM[2].EmcTxdsrvttgen = 0x00000000;
+SDRAM[2].EmcBgbiasCtl0 = 0x00000000;
+SDRAM[2].McEmemAdrCfg = 0x00000001;
+SDRAM[2].McEmemAdrCfgDev0 = 0x00080304;
+SDRAM[2].McEmemAdrCfgDev1 = 0x00080304;
+SDRAM[2].McEmemAdrCfgBankMask0 = 0x00001248;
+SDRAM[2].McEmemAdrCfgBankMask1 = 0x00002490;
+SDRAM[2].McEmemAdrCfgBankMask2 = 0x00000920;
+SDRAM[2].McEmemAdrCfgBankSwizzle3 = 0x00000001;
+SDRAM[2].McEmemCfg = 0x00001000;
+SDRAM[2].McEmemArbCfg = 0x0f000007;
+SDRAM[2].McEmemArbOutstandingReq = 0x80000040;
+SDRAM[2].McEmemArbTimingRcd = 0x00000003;
+SDRAM[2].McEmemArbTimingRp = 0x00000004;
+SDRAM[2].McEmemArbTimingRc = 0x00000010;
+SDRAM[2].McEmemArbTimingRas = 0x0000000a;
+SDRAM[2].McEmemArbTimingFaw = 0x0000000d;
+SDRAM[2].McEmemArbTimingRrd = 0x00000002;
+SDRAM[2].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[2].McEmemArbTimingWap2Pre = 0x00000009;
+SDRAM[2].McEmemArbTimingR2R = 0x00000003;
+SDRAM[2].McEmemArbTimingW2W = 0x00000001;
+SDRAM[2].McEmemArbTimingR2W = 0x00000006;
+SDRAM[2].McEmemArbTimingW2R = 0x00000006;
+SDRAM[2].McEmemArbDaTurns = 0x06060103;
+SDRAM[2].McEmemArbDaCovers = 0x00120b10;
+SDRAM[2].McEmemArbMisc0 = 0x71c81811;
+SDRAM[2].McEmemArbMisc1 = 0x70000f03;
+SDRAM[2].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[2].McEmemArbOverride = 0x10000000;
+SDRAM[2].McEmemArbOverride1 = 0x00000000;
+SDRAM[2].McEmemArbRsv = 0xff00ff00;
+SDRAM[2].McClkenOverride = 0x00000000;
+SDRAM[2].McStatControl = 0x00000000;
+SDRAM[2].McDisplaySnapRing = 0x00000003;
+SDRAM[2].McVideoProtectBom = 0xfff00000;
+SDRAM[2].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[2].McVideoProtectSizeMb = 0x00000000;
+SDRAM[2].McVideoProtectVprOverride = 0xe4bac743;
+SDRAM[2].McVideoProtectVprOverride1 = 0x00000013;
+SDRAM[2].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[2].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[2].McSecCarveoutBom = 0xfff00000;
+SDRAM[2].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[2].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[2].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[2].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[2].EmcCaTrainingEnable = 0x00000001;
+SDRAM[2].EmcCaTrainingTimingCntl1 = 0x09257359;
+SDRAM[2].EmcCaTrainingTimingCntl2 = 0x00000017;
+SDRAM[2].SwizzleRankByteEncode = 0x00000008;
+SDRAM[2].BootRomPatchControl = 0x00000000;
+SDRAM[2].BootRomPatchData = 0x00000000;
+SDRAM[2].McMtsCarveoutBom = 0x78000000;
+SDRAM[2].McMtsCarveoutAdrHi = 0x00000001;
+SDRAM[2].McMtsCarveoutSizeMb = 0x00000080;
+SDRAM[2].McMtsCarveoutRegCtrl = 0x00000001;
+#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000000d;
+#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000000fd;
+#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00c10038;
+#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00c10038;
+#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00c1003c;
+#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00c10090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00c10041;
+#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00c10090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00c10041;
+#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
+#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00c10080;
+#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080021;
+#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000c1;
+#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00c10026;
+#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00c1001a;
+#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00c10024;
+#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00c10029;
+#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000c1;
+#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
+#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
+#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00c10065;
+#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00c1002a;
+
+# CFG Version 01 Spare (using Micron part)
+# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command:
+# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_528MHz_emc_reg.txt 1.89394
+# -o A44_64_528_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6
+# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.89 ns (528.00 MHz)
+# bkv file: A44_528MHz_emc_reg.txt
+SDRAM[3].MemoryType = NvBootMemoryType_LpDdr2;
+SDRAM[3].PllMInputDivider = 0x00000001;
+SDRAM[3].PllMFeedbackDivider = 0x0000002c;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].PllMSetupControl = 0x00000000;
+SDRAM[3].PllMSelectDiv2 = 0x00000000;
+SDRAM[3].PllMPDLshiftPh45 = 0x00000001;
+SDRAM[3].PllMPDLshiftPh90 = 0x00000001;
+SDRAM[3].PllMPDLshiftPh135 = 0x00000001;
+SDRAM[3].PllMKCP = 0x00000000;
+SDRAM[3].PllMKVCO = 0x00000000;
+SDRAM[3].EmcBctSpare0 = 0x00000000;
+SDRAM[3].EmcBctSpare1 = 0x00000000;
+SDRAM[3].EmcBctSpare2 = 0x00000000;
+SDRAM[3].EmcBctSpare3 = 0x00000000;
+SDRAM[3].EmcBctSpare4 = 0x00000000;
+SDRAM[3].EmcBctSpare5 = 0x00000000;
+SDRAM[3].EmcBctSpare6 = 0x00000000;
+SDRAM[3].EmcBctSpare7 = 0x00000000;
+SDRAM[3].EmcBctSpare8 = 0x00000000;
+SDRAM[3].EmcBctSpare9 = 0x00000000;
+SDRAM[3].EmcBctSpare10 = 0x00000000;
+SDRAM[3].EmcBctSpare11 = 0x00000000;
+SDRAM[3].EmcClockSource = 0x80000000;
+SDRAM[3].EmcAutoCalInterval = 0x001fffff;
+SDRAM[3].EmcAutoCalConfig = 0xa1430000;
+SDRAM[3].EmcAutoCalConfig2 = 0x00000000;
+SDRAM[3].EmcAutoCalConfig3 = 0x00000000;
+SDRAM[3].EmcAutoCalWait = 0x00000190;
+SDRAM[3].EmcAdrCfg = 0x00000001;
+SDRAM[3].EmcPinProgramWait = 0x00000000;
+SDRAM[3].EmcPinExtraWait = 0x00000000;
+SDRAM[3].EmcTimingControlWait = 0x00000000;
+SDRAM[3].EmcRc = 0x0000001f;
+SDRAM[3].EmcRfc = 0x00000044;
+SDRAM[3].EmcRfcSlr = 0x00000000;
+SDRAM[3].EmcRas = 0x00000016;
+SDRAM[3].EmcRp = 0x00000009;
+SDRAM[3].EmcR2r = 0x00000000;
+SDRAM[3].EmcW2w = 0x00000000;
+SDRAM[3].EmcR2w = 0x0000000a;
+SDRAM[3].EmcW2r = 0x00000009;
+SDRAM[3].EmcR2p = 0x00000003;
+SDRAM[3].EmcW2p = 0x0000000d;
+SDRAM[3].EmcRdRcd = 0x00000009;
+SDRAM[3].EmcWrRcd = 0x00000009;
+SDRAM[3].EmcRrd = 0x00000005;
+SDRAM[3].EmcRext = 0x00000004;
+SDRAM[3].EmcWext = 0x00000000;
+SDRAM[3].EmcWdv = 0x00000002;
+SDRAM[3].EmcWdvMask = 0x00000002;
+SDRAM[3].EmcQUse = 0x00000008;
+SDRAM[3].EmcQuseWidth = 0x00000003;
+SDRAM[3].EmcIbdly = 0x00000000;
+SDRAM[3].EmcEInput = 0x00000003;
+SDRAM[3].EmcEInputDuration = 0x0000000a;
+SDRAM[3].EmcPutermExtra = 0x00050000;
+SDRAM[3].EmcPutermWidth = 0x00000004;
+SDRAM[3].EmcPutermAdj = 0x00000000;
+SDRAM[3].EmcCdbCntl1 = 0x00000000;
+SDRAM[3].EmcCdbCntl2 = 0x00000000;
+SDRAM[3].EmcCdbCntl3 = 0x00000000;
+SDRAM[3].EmcQRst = 0x00000002;
+SDRAM[3].EmcQSafe = 0x00000011;
+SDRAM[3].EmcRdv = 0x00000015;
+SDRAM[3].EmcRdvMask = 0x00000017;
+SDRAM[3].EmcQpop = 0x0000000d;
+SDRAM[3].EmcCtt = 0x00000000;
+SDRAM[3].EmcCttDuration = 0x00000004;
+SDRAM[3].EmcRefresh = 0x000007cd;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPreRefreshReqCnt = 0x000001f3;
+SDRAM[3].EmcPdEx2Wr = 0x00000003;
+SDRAM[3].EmcPdEx2Rd = 0x00000003;
+SDRAM[3].EmcPChg2Pden = 0x00000009;
+SDRAM[3].EmcAct2Pden = 0x00000000;
+SDRAM[3].EmcAr2Pden = 0x00000001;
+SDRAM[3].EmcRw2Pden = 0x00000011;
+SDRAM[3].EmcTxsr = 0x0000004a;
+SDRAM[3].EmcTxsrDll = 0x0000004a;
+SDRAM[3].EmcTcke = 0x00000004;
+SDRAM[3].EmcTckesr = 0x00000008;
+SDRAM[3].EmcTpd = 0x00000004;
+SDRAM[3].EmcTfaw = 0x00000019;
+SDRAM[3].EmcTrpab = 0x0000000c;
+SDRAM[3].EmcTClkStable = 0x00000003;
+SDRAM[3].EmcTClkStop = 0x00000003;
+SDRAM[3].EmcTRefBw = 0x00000895;
+SDRAM[3].EmcFbioCfg5 = 0x1363a096;
+SDRAM[3].EmcFbioCfg6 = 0x00000000;
+SDRAM[3].EmcFbioSpare = 0x00000000;
+SDRAM[3].EmcCfgRsv = 0xff00ff00;
+SDRAM[3].EmcMrs = 0x00000000;
+SDRAM[3].EmcEmrs = 0x00000000;
+SDRAM[3].EmcEmrs2 = 0x00000000;
+SDRAM[3].EmcEmrs3 = 0x00000000;
+SDRAM[3].EmcMrw1 = 0x000100c3;
+SDRAM[3].EmcMrw2 = 0x00020006;
+SDRAM[3].EmcMrw3 = 0x00030001;
+SDRAM[3].EmcMrw4 = 0x800b0000;
+SDRAM[3].EmcMrwExtra = 0x000100c3;
+SDRAM[3].EmcWarmBootMrwExtra = 0x00020006;
+SDRAM[3].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[3].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x003f00fc;
+SDRAM[3].EmcMrwResetNInitWait = 0x0000000a;
+SDRAM[3].EmcMrsWaitCnt = 0x02100013;
+SDRAM[3].EmcMrsWaitCnt2 = 0x02100013;
+SDRAM[3].EmcCfg = 0xf3300000;
+SDRAM[3].EmcCfg2 = 0x0000089f;
+SDRAM[3].EmcCfgPipe = 0x000042a0;
+SDRAM[3].EmcDbg = 0x01000c00;
+SDRAM[3].EmcCmdQ = 0x10004408;
+SDRAM[3].EmcMc2EmcQ = 0x06000404;
+SDRAM[3].EmcDynSelfRefControl = 0x800010b3;
+SDRAM[3].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[3].EmcCfgDigDll = 0xe01200b9;
+SDRAM[3].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[3].EmcDevSelect = 0x00000000;
+SDRAM[3].EmcSelDpdCtrl = 0x0004001c;
+SDRAM[3].EmcDllXformDqs0 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs1 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs2 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs3 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs4 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs5 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs6 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs7 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs8 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs9 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs10 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs11 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs12 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs13 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs14 = 0x007f400a;
+SDRAM[3].EmcDllXformDqs15 = 0x007f400a;
+SDRAM[3].EmcDllXformQUse0 = 0x00000000;
+SDRAM[3].EmcDllXformQUse1 = 0x00000000;
+SDRAM[3].EmcDllXformQUse2 = 0x00000000;
+SDRAM[3].EmcDllXformQUse3 = 0x00000000;
+SDRAM[3].EmcDllXformQUse4 = 0x00000000;
+SDRAM[3].EmcDllXformQUse5 = 0x00000000;
+SDRAM[3].EmcDllXformQUse6 = 0x00000000;
+SDRAM[3].EmcDllXformQUse7 = 0x00000000;
+SDRAM[3].EmcDllXformAddr0 = 0x00024000;
+SDRAM[3].EmcDllXformAddr1 = 0x00024000;
+SDRAM[3].EmcDllXformAddr2 = 0x00000006;
+SDRAM[3].EmcDllXformAddr3 = 0x00024000;
+SDRAM[3].EmcDllXformAddr4 = 0x00024000;
+SDRAM[3].EmcDllXformAddr5 = 0x00000006;
+SDRAM[3].EmcDllXformQUse8 = 0x00000000;
+SDRAM[3].EmcDllXformQUse9 = 0x00000000;
+SDRAM[3].EmcDllXformQUse10 = 0x00000000;
+SDRAM[3].EmcDllXformQUse11 = 0x00000000;
+SDRAM[3].EmcDllXformQUse12 = 0x00000000;
+SDRAM[3].EmcDllXformQUse13 = 0x00000000;
+SDRAM[3].EmcDllXformQUse14 = 0x00000000;
+SDRAM[3].EmcDllXformQUse15 = 0x00000000;
+SDRAM[3].EmcDliTrimTxDqs0 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs1 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs2 = 0x00000008;
+SDRAM[3].EmcDliTrimTxDqs3 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs4 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs5 = 0x00000008;
+SDRAM[3].EmcDliTrimTxDqs6 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs7 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs8 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs9 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs10 = 0x00000008;
+SDRAM[3].EmcDliTrimTxDqs11 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs12 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs13 = 0x00000008;
+SDRAM[3].EmcDliTrimTxDqs14 = 0x0000000b;
+SDRAM[3].EmcDliTrimTxDqs15 = 0x0000000b;
+SDRAM[3].EmcDllXformDq0 = 0x0000000c;
+SDRAM[3].EmcDllXformDq1 = 0x0000000c;
+SDRAM[3].EmcDllXformDq2 = 0x0000000c;
+SDRAM[3].EmcDllXformDq3 = 0x0000000c;
+SDRAM[3].EmcDllXformDq4 = 0x0000000c;
+SDRAM[3].EmcDllXformDq5 = 0x0000000c;
+SDRAM[3].EmcDllXformDq6 = 0x0000000c;
+SDRAM[3].EmcDllXformDq7 = 0x0000000c;
+SDRAM[3].WarmBootWait = 0x00000001;
+SDRAM[3].EmcCttTermCtrl = 0x00000802;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcOdtRead = 0x00000000;
+SDRAM[3].EmcZcalInterval = 0x00064000;
+SDRAM[3].EmcZcalWaitCnt = 0x00000034;
+SDRAM[3].EmcZcalMrwCmd = 0x000a0056;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcZcalInitDev0 = 0x840a00ff;
+SDRAM[3].EmcZcalInitDev1 = 0x440a00ff;
+SDRAM[3].EmcZcalInitWait = 0x00000001;
+SDRAM[3].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[3].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[3].EmcZqCalDdr3WarmBoot = 0x00000000;
+SDRAM[3].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[3].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcMrsExtra = 0x00000000;
+SDRAM[3].EmcWarmBootMrsExtra = 0x00000000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[3].EmcDdr2Wait = 0x00000000;
+SDRAM[3].EmcClkenOverride = 0x00000000;
+SDRAM[3].McDisExtraSnapLevels = 0x00000000;
+SDRAM[3].EmcExtraRefreshNum = 0x00000002;
+SDRAM[3].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[3].PmcVddpSel = 0x00000001;
+SDRAM[3].PmcVddpSelWait = 0x00000002;
+SDRAM[3].PmcDdrPwr = 0x00000003;
+SDRAM[3].PmcDdrCfg = 0x00001000;
+SDRAM[3].PmcIoDpd3Req = 0x4ffefef7;
+SDRAM[3].PmcIoDpd3ReqWait = 0x00000000;
+SDRAM[3].PmcRegShort = 0x0000330f;
+SDRAM[3].PmcNoIoPower = 0x00000000;
+SDRAM[3].PmcPorDpdCtrlWait = 0x00000001;
+SDRAM[3].EmcXm2CmdPadCtrl = 0x00000220;
+SDRAM[3].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[3].EmcXm2CmdPadCtrl3 = 0x050c0000;
+SDRAM[3].EmcXm2CmdPadCtrl4 = 0x00000000;
+SDRAM[3].EmcXm2CmdPadCtrl5 = 0x00100100;
+SDRAM[3].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[3].EmcXm2DqsPadCtrl2 = 0x0123123d;
+SDRAM[3].EmcXm2DqsPadCtrl3 = 0x51451420;
+SDRAM[3].EmcXm2DqsPadCtrl4 = 0x00514514;
+SDRAM[3].EmcXm2DqsPadCtrl5 = 0x00514514;
+SDRAM[3].EmcXm2DqsPadCtrl6 = 0x51451400;
+SDRAM[3].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[3].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[3].EmcXm2DqPadCtrl3 = 0x00000000;
+SDRAM[3].EmcXm2ClkPadCtrl = 0x77ffc004;
+SDRAM[3].EmcXm2ClkPadCtrl2 = 0x00000000;
+SDRAM[3].EmcXm2CompPadCtrl = 0x81f1f008;
+SDRAM[3].EmcXm2VttGenPadCtrl = 0x07070000;
+SDRAM[3].EmcXm2VttGenPadCtrl2 = 0x0000003f;
+SDRAM[3].EmcXm2VttGenPadCtrl3 = 0x015ddddd;
+SDRAM[3].EmcAcpdControl = 0x00000000;
+SDRAM[3].EmcSwizzleRank0ByteCfg = 0x00001032;
+SDRAM[3].EmcSwizzleRank0Byte0 = 0x53067142;
+SDRAM[3].EmcSwizzleRank0Byte1 = 0x73025146;
+SDRAM[3].EmcSwizzleRank0Byte2 = 0x20136475;
+SDRAM[3].EmcSwizzleRank0Byte3 = 0x46273150;
+SDRAM[3].EmcSwizzleRank1ByteCfg = 0x00003210;
+SDRAM[3].EmcSwizzleRank1Byte0 = 0x73451026;
+SDRAM[3].EmcSwizzleRank1Byte1 = 0x73025146;
+SDRAM[3].EmcSwizzleRank1Byte2 = 0x20641735;
+SDRAM[3].EmcSwizzleRank1Byte3 = 0x42136075;
+SDRAM[3].EmcDsrVttgenDrv = 0x0000003f;
+SDRAM[3].EmcTxdsrvttgen = 0x00000000;
+SDRAM[3].EmcBgbiasCtl0 = 0x00000000;
+SDRAM[3].McEmemAdrCfg = 0x00000001;
+SDRAM[3].McEmemAdrCfgDev0 = 0x00080304;
+SDRAM[3].McEmemAdrCfgDev1 = 0x00080304;
+SDRAM[3].McEmemAdrCfgBankMask0 = 0x00001248;
+SDRAM[3].McEmemAdrCfgBankMask1 = 0x00002490;
+SDRAM[3].McEmemAdrCfgBankMask2 = 0x00000920;
+SDRAM[3].McEmemAdrCfgBankSwizzle3 = 0x00000001;
+SDRAM[3].McEmemCfg = 0x00001000;
+SDRAM[3].McEmemArbCfg = 0x0f000007;
+SDRAM[3].McEmemArbOutstandingReq = 0x80000040;
+SDRAM[3].McEmemArbTimingRcd = 0x00000003;
+SDRAM[3].McEmemArbTimingRp = 0x00000004;
+SDRAM[3].McEmemArbTimingRc = 0x00000010;
+SDRAM[3].McEmemArbTimingRas = 0x0000000a;
+SDRAM[3].McEmemArbTimingFaw = 0x0000000d;
+SDRAM[3].McEmemArbTimingRrd = 0x00000002;
+SDRAM[3].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[3].McEmemArbTimingWap2Pre = 0x00000009;
+SDRAM[3].McEmemArbTimingR2R = 0x00000003;
+SDRAM[3].McEmemArbTimingW2W = 0x00000001;
+SDRAM[3].McEmemArbTimingR2W = 0x00000006;
+SDRAM[3].McEmemArbTimingW2R = 0x00000006;
+SDRAM[3].McEmemArbDaTurns = 0x06060103;
+SDRAM[3].McEmemArbDaCovers = 0x00120b10;
+SDRAM[3].McEmemArbMisc0 = 0x71c81811;
+SDRAM[3].McEmemArbMisc1 = 0x70000f03;
+SDRAM[3].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[3].McEmemArbOverride = 0x10000000;
+SDRAM[3].McEmemArbOverride1 = 0x00000000;
+SDRAM[3].McEmemArbRsv = 0xff00ff00;
+SDRAM[3].McClkenOverride = 0x00000000;
+SDRAM[3].McStatControl = 0x00000000;
+SDRAM[3].McDisplaySnapRing = 0x00000003;
+SDRAM[3].McVideoProtectBom = 0xfff00000;
+SDRAM[3].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[3].McVideoProtectSizeMb = 0x00000000;
+SDRAM[3].McVideoProtectVprOverride = 0xe4bac743;
+SDRAM[3].McVideoProtectVprOverride1 = 0x00000013;
+SDRAM[3].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[3].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[3].McSecCarveoutBom = 0xfff00000;
+SDRAM[3].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[3].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[3].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[3].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[3].EmcCaTrainingEnable = 0x00000001;
+SDRAM[3].EmcCaTrainingTimingCntl1 = 0x09257359;
+SDRAM[3].EmcCaTrainingTimingCntl2 = 0x00000017;
+SDRAM[3].SwizzleRankByteEncode = 0x00000008;
+SDRAM[3].BootRomPatchControl = 0x00000000;
+SDRAM[3].BootRomPatchData = 0x00000000;
+SDRAM[3].McMtsCarveoutBom = 0x78000000;
+SDRAM[3].McMtsCarveoutAdrHi = 0x00000001;
+SDRAM[3].McMtsCarveoutSizeMb = 0x00000080;
+SDRAM[3].McMtsCarveoutRegCtrl = 0x00000001;
+#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000000d;
+#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000000fd;
+#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00c10038;
+#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00c10038;
+#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00c1003c;
+#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00c10090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00c10041;
+#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00c10090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00c10041;
+#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
+#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00c10080;
+#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080021;
+#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000c1;
+#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00c10004;
+#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00c10026;
+#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00c1001a;
+#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00c10024;
+#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00c10029;
+#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000c1;
+#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
+#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
+#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00c100c1;
+#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00c10065;
+#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00c1002a;
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 8a5d087a7..0ce29a03f 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -99,4 +99,10 @@ config TRUSTZONE_CARVEOUT_SIZE_MB
help
Size of Trust Zone area in MiB to reserve in memory map.
+config BOOTROM_SDRAM_INIT
+ bool "SoC BootROM does SDRAM init with full BCT"
+ default n
+ help
+ Use during Ryu LPDDR3 bringup
+
endif
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index e7e545d00..2a1bd46d0 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -38,9 +38,13 @@ void romstage(void)
printk(BIOS_INFO, "T132: romstage here\n");
+#if CONFIG_BOOTROM_SDRAM_INIT
+ printk(BIOS_INFO, "T132 romstage: SDRAM init done by BootROM, RAMCODE = %d\n",
+ sdram_get_ram_code());
+#else
sdram_init(get_sdram_config());
printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
-
+#endif
cbmem_initialize();
ccplex_cpu_prepare();