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authorDeepa Dinamani <deepad@codeaurora.org>2014-12-10 15:23:47 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-15 21:57:04 +0200
commit18e434d1d35f96d5cf6a4b6c14f5528019c4f2f4 (patch)
tree2b5a9218e7921ee51500545db429dfd7800ce33c
parent08f249e7d07e7742e202d08305822af2b3ddec78 (diff)
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storm: Add watchdog reset api.
Use the apps processor watchdog reset to do a hard reset. The watchdog reset drives the RESETOUT on the chip. Modify register address definitions to be able to use pointers and pointer arithmetics. BRANCH=storm BUG=chrome-os-partner:34334 TEST=the chip resets and the control returns to start of SBL. Change-Id: Ib5772ab152b27058fde1be9de2d2ac26bfe00ca4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d50413cb614ef05ada93be1252fe5ef617a94d91 Original-Change-Id: I9b249d057b473429335587f7241ca462b4a6a8b7 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236141 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Reviewed-on: http://review.coreboot.org/9691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/google/storm/reset.c30
-rw-r--r--src/soc/qualcomm/ipq806x/include/soc/iomap.h4
2 files changed, 30 insertions, 4 deletions
diff --git a/src/mainboard/google/storm/reset.c b/src/mainboard/google/storm/reset.c
index 8020fbfbe..58c52f91d 100644
--- a/src/mainboard/google/storm/reset.c
+++ b/src/mainboard/google/storm/reset.c
@@ -1,6 +1,8 @@
/*
+ *
* This file is part of the coreboot project.
*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -17,10 +19,34 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <console/console.h>
+#include <soc/iomap.h>
#include <reset.h>
-void hard_reset(void)
+/* Watchdog bite time set to default reset value */
+#define RESET_WDT_BITE_TIME 0x31F3
+
+/* Watchdog bark time value is kept larger than the watchdog timeout
+ * of 0x31F3, effectively disabling the watchdog bark interrupt
+ */
+#define RESET_WDT_BARK_TIME (5 * RESET_WDT_BITE_TIME)
+
+static void wdog_reset(void)
{
- while (1)
+ printk(BIOS_DEBUG, "\nResetting with watchdog!\n");
+
+ writel(0, APCS_WDT0_EN);
+ writel(1, APCS_WDT0_RST);
+ writel(RESET_WDT_BARK_TIME, APCS_WDT0_BARK_TIME);
+ writel(RESET_WDT_BITE_TIME, APCS_WDT0_BITE_TIME);
+ writel(1, APCS_WDT0_EN);
+ writel(1, APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE);
+
+ for (;;)
;
}
+
+void hard_reset(void)
+{
+ wdog_reset();
+}
diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h
index 333e2615e..129b17700 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h
+++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h
@@ -49,9 +49,9 @@
#define clrsetbits_le32_i(addr, clear, set) \
clrsetbits_le32(((void *)(addr)), (clear), (set))
-#define MSM_CLK_CTL_BASE 0x00900000
+#define MSM_CLK_CTL_BASE ((unsigned char *)0x00900000)
-#define MSM_TMR_BASE 0x0200A000
+#define MSM_TMR_BASE ((unsigned char *)0x0200A000)
#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)