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authorjinkun.hong <jinkun.hong@rock-chips.com>2015-01-21 15:47:25 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-15 22:10:18 +0200
commit129b5fa973ca4d2c5e2a62bede3470da3bf8de3b (patch)
tree3b86ab26a4a17c7459f263c26350dfc807fe3d68
parentd4a227ba05aadf049cec0b4e4edc8345f476c2f4 (diff)
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rk3288: Fix failing LPDDR3 reboot test
tMRD request 10nCK in LPDDR3, we set the DDR_PCTL_TMRD BIT0~BIT2 to generate this signal, but the max value we can set is 7, so the standard can not be met. So, now we send the Mode Register Set command manually, and hence we can add the delay manually. BUG=chrome-os-partner:34608 TEST=loop reboot BRANCH=veyron Change-Id: Id974ab935c2df6ea35dcdd240378ffc68de0204d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b60a4de6ff3ad3720c2c06ed7de03ed942360e6c Original-Change-Id: I0d29ea9cd82ef018e835ae53090a47d0299ef61d Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242176 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/soc/rockchip/rk3288/sdram.c23
1 files changed, 20 insertions, 3 deletions
diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c
index d330f99d6..cda36be05 100644
--- a/src/soc/rockchip/rk3288/sdram.c
+++ b/src/soc/rockchip/rk3288/sdram.c
@@ -998,12 +998,29 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params)
writel(POWER_UP_START, &ddr_pctl_regs->powctl);
while (!(readl(&ddr_pctl_regs->powstat) & POWER_UP_DONE))
;
- send_command(ddr_pctl_regs, 3, DESELECT_CMD, 0);
- udelay(1);
- send_command(ddr_pctl_regs, 3, PREA_CMD, 0);
memory_init(ddr_publ_regs, sdram_params->dramtype);
move_to_config_state(ddr_publ_regs, ddr_pctl_regs);
+
+ if (sdram_params->dramtype == LPDDR3) {
+ send_command(ddr_pctl_regs, 3, DESELECT_CMD, 0);
+ udelay(1);
+ send_command(ddr_pctl_regs, 3, PREA_CMD, 0);
+ udelay(1);
+ send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(63) |
+ LPDDR2_OP(0xFC));
+ udelay(1);
+ send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(1) |
+ LPDDR2_OP(sdram_params->phy_timing.mr[1]));
+ udelay(1);
+ send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(2) |
+ LPDDR2_OP(sdram_params->phy_timing.mr[2]));
+ udelay(1);
+ send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(3) |
+ LPDDR2_OP(sdram_params->phy_timing.mr[3]));
+ udelay(1);
+ }
+
set_bandwidth_ratio(channel, sdram_params->ch[channel].bw);
/*
* set cs