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| author | H. Peter Anvin <hpa@zytor.com> | 2018-12-22 17:50:26 -0800 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2018-12-22 17:52:27 -0800 |
| commit | 7f688841cef786248b9072eb4c18eca532511cbc (patch) | |
| tree | 4c8b92d603009ff84f81c46d3fdde77304b49877 /test | |
| parent | e7f4e0e229a4b979f5d122f6c7c1e25e1524f21a (diff) | |
| download | nasm-7f688841cef786248b9072eb4c18eca532511cbc.tar.gz nasm-7f688841cef786248b9072eb4c18eca532511cbc.tar.xz nasm-7f688841cef786248b9072eb4c18eca532511cbc.zip | |
insns.dat: accept explicit ax/eax/rax operand to CLZERO
AMD documents this instruction with an rax operand. The error behavior
implies this is an address-size-sensitive instruction. Add support for
specifying the explicit operand, but consistent with normal ndisasm
behavior, don't disassemble the implicit operand.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'test')
| -rw-r--r-- | test/clzero.asm | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/test/clzero.asm b/test/clzero.asm new file mode 100644 index 00000000..89597a9a --- /dev/null +++ b/test/clzero.asm @@ -0,0 +1,26 @@ + bits 16 + + clzero + clzero ax + clzero eax +%ifdef ERROR + clzero rax +%endif + + bits 32 + + clzero + clzero ax + clzero eax +%ifdef ERROR + clzero rax +%endif + + bits 64 + + clzero +%ifdef ERROR + clzero ax +%endif + clzero eax + clzero rax |