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authorH. Peter Anvin <hpa@zytor.com>2002-04-30 20:57:59 +0000
committerH. Peter Anvin <hpa@zytor.com>2002-04-30 20:57:59 +0000
commitef7468f4ec05f23e8d866493593d7c1f07df5e03 (patch)
treece3d68c654cf05d24ff2c0a6b3b4fcccca13719b
parent620515ab4e66b45f9440cf04a1fa61869275170f (diff)
downloadnasm-ef7468f4ec05f23e8d866493593d7c1f07df5e03.tar.gz
nasm-ef7468f4ec05f23e8d866493593d7c1f07df5e03.tar.xz
nasm-ef7468f4ec05f23e8d866493593d7c1f07df5e03.zip
NASM 0.98p7nasm-0.98p7
-rw-r--r--Licence6
-rw-r--r--MODIFIED18
-rw-r--r--Makefile.in12
-rw-r--r--assemble.c79
-rw-r--r--configure.in2
-rw-r--r--disasm.c84
-rw-r--r--doc/Makefile7
-rw-r--r--insns.dat340
-rw-r--r--insns.h5
-rw-r--r--nasm.129
-rw-r--r--nasm.c17
-rw-r--r--nasm.h2
-rw-r--r--ndisasm.118
-rw-r--r--ndisasm.c2
-rw-r--r--preproc.c12
15 files changed, 378 insertions, 255 deletions
diff --git a/Licence b/Licence
index 7f5f842d..467d3af1 100644
--- a/Licence
+++ b/Licence
@@ -95,9 +95,9 @@ inaccurate or a failure of the Software to operate with any other
programs, even if you have been advised of the possibility of such
damages.
-X. In addition to what this Licence provides, the Software may be
-distributed in such a way as to be compliant with the GNU General
-Public Licence, as published by the Free Software Foundation,
+X. In addition to what this Licence otherwise provides, the Software
+may be distributed in such a way as to be compliant with the GNU
+General Public Licence, as published by the Free Software Foundation,
Cambridge, MA, USA; version 2, or, at your option, any later version;
incorporated herein by reference. You must include a copy of this
Licence with such distribution. Furthermore, patches sent to the
diff --git a/MODIFIED b/MODIFIED
index 15e4d872..247aced7 100644
--- a/MODIFIED
+++ b/MODIFIED
@@ -3,6 +3,24 @@ Anvin <hpa@zytor.com>; it is not the original form released by the
NASM authors. However, as of 0.98p6 I have agreed to release the
official 0.98 version, so this is now an "official pre-release".
+For release 0.98p7:
+
+* Fixed opcodes with a third byte-sized immediate argument to not
+ complain if given "byte" on the immediate.
+* Allow %undef to remove single-line macros with arguments. This
+ matches the behaviour of #undef in the C preprocessor.
+* Allow -d, -u, -i and -p to be specified as -D, -U, -I and -P for
+ compatibility with most C compilers and preprocessors. This allows
+ Makefile options to be shared between cc and nasm, for example.
+* Minor cleanups.
+* Went through the list of Katmai instructions and hopefully fixed the
+ (rather few) mistakes in it.
+* (Hopefully) fixed a number of disassembler bugs related to ambiguous
+ instructions (disambiguated by -p) and SSE instructions with REP.
+* Fix for bug reported by Mark Junger: "call dword 0x12345678" should
+ work and may add an OSP (affected CALL, JMP, Jcc).
+* Fix for environments when "stderr" isn't a compile-time constant.
+
For release 0.98p6:
* Took officially over coordination of the 0.98 release; so drop
diff --git a/Makefile.in b/Makefile.in
index b991991f..a3963fd9 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -22,9 +22,14 @@ INSTALL_DATA = @INSTALL_DATA@
NROFF = @NROFF@
+.SUFFIXES: .c .o .1 .man
+
.c.o:
$(CC) -c $(CFLAGS) $<
+.1.man:
+ $(NROFF) -man $< > $@
+
NASM = nasm.o nasmlib.o float.o insnsa.o assemble.o labels.o \
parser.o outform.o outbin.o outaout.o outcoff.o outelf.o \
outobj.o outas86.o outrdf.o outrdf2.o outdbg.o zoutieee.o \
@@ -32,7 +37,7 @@ NASM = nasm.o nasmlib.o float.o insnsa.o assemble.o labels.o \
NDISASM = ndisasm.o disasm.o sync.o nasmlib.o insnsd.o
-all: nasm ndisasm nasm.man
+all: nasm ndisasm nasm.man ndisasm.man
nasm: $(NASM)
$(CC) -o nasm $(NASM)
@@ -82,9 +87,6 @@ insnsa.c insnsd.c insnsi.h insnsn.c: insns.dat insns.pl
macros.c: standard.mac macros.pl
perl $(srcdir)/macros.pl $(srcdir)/standard.mac
-nasm.man: nasm.1
- $(NROFF) -man nasm.1 > nasm.man
-
install: nasm ndisasm
$(INSTALL_PROGRAM) nasm $(bindir)/nasm
$(INSTALL_PROGRAM) ndisasm $(bindir)/ndisasm
@@ -100,7 +102,7 @@ distclean: clean
cd rdoff; $(MAKE) distclean
cleaner: clean
- rm -f insnsa.c insnsd.c insnsi.h insnsn.c macros.c nasm.man
+ rm -f insnsa.c insnsd.c insnsi.h insnsn.c macros.c *.man
spotless: distclean cleaner
diff --git a/assemble.c b/assemble.c
index ae1de206..426bae23 100644
--- a/assemble.c
+++ b/assemble.c
@@ -45,6 +45,11 @@
* generates no code in the assembler)
* \330 - a literal byte follows in the code stream, to be added
* to the condition code value of the instruction.
+ * \331 - instruction not valid with REP prefix. Hint for
+ * disassembler only; for SSE instructions.
+ * \332 - disassemble a rep (0xF3 byte) prefix as repe not rep.
+ * \333 - REP prefix (0xF3 byte); for SSE instructions. Not encoded
+ * as a literal byte in order to aid the disassembler.
* \340 - reserve <operand 0> bytes of uninitialised storage.
* Operand 0 had better be a segmentless constant.
*/
@@ -555,6 +560,11 @@ static long calcsize (long segment, long offset, int bits,
break;
case 0330:
codes++, length++; break;
+ case 0331:
+ case 0332:
+ break;
+ case 0333:
+ length++; break;
case 0340: case 0341: case 0342:
if (ins->oprs[0].segment != NO_SEG)
errfunc (ERR_NONFATAL, "attempt to reserve non-constant"
@@ -853,6 +863,17 @@ static void gencode (long segment, long offset, int bits,
offset += 1;
break;
+ case 0331:
+ case 0332:
+ break;
+
+ case 0333:
+ *bytes = 0xF3;
+ out (offset, segment, bytes,
+ OUT_RAWDATA+1, NO_SEG, NO_SEG);
+ offset += 1;
+ break;
+
case 0340: case 0341: case 0342:
if (ins->oprs[0].segment != NO_SEG)
errfunc (ERR_PANIC, "non-constant BSS size in pass two");
@@ -959,7 +980,7 @@ static int regval (operand *o)
static int matches (struct itemplate *itemp, insn *instruction)
{
- int i, size, oprs, ret;
+ int i, size[3], asize, oprs, ret;
ret = 100;
@@ -998,29 +1019,55 @@ static int matches (struct itemplate *itemp, insn *instruction)
/*
* Check operand sizes
*/
- if (itemp->flags & IF_SB) {
- size = BITS8;
+ if (itemp->flags & IF_ARMASK) {
+ size[0] = size[1] = size[2] = 0;
+
+ switch (itemp->flags & IF_ARMASK) {
+ case IF_AR0: i = 0; break;
+ case IF_AR1: i = 1; break;
+ case IF_AR2: i = 2; break;
+ default: break; /* Shouldn't happen */
+ }
+ if (itemp->flags & IF_SB) {
+ size[i] = BITS8;
+ } else if (itemp->flags & IF_SW) {
+ size[i] = BITS16;
+ } else if (itemp->flags & IF_SD) {
+ size[i] = BITS32;
+ }
+ } else {
+ asize = 0;
+ if (itemp->flags & IF_SB) {
+ asize = BITS8;
oprs = itemp->operands;
- } else if (itemp->flags & IF_SW) {
- size = BITS16;
+ } else if (itemp->flags & IF_SW) {
+ asize = BITS16;
oprs = itemp->operands;
- } else if (itemp->flags & IF_SD) {
- size = BITS32;
+ } else if (itemp->flags & IF_SD) {
+ asize = BITS32;
oprs = itemp->operands;
- } else if (itemp->flags & (IF_SM | IF_SM2)) {
- oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
- size = 0; /* placate gcc */
- for (i=0; i<oprs; i++)
- if ( (size = itemp->opd[i] & SIZE_MASK) != 0)
- break;
+ }
+ size[0] = size[1] = size[2] = asize;
+ }
+
+ if (itemp->flags & (IF_SM | IF_SM2)) {
+ oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
+ asize = 0;
+ for (i=0; i<oprs; i++) {
+ if ( (asize = itemp->opd[i] & SIZE_MASK) != 0) {
+ int j;
+ for (j=0; j<oprs; j++)
+ size[j] = asize;
+ break;
+ }
+ }
} else {
- size = 0;
- oprs = itemp->operands;
+ oprs = itemp->operands;
}
for (i=0; i<itemp->operands; i++)
if (!(itemp->opd[i] & SIZE_MASK) &&
- (instruction->oprs[i].type & SIZE_MASK & ~size))
+ (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
ret = 2;
return ret;
diff --git a/configure.in b/configure.in
index 80e9b38f..6555596f 100644
--- a/configure.in
+++ b/configure.in
@@ -63,7 +63,7 @@ fi
AC_SUBST(GCCFLAGS)
dnl Look for "nroff" or "groff"
-AC_CHECK_PROGS(NROFF, groff nroff, echo)
+AC_CHECK_PROGS(NROFF, nroff, echo)
AC_SUBST(NROFF)
dnl Checks for header files.
diff --git a/disasm.c b/disasm.c
index ba76097b..e7e634ef 100644
--- a/disasm.c
+++ b/disasm.c
@@ -252,14 +252,21 @@ static unsigned char *do_ea (unsigned char *data, int modrm, int asize,
}
/*
- * Determine whether the code string in r corresponds to the data
+ * Determine whether the instruction template in t corresponds to the data
* stream in data. Return the number of bytes matched if so.
*/
-static int matches (unsigned char *r, unsigned char *data, int asize,
- int osize, int segsize, insn *ins)
+static int matches (struct itemplate *t, unsigned char *data, int asize,
+ int osize, int segsize, int rep, insn *ins)
{
+ unsigned char * r = (unsigned char *)(t->code);
unsigned char * origdata = data;
int a_used = FALSE, o_used = FALSE;
+ int drep = 0;
+
+ if ( rep == 0xF2 )
+ drep = P_REPNE;
+ else if ( rep == 0xF3 )
+ drep = P_REP;
while (*r)
{
@@ -434,12 +441,27 @@ static int matches (unsigned char *r, unsigned char *data, int asize,
else
ins->condition = d - t;
}
+ if (c == 0331) {
+ if ( rep )
+ return FALSE;
+ }
+ if (c == 0332) {
+ if (drep == P_REP)
+ drep = P_REPE;
+ }
+ if (c == 0333) {
+ if ( rep != 0xF3 )
+ return FALSE;
+ drep = 0;
+ }
}
/*
- * Check for unused a/o prefixes.
+ * Check for unused rep or a/o prefixes.
*/
ins->nprefix = 0;
+ if (drep)
+ ins->prefixes[ins->nprefix++] = drep;
if (!a_used && asize != segsize)
ins->prefixes[ins->nprefix++] = (asize == 16 ? P_A16 : P_A32);
if (!o_used && osize != segsize)
@@ -457,7 +479,7 @@ long disasm (unsigned char *data, char *output, int segsize, long offset,
int rep, lock, asize, osize, i, slen, colon;
unsigned char *origdata;
int works;
- insn ins;
+ insn tmp_ins, ins;
unsigned long goodness, best;
/*
@@ -490,35 +512,35 @@ long disasm (unsigned char *data, char *output, int segsize, long offset,
break;
}
- ins.oprs[0].segment = ins.oprs[1].segment = ins.oprs[2].segment =
- ins.oprs[0].addr_size = ins.oprs[1].addr_size = ins.oprs[2].addr_size =
- (segsize == 16 ? 0 : SEG_32BIT);
- ins.condition = -1;
+ tmp_ins.oprs[0].segment = tmp_ins.oprs[1].segment =
+ tmp_ins.oprs[2].segment =
+ tmp_ins.oprs[0].addr_size = tmp_ins.oprs[1].addr_size =
+ tmp_ins.oprs[2].addr_size = (segsize == 16 ? 0 : SEG_32BIT);
+ tmp_ins.condition = -1;
best = ~0UL; /* Worst possible */
best_p = NULL;
for (p = itable[*data]; *p; p++) {
- if ( (length = matches((unsigned char *)((*p)->code), data,
- asize, osize, segsize, &ins)) ) {
+ if ( (length = matches(*p, data, asize, osize,
+ segsize, rep, &tmp_ins)) ) {
works = TRUE;
/*
* Final check to make sure the types of r/m match up.
*/
for (i = 0; i < (*p)->operands; i++) {
if (
-
/* If it's a mem-only EA but we have a register, die. */
- ((ins.oprs[i].segment & SEG_RMREG) &&
+ ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
!(MEMORY & ~(*p)->opd[i])) ||
/* If it's a reg-only EA but we have a memory ref, die. */
- (!(ins.oprs[i].segment & SEG_RMREG) &&
+ (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
!(REGNORM & ~(*p)->opd[i]) &&
!((*p)->opd[i] & REG_SMASK)) ||
/* Register type mismatch (eg FS vs REG_DESS): die. */
((((*p)->opd[i] & (REGISTER | FPUREG)) ||
- (ins.oprs[i].segment & SEG_RMREG)) &&
- !whichreg ((*p)->opd[i], ins.oprs[i].basereg))) {
+ (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
+ !whichreg ((*p)->opd[i], tmp_ins.oprs[i].basereg))) {
works = FALSE;
break;
}
@@ -528,41 +550,35 @@ long disasm (unsigned char *data, char *output, int segsize, long offset,
goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
if ( goodness < best ) {
/* This is the best one found so far */
- best = goodness;
- best_p = p;
+ best = goodness;
+ best_p = p;
best_length = length;
+ ins = tmp_ins;
}
}
}
}
- if (!best_p )
+ if (!best_p)
return 0; /* no instruction was matched */
/* Pick the best match */
- p = best_p;
+ p = best_p;
length = best_length;
slen = 0;
- if (rep) {
- slen += sprintf(output+slen, "rep%s ",
- (rep == 0xF2 ? "ne" :
- (*p)->opcode == I_CMPSB ||
- (*p)->opcode == I_CMPSW ||
- (*p)->opcode == I_CMPSD ||
- (*p)->opcode == I_SCASB ||
- (*p)->opcode == I_SCASW ||
- (*p)->opcode == I_SCASD ? "e" : ""));
- }
if (lock)
slen += sprintf(output+slen, "lock ");
for (i = 0; i < ins.nprefix; i++)
switch (ins.prefixes[i]) {
- case P_A16: slen += sprintf(output+slen, "a16 "); break;
- case P_A32: slen += sprintf(output+slen, "a32 "); break;
- case P_O16: slen += sprintf(output+slen, "o16 "); break;
- case P_O32: slen += sprintf(output+slen, "o32 "); break;
+ case P_REP: slen += sprintf(output+slen, "rep "); break;
+ case P_REPE: slen += sprintf(output+slen, "repe "); break;
+ case P_REPNE: slen += sprintf(output+slen, "repne "); break;
+ case P_A16: slen += sprintf(output+slen, "a16 "); break;
+ case P_A32: slen += sprintf(output+slen, "a32 "); break;
+ case P_O16: slen += sprintf(output+slen, "o16 "); break;
+ case P_O32: slen += sprintf(output+slen, "o32 "); break;
}
for (i = 0; i < elements(ico); i++)
diff --git a/doc/Makefile b/doc/Makefile
index 572ca570..c5104052 100644
--- a/doc/Makefile
+++ b/doc/Makefile
@@ -1,5 +1,6 @@
#
-# Makefile for NASM documentation
+# UNIX Makefile for NASM documentation
+#
SRCS = nasmdoc.src
OUT = nasm.info
@@ -10,12 +11,12 @@ all: $(OUT)
# Consider html, txt and src output a side effect
.src.texi:
- -mkdir html
+ mkdir -p html
perl ./rdsrc.pl < $<
mv -f *.html html
nasm.info: nasmdoc.texi
- -mkdir info
+ mkdir -p info
makeinfo $<
mv -f *.info *.info-* info
diff --git a/insns.dat b/insns.dat
index 350adec1..fb2cf454 100644
--- a/insns.dat
+++ b/insns.dat
@@ -1,4 +1,5 @@
; insns.dat table of instructions for the Netwide Assembler
+; $Id$
;
; The Netwide Assembler is copyright (C) 1996 Simon Tatham and
; Julian Hall. All rights reserved. The software is
@@ -129,6 +130,12 @@ BTS rm32,imm \321\300\2\x0F\xBA\205\25 386,SB
CALL imm \322\1\xE8\64 8086
CALL imm|near \322\1\xE8\64 8086
CALL imm|far \322\1\x9A\34\37 8086,ND
+CALL imm16 \320\1\xE8\64 8086
+CALL imm16|near \320\1\xE8\64 8086
+CALL imm16|far \320\1\x9A\34\37 8086,ND
+CALL imm32 \321\1\xE8\64 8086
+CALL imm32|near \321\1\xE8\64 8086
+CALL imm32|far \321\1\x9A\34\37 8086,ND
CALL imm:imm \322\1\x9A\35\30 8086
CALL imm16:imm \320\1\x9A\31\30 8086
CALL imm:imm16 \320\1\x9A\31\30 8086
@@ -175,9 +182,9 @@ CMP rm32,imm \321\300\1\x81\207\41 386,SM
CMP mem,imm8 \300\1\x80\207\21 8086,SM
CMP mem,imm16 \320\300\1\x81\207\31 8086,SM
CMP mem,imm32 \321\300\1\x81\207\41 386,SM
-CMPSB void \1\xA6 8086
-CMPSD void \321\1\xA7 386
-CMPSW void \320\1\xA7 8086
+CMPSB void \332\1\xA6 8086
+CMPSD void \332\321\1\xA7 386
+CMPSW void \332\320\1\xA7 8086
CMPXCHG mem,reg8 \300\2\x0F\xB0\101 PENT,SM
CMPXCHG reg8,reg8 \300\2\x0F\xB0\101 PENT
CMPXCHG mem,reg16 \320\300\2\x0F\xB1\101 PENT,SM
@@ -452,8 +459,14 @@ JCXZ imm \320\1\xE3\50 8086
JECXZ imm \321\1\xE3\50 386
JMP imm|short \1\xEB\50 8086
JMP imm \322\1\xE9\64 8086
-JMP imm|near \322\1\xE9\64 8086
+JMP imm|near \322\1\xE9\64 8086,ND
JMP imm|far \322\1\xEA\34\37 8086,ND
+JMP imm16 \320\1\xE9\64 8086
+JMP imm16|near \320\1\xE9\64 8086,ND
+JMP imm16|far \320\1\xEA\34\37 8086,ND
+JMP imm32 \321\1\xE9\64 8086
+JMP imm32|near \321\1\xE9\64 8086,ND
+JMP imm32|far \321\1\xEA\34\37 8086,ND
JMP imm:imm \322\1\xEA\35\30 8086
JMP imm16:imm \320\1\xEA\31\30 8086
JMP imm:imm16 \320\1\xEA\31\30 8086
@@ -913,9 +926,9 @@ SBB rm32,imm \321\300\1\x81\203\41 386,SM
SBB mem,imm8 \300\1\x80\203\21 8086,SM
SBB mem,imm16 \320\300\1\x81\203\31 8086,SM
SBB mem,imm32 \321\300\1\x81\203\41 386,SM
-SCASB void \1\xAE 8086
-SCASD void \321\1\xAF 386
-SCASW void \320\1\xAF 8086
+SCASB void \332\1\xAE 8086
+SCASD void \332\321\1\xAF 386
+SCASW void \332\320\1\xAF 8086
SGDT mem \300\2\x0F\x01\200 286
SHL rm8,unity \300\1\xD0\204 8086
SHL rm8,reg_cl \300\1\xD2\204 8086
@@ -926,10 +939,10 @@ SHL rm16,imm \320\300\1\xC1\204\25 186,SB
SHL rm32,unity \321\300\1\xD1\204 386
SHL rm32,reg_cl \321\300\1\xD3\204 386
SHL rm32,imm \321\300\1\xC1\204\25 386,SB
-SHLD mem,reg16,imm \300\320\2\x0F\xA4\101\26 386,SM2
-SHLD reg16,reg16,imm \300\320\2\x0F\xA4\101\26 386,SM2
-SHLD mem,reg32,imm \300\321\2\x0F\xA4\101\26 386,SM2
-SHLD reg32,reg32,imm \300\321\2\x0F\xA4\101\26 386,SM2
+SHLD mem,reg16,imm \300\320\2\x0F\xA4\101\26 386,SM2,SB,AR2
+SHLD reg16,reg16,imm \300\320\2\x0F\xA4\101\26 386,SM2,SB,AR2
+SHLD mem,reg32,imm \300\321\2\x0F\xA4\101\26 386,SM2,SB,AR2
+SHLD reg32,reg32,imm \300\321\2\x0F\xA4\101\26 386,SM2,SB,AR2
SHLD mem,reg16,reg_cl \300\320\2\x0F\xA5\101 386,SM
SHLD reg16,reg16,reg_cl \300\320\2\x0F\xA5\101 386
SHLD mem,reg32,reg_cl \300\321\2\x0F\xA5\101 386,SM
@@ -943,10 +956,10 @@ SHR rm16,imm \320\300\1\xC1\205\25 186,SB
SHR rm32,unity \321\300\1\xD1\205 386
SHR rm32,reg_cl \321\300\1\xD3\205 386
SHR rm32,imm \321\300\1\xC1\205\25 386,SB
-SHRD mem,reg16,imm \300\320\2\x0F\xAC\101\26 386,SM2
-SHRD reg16,reg16,imm \300\320\2\x0F\xAC\101\26 386,SM2
-SHRD mem,reg32,imm \300\321\2\x0F\xAC\101\26 386,SM2
-SHRD reg32,reg32,imm \300\321\2\x0F\xAC\101\26 386,SM2
+SHRD mem,reg16,imm \300\320\2\x0F\xAC\101\26 386,SM2,SB,AR2
+SHRD reg16,reg16,imm \300\320\2\x0F\xAC\101\26 386,SM2,SB,AR2
+SHRD mem,reg32,imm \300\321\2\x0F\xAC\101\26 386,SM2,SB,AR2
+SHRD reg32,reg32,imm \300\321\2\x0F\xAC\101\26 386,SM2,SB,AR2
SHRD mem,reg16,reg_cl \300\320\2\x0F\xAD\101 386,SM
SHRD reg16,reg16,reg_cl \300\320\2\x0F\xAD\101 386
SHRD mem,reg32,reg_cl \300\321\2\x0F\xAD\101 386,SM
@@ -958,7 +971,7 @@ SLDT reg16 \300\1\x0F\17\200 286
SMI void \1\xF1 386,UNDOC
SMINT void \2\x0F\x38 P6,CYRIX
; Older Cyrix chips had this; they had to move due to conflict with MMX
-SMINTOLD void \2\x0F\x7E 486,CYRIX
+SMINTOLD void \2\x0F\x7E 486,CYRIX,ND
SMSW mem \300\2\x0F\x01\204 286
SMSW mem16 \300\2\x0F\x01\204 286
SMSW reg16 \300\2\x0F\x01\204 286
@@ -1098,188 +1111,168 @@ CMOVcc reg16,reg16 \320\301\1\x0F\330\x40\110 P6
CMOVcc reg32,mem \321\301\1\x0F\330\x40\110 P6,SM
CMOVcc reg32,reg32 \321\301\1\x0F\330\x40\110 P6
Jcc imm|near \322\1\x0F\330\x80\64 386
+Jcc imm16|near \320\1\x0F\330\x80\64 386
+Jcc imm32|near \321\1\x0F\330\x80\64 386
Jcc imm \330\x70\50 8086
-Jcc imm|short \330\x70\50 8086
+Jcc imm|short \330\x70\50 8086,ND
SETcc mem \300\1\x0F\330\x90\200 386,SB
SETcc reg8 \300\1\x0F\330\x90\200 386
; Katmai Streaming SIMD instructions (SSE -- a.k.a. KNI, XMM, MMX2)
-ADDPS xmmreg,xmmreg \2\x0F\x58\110 KATMAI,SSE
-ADDPS xmmreg,mem \301\2\x0F\x58\110 KATMAI,SSE
-ADDSS xmmreg,xmmreg \3\xF3\x0F\x58\110 KATMAI,SSE
-ADDSS xmmreg,mem \301\3\xF3\x0F\x58\110 KATMAI,SSE
-
-MULPS xmmreg,xmmreg \2\x0F\x59\110 KATMAI,SSE
-MULPS xmmreg,mem \301\2\x0F\x59\110 KATMAI,SSE
-MULSS xmmreg,xmmreg \3\xF3\x0F\x59\110 KATMAI,SSE
-MULSS xmmreg,mem \301\3\xF3\x0F\x59\110 KATMAI,SSE
-
-DIVPS xmmreg,xmmreg \2\x0F\x5E\110 KATMAI,SSE
-DIVPS xmmreg,mem \301\2\x0F\x5E\110 KATMAI,SSE
-DIVSS xmmreg,xmmreg \3\xF3\x0F\x5E\110 KATMAI,SSE
-DIVSS xmmreg,mem \301\3\xF3\x0F\x5E\110 KATMAI,SSE
-
-SUBPS xmmreg,xmmreg \2\x0F\x5C\110 KATMAI,SSE
-SUBPS xmmreg,mem \301\2\x0F\x5C\110 KATMAI,SSE
-SUBSS xmmreg,xmmreg \3\xF3\x0F\x5C\110 KATMAI,SSE
-SUBSS xmmreg,mem \301\3\xF3\x0F\x5C\110 KATMAI,SSE
-
-RCPPS xmmreg,xmmreg \2\x0F\x53\110 KATMAI,SSE
-RCPPS xmmreg,mem \301\2\x0F\x53\110 KATMAI,SSE
-RCPSS xmmreg,xmmreg \3\xF3\x0F\x53\110 KATMAI,SSE
-RCPSS xmmreg,mem \301\3\xF3\x0F\x53\110 KATMAI,SSE
-
-RSQRTPS xmmreg,xmmreg \2\x0F\x52\110 KATMAI,SSE
-RSQRTPS xmmreg,mem \301\2\x0F\x52\110 KATMAI,SSE
-RSQRTSS xmmreg,xmmreg \3\xF3\x0F\x52\110 KATMAI,SSE
-RSQRTSS xmmreg,mem \301\3\xF3\x0F\x52\110 KATMAI,SSE
-
-SQRTPS xmmreg,xmmreg \2\x0F\x51\110 KATMAI,SSE
-SQRTPS xmmreg,mem \301\2\x0F\x51\110 KATMAI,SSE
-SQRTSS xmmreg,xmmreg \3\xF3\x0F\x51\110 KATMAI,SSE
-SQRTSS xmmreg,mem \301\3\xF3\x0F\x51\110 KATMAI,SSE
-
-ANDPS xmmreg,xmmreg \2\x0F\x54\110 KATMAI,SSE
-ANDPS xmmreg,mem \301\2\x0F\x54\110 KATMAI,SSE
-ANDNPS xmmreg,xmmreg \2\x0F\x55\110 KATMAI,SSE
+ADDPS xmmreg,mem \301\331\2\x0F\x58\110 KATMAI,SSE
+ADDPS xmmreg,xmmreg \331\2\x0F\x58\110 KATMAI,SSE
+ADDSS xmmreg,mem \301\333\2\x0F\x58\110 KATMAI,SSE
+ADDSS xmmreg,xmmreg \333\2\x0F\x58\110 KATMAI,SSE
ANDNPS xmmreg,mem \301\2\x0F\x55\110 KATMAI,SSE
-ORPS xmmreg,xmmreg \2\x0F\x56\110 KATMAI,SSE
-ORPS xmmreg,mem \301\2\x0F\x56\110 KATMAI,SSE
-XORPS xmmreg,xmmreg \2\x0F\x57\110 KATMAI,SSE
-XORPS xmmreg,mem \301\2\x0F\x57\110 KATMAI,SSE
-
-MAXPS xmmreg,xmmreg \2\x0F\x5F\110 KATMAI,SSE
-MAXPS xmmreg,mem \301\2\x0F\x5F\110 KATMAI,SSE
-MAXSS xmmreg,xmmreg \3\xF3\x0F\x5F\110 KATMAI,SSE
-MAXSS xmmreg,mem \301\3\xF3\x0F\x5F\110 KATMAI,SSE
-MINPS xmmreg,xmmreg \2\x0F\x5D\110 KATMAI,SSE
-MINPS xmmreg,mem \301\2\x0F\x5D\110 KATMAI,SSE
-MINSS xmmreg,xmmreg \3\xF3\x0F\x5D\110 KATMAI,SSE
-MINSS xmmreg,mem \301\3\xF3\x0F\x5D\110 KATMAI,SSE
-
-CMPEQPS xmmreg,xmmreg \2\x0F\xC2\110\1\x00 KATMAI,SSE
-CMPEQPS xmmreg,mem \301\2\x0F\xC2\110\1\x00 KATMAI,SSE
-CMPEQSS xmmreg,xmmreg \3\xF3\x0F\xC2\110\1\x00 KATMAI,SSE
-CMPEQSS xmmreg,mem \301\3\xF3\x0F\xC2\110\1\0x00 KATMAI,SSE
-
-CMPLTPS xmmreg,xmmreg \2\x0F\xC2\110\1\x01 KATMAI,SSE
-CMPLTPS xmmreg,mem \301\2\x0F\xC2\110\1\x01 KATMAI,SSE
-CMPLTSS xmmreg,xmmreg \3\xF3\x0F\xC2\110\1\x01 KATMAI,SSE
-CMPLTSS xmmreg,mem \301\3\xF3\x0F\xC2\110\1\x01 KATMAI,SSE
-
-CMPLEPS xmmreg,xmmreg \2\x0F\xC2\110\1\x02 KATMAI,SSE
-CMPLEPS xmmreg,mem \301\2\x0F\xC2\110\1\x02 KATMAI,SSE
-CMPLESS xmmreg,xmmreg \3\xF3\x0F\xC2\110\1\x02 KATMAI,SSE
-CMPLESS xmmreg,mem \301\3\xF3\x0F\xC2\110\1\x02 KATMAI,SSE
-
-CMPUNORDPS xmmreg,xmmreg \2\x0F\xC2\110\1\x03 KATMAI,SSE
-CMPUNORDPS xmmreg,mem \301\2\x0F\xC2\110\1\x03 KATMAI,SSE
-CMPUNORDSS xmmreg,xmmreg \3\xF3\x0F\xC2\110\1\x03 KATMAI,SSE
-CMPUNORDSS xmmreg,mem \301\3\xF3\x0F\xC2\110\1\x03 KATMAI,SSE
-
-CMPNEQPS xmmreg,xmmreg \2\x0F\xC2\110\1\x04 KATMAI,SSE
-CMPNEQPS xmmreg,mem \301\2\x0F\xC2\110\1\x04 KATMAI,SSE
-CMPNEQSS xmmreg,xmmreg \3\xF3\x0F\xC2\110\1\x04 KATMAI,SSE
-CMPNEQSS xmmreg,mem \301\3\xF3\x0F\xC2\110\1\x04 KATMAI,SSE
-
-CMPNLTPS xmmreg,xmmreg \2\x0F\xC2\110\1\x05 KATMAI,SSE
-CMPNLTPS xmmreg,mem \301\2\x0F\xC2\110\1\x05 KATMAI,SSE
-CMPNLTSS xmmreg,xmmreg \3\xF3\x0F\xC2\110\1\x05 KATMAI,SSE
-CMPNLTSS xmmreg,mem \301\3\xF3\x0F\xC2\110\1\x05 KATMAI,SSE
-
-CMPNLEPS xmmreg,xmmreg \2\x0F\xC2\110\1\x06 KATMAI,SSE
-CMPNLEPS xmmreg,mem \301\2\x0F\xC2\110\1\x06 KATMAI,SSE
-CMPNLESS xmmreg,xmmreg \3\xF3\x0F\xC2\110\1\x06 KATMAI,SSE
-CMPNLESS xmmreg,mem \301\3\xF3\x0F\xC2\110\1\x06 KATMAI,SSE
-
-CMPORDPS xmmreg,xmmreg \2\x0F\xC2\110\1\x07 KATMAI,SSE
-CMPORDPS xmmreg,mem \301\2\x0F\xC2\110\1\x07 KATMAI,SSE
-CMPORDSS xmmreg,xmmreg \3\xF3\x0F\xC2\110\1\x07 KATMAI,SSE
-CMPORDSS xmmreg,mem \301\3\xF3\x0F\xC2\110\1\x07 KATMAI,SSE
-
-UCOMISS xmmreg,xmmreg \2\x0F\x2E\110 KATMAI,SSE
-UCOMISS xmmreg,mem \301\2\x0F\x2E\110 KATMAI,SSE
-COMISS xmmreg,xmmreg \2\x0F\x2F\110 KATMAI,SSE
+ANDNPS xmmreg,xmmreg \2\x0F\x55\110 KATMAI,SSE
+ANDPS xmmreg,mem \301\2\x0F\x54\110 KATMAI,SSE
+ANDPS xmmreg,xmmreg \2\x0F\x54\110 KATMAI,SSE
+CMPEQPS xmmreg,mem \301\331\2\x0F\xC2\110\1\x00 KATMAI,SSE
+CMPEQPS xmmreg,xmmreg \331\2\x0F\xC2\110\1\x00 KATMAI,SSE
+CMPEQSS xmmreg,mem \301\333\2\x0F\xC2\110\1\0x00 KATMAI,SSE
+CMPEQSS xmmreg,xmmreg \333\2\x0F\xC2\110\1\x00 KATMAI,SSE
+CMPLEPS xmmreg,mem \301\331\2\x0F\xC2\110\1\x02 KATMAI,SSE
+CMPLEPS xmmreg,xmmreg \331\2\x0F\xC2\110\1\x02 KATMAI,SSE
+CMPLESS xmmreg,mem \301\333\2\x0F\xC2\110\1\x02 KATMAI,SSE
+CMPLESS xmmreg,xmmreg \333\2\x0F\xC2\110\1\x02 KATMAI,SSE
+CMPLTPS xmmreg,mem \301\331\2\x0F\xC2\110\1\x01 KATMAI,SSE
+CMPLTPS xmmreg,xmmreg \331\2\x0F\xC2\110\1\x01 KATMAI,SSE
+CMPLTSS xmmreg,mem \301\333\2\x0F\xC2\110\1\x01 KATMAI,SSE
+CMPLTSS xmmreg,xmmreg \333\2\x0F\xC2\110\1\x01 KATMAI,SSE
+CMPNEQPS xmmreg,mem \301\331\2\x0F\xC2\110\1\x04 KATMAI,SSE
+CMPNEQPS xmmreg,xmmreg \331\2\x0F\xC2\110\1\x04 KATMAI,SSE
+CMPNEQSS xmmreg,mem \301\333\2\x0F\xC2\110\1\x04 KATMAI,SSE
+CMPNEQSS xmmreg,xmmreg \333\2\x0F\xC2\110\1\x04 KATMAI,SSE
+CMPNLEPS xmmreg,mem \301\331\2\x0F\xC2\110\1\x06 KATMAI,SSE
+CMPNLEPS xmmreg,xmmreg \331\2\x0F\xC2\110\1\x06 KATMAI,SSE
+CMPNLESS xmmreg,mem \301\333\2\x0F\xC2\110\1\x06 KATMAI,SSE
+CMPNLESS xmmreg,xmmreg \333\2\x0F\xC2\110\1\x06 KATMAI,SSE
+CMPNLTPS xmmreg,mem \301\331\2\x0F\xC2\110\1\x05 KATMAI,SSE
+CMPNLTPS xmmreg,xmmreg \331\2\x0F\xC2\110\1\x05 KATMAI,SSE
+CMPNLTSS xmmreg,mem \301\333\2\x0F\xC2\110\1\x05 KATMAI,SSE
+CMPNLTSS xmmreg,xmmreg \333\2\x0F\xC2\110\1\x05 KATMAI,SSE
+CMPORDPS xmmreg,mem \301\331\2\x0F\xC2\110\1\x07 KATMAI,SSE
+CMPORDPS xmmreg,xmmreg \331\2\x0F\xC2\110\1\x07 KATMAI,SSE
+CMPORDSS xmmreg,mem \301\333\2\x0F\xC2\110\1\x07 KATMAI,SSE
+CMPORDSS xmmreg,xmmreg \333\2\x0F\xC2\110\1\x07 KATMAI,SSE
+CMPUNORDPS xmmreg,mem \301\331\2\x0F\xC2\110\1\x03 KATMAI,SSE
+CMPUNORDPS xmmreg,xmmreg \331\2\x0F\xC2\110\1\x03 KATMAI,SSE
+CMPUNORDSS xmmreg,mem \301\333\2\x0F\xC2\110\1\x03 KATMAI,SSE
+CMPUNORDSS xmmreg,xmmreg \333\2\x0F\xC2\110\1\x03 KATMAI,SSE
+; CMPPS/CMPSS must come after the specific ops; that way the disassembler will find the
+; specific ops first and only disassemble illegal ones as cmpps.
+CMPPS xmmreg,mem,imm \301\331\2\x0F\xC2\110\22 KATMAI,SSE,SB,AR2
+CMPPS xmmreg,xmmreg,imm \331\2\x0F\xC2\110\22 KATMAI,SSE,SB,AR2
+CMPSS xmmreg,mem,imm \301\333\2\x0F\xC2\110\22 KATMAI,SSE,SB,AR2
+CMPSS xmmreg,xmmreg,imm \333\2\x0F\xC2\110\22 KATMAI,SSE,SB,AR2
COMISS xmmreg,mem \301\2\x0F\x2F\110 KATMAI,SSE
-
-CVTPI2PS xmmreg,mmxreg \2\x0F\x2A\110 KATMAI,SSE,MMX
-CVTPI2PS xmmreg,mem \301\2\x0F\x2A\110 KATMAI,SSE,MMX
-CVTPS2PI mmxreg,xmmreg \2\x0F\x2D\110 KATMAI,SSE,MMX
-CVTPS2PI mmxreg,mem \301\2\x0F\x2D\110 KATMAI,SSE,MMX
-CVTTPS2PI mmxreg,xmmreg \2\x0F\x2C\110 KATMAI,SSE,MMX
-CVTTPS2PI mmxreg,mem \301\2\x0F\x2C\110 KATMAI,SSE,MMX
-
-CVTSI2SS xmmreg,reg32 \3\xF3\x0F\x2A\110 KATMAI,SSE
-CVTSI2SS xmmreg,mem \301\3\xF3\x0F\x2A\110 KATMAI,SSE
-CVTSS2SI reg32,xmmreg \3\xF3\x0F\x2D\110 KATMAI,SSE
-CVTSS2SI reg32,mem \301\3\xF3\x0F\x2D\110 KATMAI,SSE
-CVTTSS2SI reg32,xmmreg \3\xF3\x0F\x2C\110 KATMAI,SSE
-CVTTSS2SI reg32,mem \301\xF3\3\x0F\x2C\110 KATMAI,SSE
-
-; FXSAVE/FXRSTOR were introduced in Deschutes
-FXSAVE mem \300\2\x0F\xAE\200 P6,SSE,FPU
-FXRSTOR mem \300\2\x0F\xAE\201 P6,SSE,FPU
-LDMXCSR mem \300\2\x0F\xAE\202 KATMAI,SSE
-STMXCSR mem \300\2\x0F\xAE\203 KATMAI,SSE
-
-; These instructions aren't SSE-specific; they are generic memory operations
-; and work even if CR4.OSFXFR == 0
-SFENCE void \3\x0F\xAE\xF8 KATMAI
-
-PREFETCHNTA mem \300\2\x0F\x18\200 KATMAI,SM
-PREFETCHT0 mem \300\2\x0F\x18\201 KATMAI,SM
-PREFETCHT1 mem \300\2\x0F\x18\202 KATMAI,SM
-PREFETCHT2 mem \300\2\x0F\x18\203 KATMAI,SM
-
-MOVAPS xmmreg,xmmreg \2\x0F\x28\110 KATMAI,SSE
+COMISS xmmreg,xmmreg \2\x0F\x2F\110 KATMAI,SSE
+CVTPI2PS xmmreg,mem \301\331\2\x0F\x2A\110 KATMAI,SSE,MMX
+CVTPI2PS xmmreg,mmxreg \331\2\x0F\x2A\110 KATMAI,SSE,MMX
+CVTPS2PI mmxreg,mem \301\331\2\x0F\x2D\110 KATMAI,SSE,MMX
+CVTPS2PI mmxreg,xmmreg \331\2\x0F\x2D\110 KATMAI,SSE,MMX
+CVTSI2SS xmmreg,mem \301\333\2\x0F\x2A\110 KATMAI,SSE,SD,AR1
+CVTSI2SS xmmreg,reg32 \333\2\x0F\x2A\110 KATMAI,SSE
+CVTSS2SI reg32,mem \301\333\2\x0F\x2D\110 KATMAI,SSE
+CVTSS2SI reg32,xmmreg \333\2\x0F\x2D\110 KATMAI,SSE
+CVTTPS2PI mmxreg,mem \301\331\2\x0F\x2C\110 KATMAI,SSE,MMX
+CVTTPS2PI mmxreg,xmmreg \331\2\x0F\x2C\110 KATMAI,SSE,MMX
+CVTTSS2SI reg32,mem \301\333\2\x0F\x2C\110 KATMAI,SSE
+CVTTSS2SI reg32,xmmreg \333\2\x0F\x2C\110 KATMAI,SSE
+DIVPS xmmreg,mem \301\331\2\x0F\x5E\110 KATMAI,SSE
+DIVPS xmmreg,xmmreg \331\2\x0F\x5E\110 KATMAI,SSE
+DIVSS xmmreg,mem \301\333\2\x0F\x5E\110 KATMAI,SSE
+DIVSS xmmreg,xmmreg \333\2\x0F\x5E\110 KATMAI,SSE
+LDMXCSR mem \300\2\x0F\xAE\202 KATMAI,SSE,SD
+MAXPS xmmreg,mem \301\331\2\x0F\x5F\110 KATMAI,SSE
+MAXPS xmmreg,xmmreg \331\2\x0F\x5F\110 KATMAI,SSE
+MAXSS xmmreg,mem \301\333\2\x0F\x5F\110 KATMAI,SSE
+MAXSS xmmreg,xmmreg \333\2\x0F\x5F\110 KATMAI,SSE
+MINPS xmmreg,mem \301\331\2\x0F\x5D\110 KATMAI,SSE
+MINPS xmmreg,xmmreg \331\2\x0F\x5D\110 KATMAI,SSE
+MINSS xmmreg,mem \301\333\2\x0F\x5D\110 KATMAI,SSE
+MINSS xmmreg,xmmreg \333\2\x0F\x5D\110 KATMAI,SSE
MOVAPS xmmreg,mem \301\2\x0F\x28\110 KATMAI,SSE
-MOVAPS xmmreg,xmmreg \2\x0F\x29\101 KATMAI,SSE
MOVAPS mem,xmmreg \300\2\x0F\x29\101 KATMAI,SSE
-
-MOVHPS xmmreg,xmmreg \2\x0F\x16\110 KATMAI,SSE
+MOVAPS xmmreg,xmmreg \2\x0F\x28\110 KATMAI,SSE
+MOVAPS xmmreg,xmmreg \2\x0F\x29\101 KATMAI,SSE
MOVHPS xmmreg,mem \301\2\x0F\x16\110 KATMAI,SSE
-MOVHPS xmmreg,xmmreg \2\x0F\x17\101 KATMAI,SSE
MOVHPS mem,xmmreg \300\2\x0F\x17\101 KATMAI,SSE
-
-MOVLPS xmmreg,xmmreg \2\x0F\x12\110 KATMAI,SSE
+MOVHPS xmmreg,xmmreg \2\x0F\x16\101 KATMAI,SSE,ND
+MOVLHPS xmmreg,xmmreg \2\x0F\x16\110 KATMAI,SSE
MOVLPS xmmreg,mem \301\2\x0F\x12\110 KATMAI,SSE
-MOVLPS xmmreg,xmmreg \2\x0F\x13\101 KATMAI,SSE
MOVLPS mem,xmmreg \300\2\x0F\x13\101 KATMAI,SSE
-
-MOVUPS xmmreg,xmmreg \2\x0F\x10\110 KATMAI,SSE
-MOVUPS xmmreg,mem \301\2\x0F\x10\110 KATMAI,SSE
-MOVUPS xmmreg,xmmreg \2\x0F\x11\101 KATMAI,SSE
-MOVUPS mem,xmmreg \300\2\x0F\x11\101 KATMAI,SSE
-
-MOVSS xmmreg,xmmreg \3\xF3\x0F\x10\110 KATMAI,SSE
-MOVSS xmmreg,mem \301\3\xF3\x0F\x10\110 KATMAI,SSE
-MOVSS xmmreg,xmmreg \3\xF3\x0F\x11\101 KATMAI,SSE
-MOVSS mem,xmmreg \300\3\xF3\x0F\x11\101 KATMAI,SSE
-
+MOVLPS xmmreg,xmmreg \2\x0F\x12\101 KATMAI,SSE,ND
+MOVHLPS xmmreg,xmmreg \2\x0F\x12\110 KATMAI,SSE
MOVMSKPS reg32,xmmreg \2\x0F\x50\110 KATMAI,SSE
-
MOVNTPS mem,xmmreg \2\x0F\x2B\101 KATMAI,SSE
-
-SHUFPS xmmreg,xmmreg,imm8 \2\x0F\xC6\110\22 KATMAI,SSE
-SHUFPS xmmreg,mem,imm8 \301\2\x0F\xC6\110\22 KATMAI,SSE
-
-UNPCKHPS xmmreg,xmmreg \2\x0F\x15\110 KATMAI,SSE
+MOVSS xmmreg,mem \301\333\2\x0F\x10\110 KATMAI,SSE
+MOVSS mem,xmmreg \300\333\2\x0F\x11\101 KATMAI,SSE
+MOVSS xmmreg,xmmreg \333\2\x0F\x10\110 KATMAI,SSE
+MOVSS xmmreg,xmmreg \333\2\x0F\x11\101 KATMAI,SSE
+MOVUPS xmmreg,mem \301\331\2\x0F\x10\110 KATMAI,SSE
+MOVUPS mem,xmmreg \300\331\2\x0F\x11\101 KATMAI,SSE
+MOVUPS xmmreg,xmmreg \331\2\x0F\x10\110 KATMAI,SSE
+MOVUPS xmmreg,xmmreg \331\2\x0F\x11\101 KATMAI,SSE
+MULPS xmmreg,mem \301\2\x0F\x59\110 KATMAI,SSE
+MULPS xmmreg,xmmreg \2\x0F\x59\110 KATMAI,SSE
+MULSS xmmreg,mem \301\333\2\x0F\x59\110 KATMAI,SSE
+MULSS xmmreg,xmmreg \333\2\x0F\x59\110 KATMAI,SSE
+ORPS xmmreg,mem \301\2\x0F\x56\110 KATMAI,SSE
+ORPS xmmreg,xmmreg \2\x0F\x56\110 KATMAI,SSE
+RCPPS xmmreg,mem \301\331\2\x0F\x53\110 KATMAI,SSE
+RCPPS xmmreg,xmmreg \331\2\x0F\x53\110 KATMAI,SSE
+RCPSS xmmreg,mem \301\333\2\x0F\x53\110 KATMAI,SSE
+RCPSS xmmreg,xmmreg \333\2\x0F\x53\110 KATMAI,SSE
+RSQRTPS xmmreg,mem \301\331\2\x0F\x52\110 KATMAI,SSE
+RSQRTPS xmmreg,xmmreg \331\2\x0F\x52\110 KATMAI,SSE
+RSQRTSS xmmreg,mem \301\333\2\x0F\x52\110 KATMAI,SSE
+RSQRTSS xmmreg,xmmreg \333\2\x0F\x52\110 KATMAI,SSE
+SHUFPS xmmreg,mem,imm \301\2\x0F\xC6\110\22 KATMAI,SSE,SB,AR2
+SHUFPS xmmreg,xmmreg,imm \2\x0F\xC6\110\22 KATMAI,SSE,SB,AR2
+SQRTPS xmmreg,mem \301\331\2\x0F\x51\110 KATMAI,SSE
+SQRTPS xmmreg,xmmreg \331\2\x0F\x51\110 KATMAI,SSE
+SQRTSS xmmreg,mem \301\333\2\x0F\x51\110 KATMAI,SSE
+SQRTSS xmmreg,xmmreg \333\2\x0F\x51\110 KATMAI,SSE
+STMXCSR mem \300\2\x0F\xAE\203 KATMAI,SSE,SD
+SUBPS xmmreg,mem \301\331\2\x0F\x5C\110 KATMAI,SSE
+SUBPS xmmreg,xmmreg \331\2\x0F\x5C\110 KATMAI,SSE
+SUBSS xmmreg,mem \301\333\2\x0F\x5C\110 KATMAI,SSE
+SUBSS xmmreg,xmmreg \333\2\x0F\x5C\110 KATMAI,SSE
+UCOMISS xmmreg,mem \301\2\x0F\x2E\110 KATMAI,SSE
+UCOMISS xmmreg,xmmreg \2\x0F\x2E\110 KATMAI,SSE
UNPCKHPS xmmreg,mem \301\2\x0F\x15\110 KATMAI,SSE
-UNPCKLPS xmmreg,xmmreg \2\x0F\x14\110 KATMAI,SSE
+UNPCKHPS xmmreg,xmmreg \2\x0F\x15\110 KATMAI,SSE
UNPCKLPS xmmreg,mem \301\2\x0F\x14\110 KATMAI,SSE
+UNPCKLPS xmmreg,xmmreg \2\x0F\x14\110 KATMAI,SSE
+XORPS xmmreg,mem \301\2\x0F\x57\110 KATMAI,SSE
+XORPS xmmreg,xmmreg \2\x0F\x57\110 KATMAI,SSE
+
+; Introduced in Dechutes but necessary for SSE support
+FXRSTOR mem \300\2\x0F\xAE\201 P6,SSE,FPU
+FXSAVE mem \300\2\x0F\xAE\200 P6,SSE,FPU
+
+; These instructions aren't SSE-specific; they are generic memory operations
+; and work even if CR4.OSFXFR == 0
+PREFETCHNTA mem \300\2\x0F\x18\200 KATMAI
+PREFETCHT0 mem \300\2\x0F\x18\201 KATMAI
+PREFETCHT1 mem \300\2\x0F\x18\202 KATMAI
+PREFETCHT2 mem \300\2\x0F\x18\203 KATMAI
+SFENCE void \3\x0F\xAE\xF8 KATMAI
; New MMX instructions introduced in Katmai
+MASKMOVQ mmxreg,mmxreg \2\x0F\xF7\110 KATMAI,MMX
MOVNTQ mem,mmxreg \2\x0F\xE7\101 KATMAI,MMX,SM
PAVGB mmxreg,mmxreg \2\x0F\xE0\110 KATMAI,MMX
PAVGB mmxreg,mem \301\2\x0F\xE0\110 KATMAI,MMX,SM
PAVGW mmxreg,mmxreg \2\x0F\xE3\110 KATMAI,MMX
PAVGW mmxreg,mem \301\2\x0F\xE3\110 KATMAI,MMX,SM
-PEXTRW reg32,mmxreg,imm8 \2\x0F\xC5\110\22 KATMAI,MMX
+PEXTRW reg32,mmxreg,imm \2\x0F\xC5\110\22 KATMAI,MMX,SB,AR2
; PINSRW is documented as using a reg32, but it's really using only 16 bit
-; -- accept either
-PINSRW mmxreg,reg16,imm8 \2\x0F\xC4\110\22 KATMAI,MMX
-PINSRW mmxreg,reg32,imm8 \2\x0F\xC4\110\22 KATMAI,MMX
-PINSRW mmxreg,mem16,imm8 \301\2\x0F\xC4\110\22 KATMAI,MMX
+; -- accept either, but be truthful in disassembly
+PINSRW mmxreg,reg16,imm \2\x0F\xC4\110\22 KATMAI,MMX,SB,AR2
+PINSRW mmxreg,reg32,imm \2\x0F\xC4\110\22 KATMAI,MMX,SB,AR2,ND
+PINSRW mmxreg,mem16,imm \301\2\x0F\xC4\110\22 KATMAI,MMX,SB,AR2
PMAXSW mmxreg,mmxreg \2\x0F\xEE\110 KATMAI,MMX
PMAXSW mmxreg,mem \301\2\x0F\xEE\110 KATMAI,MMX,SM
PMAXUB mmxreg,mmxreg \2\x0F\xDE\110 KATMAI,MMX
@@ -1295,4 +1288,3 @@ PSADBW mmxreg,mmxreg \2\x0F\xF6\110 KATMAI,MMX
PSADBW mmxreg,mem \301\2\x0F\xF6\110 KATMAI,MMX,SM
PSHUFW mmxreg,mmxreg,imm8 \2\x0F\x70\110\22 KATMAI,MMX
PSHUFW mmxreg,mem,imm8 \301\2\x0F\x70\110\22 KATMAI,MMX,SM
-MASKMOVQ mmxreg,mmxreg \2\x0F\xF7\110 KATMAI,MMX
diff --git a/insns.h b/insns.h
index f12ea60c..af911eea 100644
--- a/insns.h
+++ b/insns.h
@@ -1,4 +1,5 @@
/* insns.h header file for insns.c
+ * $Id$
*
* The Netwide Assembler is copyright (C) 1996 Simon Tatham and
* Julian Hall. All rights reserved. The software is
@@ -49,6 +50,10 @@ struct itemplate {
#define IF_SB 0x00000004UL /* unsized operands can't be non-byte */
#define IF_SW 0x00000008UL /* unsized operands can't be non-word */
#define IF_SD 0x00000010UL /* unsized operands can't be nondword */
+#define IF_AR0 0x00000020UL /* SB, SW, SD applies to argument 0 */
+#define IF_AR1 0x00000040UL /* SB, SW, SD applies to argument 1 */
+#define IF_AR2 0x00000060UL /* SB, SW, SD applies to argument 2 */
+#define IF_ARMASK 0x00000060UL /* mask for unsized argument spec */
#define IF_PRIV 0x00000100UL /* it's a privileged instruction */
#define IF_SMM 0x00000200UL /* it's only valid in SMM */
#define IF_PROT 0x00000400UL /* it's protected mode only */
diff --git a/nasm.1 b/nasm.1
index a69723cb..1e682391 100644
--- a/nasm.1
+++ b/nasm.1
@@ -112,17 +112,40 @@ to, respectively, enable warnings about labels alone on lines or
disable warnings about incorrect numbers of parameters in macro
calls.
.TP
-.BI \-i " directory"
+.BI \-I " directory"
Adds a directory to the search path for include files. The directory
specification must include the trailing slash, as it will be
directly prepended to the name of the include file.
.TP
-.BI \-p " file"
+.BI \-i " directory"
+Same as the
+.B \-I
+option.
+.TP
+.BI \-P " file"
Specifies a file to be pre-included, before the main source file
starts to be processed.
.TP
-.BI \-d " macro[=value]"
+.BI \-p " file"
+Same as the
+.B \-P
+option.
+.TP
+.BI \-D " macro[=value]"
Pre-defines a single-line macro.
+.TP
+.BI \-d " macro[=value]"
+Same as the
+.B \-D
+option.
+.TP
+.BI \-U " macro"
+Undefines a single-line macro.
+.TP
+.BI \-u " macro"
+Same as the
+.B \-U
+option.
.PP
.RE
.SS SYNTAX
diff --git a/nasm.c b/nasm.c
index 0a03c7b9..74fcc08a 100644
--- a/nasm.c
+++ b/nasm.c
@@ -43,7 +43,7 @@ static int globallineno; /* for forward-reference tracking */
static int pass;
static struct ofmt *ofmt = NULL;
-static FILE *error_file = stderr; /* Where to write error messages */
+static FILE *error_file; /* Where to write error messages */
static FILE *ofile = NULL;
static int sb = 16; /* by default */
@@ -139,7 +139,8 @@ int main(int argc, char **argv)
preproc = &nasmpp;
operating_mode = op_normal;
-
+
+ error_file = stderr;
seg_init();
@@ -350,13 +351,13 @@ static int process_arg (char *p, char *q)
}
else
ofmt->current_dfmt = ofmt->debug_formats[0];
- } else if (p[1]=='p') { /* pre-include */
+ } else if (p[1]=='P' || p[1]=='p') { /* pre-include */
pp_pre_include (param);
} else if (p[1]=='D' || p[1]=='d') { /* pre-define */
pp_pre_define (param);
} else if (p[1]=='U' || p[1]=='u') { /* un-define */
pp_pre_undefine (param);
- } else if (p[1]=='i') { /* include search path */
+ } else if (p[1]=='I' || p[1]=='i') { /* include search path */
pp_include_path (param);
} else if (p[1]=='l') { /* listing file */
strcpy (listname, param);
@@ -392,10 +393,10 @@ static int process_arg (char *p, char *q)
" -E<file> redirect error messages to file\n\n"
" -g enable debug info\n"
" -F format select a debugging format\n\n"
- " -i<path> adds a pathname to the include file path\n"
- " -p<file> pre-includes a file\n"
- " -d<macro>[=<value>] pre-defines a macro\n"
- " -u<macro> undefines a macro\n"
+ " -I<path> adds a pathname to the include file path\n"
+ " -P<file> pre-includes a file\n"
+ " -D<macro>[=<value>] pre-defines a macro\n"
+ " -U<macro> undefines a macro\n"
" -w+foo enables warnings about foo; -w-foo disables them\n"
"where foo can be:\n");
for (i=1; i<=ERR_WARN_MAX; i++)
diff --git a/nasm.h b/nasm.h
index eca40fb8..6a37e781 100644
--- a/nasm.h
+++ b/nasm.h
@@ -13,7 +13,7 @@
#define NASM_MAJOR_VER 0
#define NASM_MINOR_VER 98
-#define NASM_VER "0.98 pre-release 6"
+#define NASM_VER "0.98 pre-release 7"
#ifndef NULL
#define NULL 0
diff --git a/ndisasm.1 b/ndisasm.1
index 78d313c3..fc95922d 100644
--- a/ndisasm.1
+++ b/ndisasm.1
@@ -1,3 +1,7 @@
+.\" $Id$
+.\"
+.\" This file is part of NASM and is released under the NASM License.
+.\"
.TH NDISASM 1 "The Netwide Assembler Project"
.SH NAME
ndisasm \- the Netwide Disassembler \- 80x86 binary file disassembler
@@ -89,6 +93,20 @@ Specifies either 16-bit or 32-bit mode. The default is 16-bit mode.
.TP
.B \-u
Specifies 32-bit mode, more compactly than using `-b 32'.
+.TP
+.BI \-p " vendor"
+Prefers instructions as defined by
+.I vendor
+in case of a conflict. Known
+.I vendor
+names include
+.BR intel ,
+.BR amd ,
+.BR cyrix ,
+and
+.BR idt .
+The default is
+.BR intel .
.PP
.RE
.SH RESTRICTIONS
diff --git a/ndisasm.c b/ndisasm.c
index 79e3ad59..354ea3c4 100644
--- a/ndisasm.c
+++ b/ndisasm.c
@@ -30,7 +30,7 @@ static const char *help =
" -r displays the version number\n"
" -e skips <bytes> bytes of header\n"
" -k avoids disassembling <bytes> bytes from position <start>\n"
-" -p selects the preferred vendor instruction set (intel, amd, cyrix)\n";
+" -p selects the preferred vendor instruction set (intel, amd, cyrix, idt)\n";
static void output_ins (unsigned long, unsigned char *, int, char *);
static void skip (unsigned long dist, FILE *fp);
diff --git a/preproc.c b/preproc.c
index 1a4fa0d1..5286dd0c 100644
--- a/preproc.c
+++ b/preproc.c
@@ -909,14 +909,14 @@ static FILE *inc_fopen(char *file)
/*
* Determine if we should warn on defining a single-line macro of
- * name `name', with `nparam' parameters. If nparam is 0, will
+ * name `name', with `nparam' parameters. If nparam is 0 or -1, will
* return TRUE if _any_ single-line macro of that name is defined.
* Otherwise, will return TRUE if a single-line macro with either
* `nparam' or no parameters is defined.
*
* If a macro with precisely the right number of parameters is
- * defined, the address of the definition structure will be
- * returned in `defn'; otherwise NULL will be returned. If `defn'
+ * defined, or nparam is -1, the address of the definition structure
+ * will be returned in `defn'; otherwise NULL will be returned. If `defn'
* is NULL, no action will be taken regarding its contents, and no
* error will occur.
*
@@ -943,9 +943,9 @@ static int smacro_defined (char *name, int nparam, SMacro **defn, int nocase)
while (m) {
if (!mstrcmp(m->name, p, m->casesense & nocase) &&
- (nparam == 0 || m->nparam == 0 || nparam == m->nparam)) {
+ (nparam <= 0 || m->nparam == 0 || nparam == m->nparam)) {
if (defn) {
- if (nparam == m->nparam)
+ if (nparam == m->nparam || nparam == -1)
*defn = m;
else
*defn = NULL;
@@ -1878,7 +1878,7 @@ static int do_directive (Token *tline)
/*
* We now have a macro name... go hunt for it.
*/
- if (smacro_defined (mname, 0, &smac, 1) && smac) {
+ while (smacro_defined (mname, -1, &smac, 1)) {
/* Defined, so we need to find its predecessor and nuke it */
SMacro **s;
for ( s = smhead ; *s && *s != smac ; s = &(*s)->next );