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authorLaurent Licour <laurent@licour.com>2011-01-30 20:50:59 +0100
committerErwan Velu <erwanaliasr1@gmail.com>2011-01-30 20:50:59 +0100
commit813daa0f83959de7c1ece9381966905a538919db (patch)
treefe6fa1ad931ebb41e4a9da37610574721b74209a
parent98d58026c4bf38e42adcfbd5f92da29fb582d41a (diff)
downloadhdt-chouffe.tar.gz
hdt-chouffe.tar.xz
hdt-chouffe.zip
DMI: Adjusting structures size / Adding cpu corechouffe
This patch adds some correction of the dmi structures but also add the support of the cpu cores/threads.
-rw-r--r--com32/gplinclude/dmi/dmi_base_board.h16
-rw-r--r--com32/gplinclude/dmi/dmi_battery.h12
-rw-r--r--com32/gplinclude/dmi/dmi_bios.h6
-rw-r--r--com32/gplinclude/dmi/dmi_cache.h4
-rw-r--r--com32/gplinclude/dmi/dmi_chassis.h8
-rw-r--r--com32/gplinclude/dmi/dmi_memory.h15
-rw-r--r--com32/gplinclude/dmi/dmi_processor.h15
-rw-r--r--com32/gplinclude/dmi/dmi_system.h12
-rw-r--r--com32/gpllib/dmi/dmi.c40
-rw-r--r--com32/gpllib/dmi/dmi_cache.c9
-rw-r--r--com32/gpllib/dmi/dmi_memory.c9
-rw-r--r--com32/gpllib/dmi/dmi_processor.c34
-rw-r--r--com32/hdt/hdt-cli-cpu.c6
-rw-r--r--com32/hdt/hdt-cli-dmi.c7
-rw-r--r--com32/hdt/hdt-menu-processor.c16
-rw-r--r--com32/hdt/hdt-menu-summary.c8
-rw-r--r--com32/lua/src/dmi.c12
-rw-r--r--com32/modules/dmitest.c6
18 files changed, 171 insertions, 64 deletions
diff --git a/com32/gplinclude/dmi/dmi_base_board.h b/com32/gplinclude/dmi/dmi_base_board.h
index 3d5fb557..0b45ccad 100644
--- a/com32/gplinclude/dmi/dmi_base_board.h
+++ b/com32/gplinclude/dmi/dmi_base_board.h
@@ -14,17 +14,19 @@
#define DMI_BASE_BOARD_H
#include "stdbool.h"
-#define BASE_BOARD_MANUFACTURER_SIZE 32
-#define BASE_BOARD_PRODUCT_NAME_SIZE 32
-#define BASE_BOARD_VERSION_SIZE 16
-#define BASE_BOARD_SERIAL_SIZE 32
-#define BASE_BOARD_ASSET_TAG_SIZE 32
-#define BASE_BOARD_LOCATION_SIZE 32
+#define BASE_BOARD_MANUFACTURER_SIZE 65
+#define BASE_BOARD_PRODUCT_NAME_SIZE 65
+#define BASE_BOARD_VERSION_SIZE 65
+#define BASE_BOARD_SERIAL_SIZE 65
+#define BASE_BOARD_ASSET_TAG_SIZE 65
+#define BASE_BOARD_LOCATION_SIZE 65
#define BASE_BOARD_FEATURES_SIZE 32
#define BASE_BOARD_TYPE_SIZE 32
#define BASE_BOARD_NB_ELEMENTS 5
+#define BASE_BOARD_DEVICE_DESCRIPTION 65
+
extern const char *base_board_features_strings[];
/* this struct have BASE_BOARD_NB_ELEMENTS */
@@ -51,7 +53,7 @@ typedef struct {
struct {
char type[16];
uint8_t status;
- char description[10];
+ char description[BASE_BOARD_DEVICE_DESCRIPTION];
} devices_information[10];
} s_base_board;
diff --git a/com32/gplinclude/dmi/dmi_battery.h b/com32/gplinclude/dmi/dmi_battery.h
index fae7acb5..c321aa9c 100644
--- a/com32/gplinclude/dmi/dmi_battery.h
+++ b/com32/gplinclude/dmi/dmi_battery.h
@@ -16,11 +16,11 @@
#include <stdbool.h>
#include <inttypes.h>
-#define BATTERY_LOCATION_SIZE 255
-#define BATTERY_MANUFACTURER_SIZE 255
-#define BATTERY_MANUFACTURE_DATE_SIZE 255
-#define BATTERY_SERIAL_SIZE 255
-#define BATTERY_DEVICE_NAME_SIZE 255
+#define BATTERY_LOCATION_SIZE 65
+#define BATTERY_MANUFACTURER_SIZE 65
+#define BATTERY_MANUFACTURE_DATE_SIZE 65
+#define BATTERY_SERIAL_SIZE 65
+#define BATTERY_DEVICE_NAME_SIZE 65
#define BATTERY_CHEMISTRY_SIZE 32
#define BATTERY_CAPACITY_SIZE 16
#define BATTERY_DESIGN_VOLTAGE_SIZE 16
@@ -28,7 +28,7 @@
#define BATTERY_MAXIMUM_ERROR_SIZE 32
#define BATTERY_SBDS_SERIAL_SIZE 32
#define BATTERY_SBDS_MANUFACTURE_DATE_SIZE 255
-#define BATTERY_SBDS_CHEMISTRY_SIZE 16
+#define BATTERY_SBDS_CHEMISTRY_SIZE 65
#define BATTERY_OEM_INFO_SIZE 255
typedef struct {
diff --git a/com32/gplinclude/dmi/dmi_bios.h b/com32/gplinclude/dmi/dmi_bios.h
index 53201acb..5d47e899 100644
--- a/com32/gplinclude/dmi/dmi_bios.h
+++ b/com32/gplinclude/dmi/dmi_bios.h
@@ -14,9 +14,9 @@
#define DMI_BIOS_H
#include "stdbool.h"
-#define BIOS_VENDOR_SIZE 32
-#define BIOS_VERSION_SIZE 32
-#define BIOS_RELEASE_SIZE 16
+#define BIOS_VENDOR_SIZE 65
+#define BIOS_VERSION_SIZE 65
+#define BIOS_RELEASE_SIZE 65
#define BIOS_RUNTIME_SIZE_UNIT_SIZE 16
#define BIOS_ROM_UNIT_SIZE 16
#define BIOS_BIOS_REVISION_SIZE 16
diff --git a/com32/gplinclude/dmi/dmi_cache.h b/com32/gplinclude/dmi/dmi_cache.h
index cfd7114e..df3cfbfb 100644
--- a/com32/gplinclude/dmi/dmi_cache.h
+++ b/com32/gplinclude/dmi/dmi_cache.h
@@ -22,8 +22,10 @@
#include "stdbool.h"
+#define CACHE_SOCKET_DESIGNATION_SIZE 65
+
typedef struct {
- char socket_designation[32];
+ char socket_designation[CACHE_SOCKET_DESIGNATION_SIZE];
char configuration[32];
char mode[32];
char location[8];
diff --git a/com32/gplinclude/dmi/dmi_chassis.h b/com32/gplinclude/dmi/dmi_chassis.h
index 88433ea1..c9a768af 100644
--- a/com32/gplinclude/dmi/dmi_chassis.h
+++ b/com32/gplinclude/dmi/dmi_chassis.h
@@ -13,12 +13,12 @@
#ifndef DMI_CHASSIS_H
#define DMI_CHASSIS_H
-#define CHASSIS_MANUFACTURER_SIZE 32
+#define CHASSIS_MANUFACTURER_SIZE 65
#define CHASSIS_TYPE_SIZE 16
#define CHASSIS_LOCK_SIZE 16
-#define CHASSIS_VERSION_SIZE 16
-#define CHASSIS_SERIAL_SIZE 32
-#define CHASSIS_ASSET_TAG_SIZE 32
+#define CHASSIS_VERSION_SIZE 65
+#define CHASSIS_SERIAL_SIZE 65
+#define CHASSIS_ASSET_TAG_SIZE 65
#define CHASSIS_BOOT_UP_STATE_SIZE 32
#define CHASSIS_POWER_SUPPLY_STATE_SIZE 32
#define CHASSIS_THERMAL_STATE_SIZE 32
diff --git a/com32/gplinclude/dmi/dmi_memory.h b/com32/gplinclude/dmi/dmi_memory.h
index 4d0ad442..aea16a07 100644
--- a/com32/gplinclude/dmi/dmi_memory.h
+++ b/com32/gplinclude/dmi/dmi_memory.h
@@ -13,21 +13,22 @@
#ifndef DMI_MEMORY_H
#define DMI_MEMORY_H
-#define MEMORY_MANUFACTURER_SIZE 32
+#define MEMORY_MANUFACTURER_SIZE 65
#define MEMORY_ERROR_SIZE 16
#define MEMORY_TOTAL_WIDTH_SIZE 16
#define MEMORY_DATA_WIDTH_SIZE 16
#define MEMORY_SIZE_SIZE 32
#define MEMORY_FORM_FACTOR_SIZE 32
#define MEMORY_DEVICE_SET_SIZE 32
-#define MEMORY_DEVICE_LOCATOR_SIZE 32
-#define MEMORY_BANK_LOCATOR_SIZE 32
+#define MEMORY_DEVICE_LOCATOR_SIZE 65
+#define MEMORY_BANK_LOCATOR_SIZE 65
#define MEMORY_TYPE_SIZE 32
#define MEMORY_TYPE_DETAIL_SIZE 16
#define MEMORY_SPEED_SIZE 16
-#define MEMORY_SERIAL_SIZE 16
-#define MEMORY_ASSET_TAG_SIZE 16
-#define MEMORY_PART_NUMBER_SIZE 16
+#define MEMORY_SERIAL_SIZE 65
+#define MEMORY_ASSET_TAG_SIZE 65
+#define MEMORY_PART_NUMBER_SIZE 65
+#define MEMORY_SOCKET_DESIGNATION_SIZE 65
typedef struct {
char manufacturer[MEMORY_MANUFACTURER_SIZE];
@@ -50,7 +51,7 @@ typedef struct {
} s_memory;
typedef struct {
- char socket_designation[8];
+ char socket_designation[MEMORY_SOCKET_DESIGNATION_SIZE];
char bank_connections[8];
char speed[8];
char type[48];
diff --git a/com32/gplinclude/dmi/dmi_processor.h b/com32/gplinclude/dmi/dmi_processor.h
index 6107d31d..dee76649 100644
--- a/com32/gplinclude/dmi/dmi_processor.h
+++ b/com32/gplinclude/dmi/dmi_processor.h
@@ -15,18 +15,18 @@
#include "stdbool.h"
#include "string.h"
-#define PROCESSOR_SOCKET_DESIGNATION_SIZE 32
+#define PROCESSOR_SOCKET_DESIGNATION_SIZE 65
#define PROCESSOR_TYPE_SIZE 32
#define PROCESSOR_FAMILY_SIZE 32
-#define PROCESSOR_MANUFACTURER_SIZE 64
-#define PROCESSOR_VERSION_SIZE 64
+#define PROCESSOR_MANUFACTURER_SIZE 65
+#define PROCESSOR_VERSION_SIZE 65
#define PROCESSOR_VOLTAGE_SIZE 16
#define PROCESSOR_STATUS_SIZE 16
#define PROCESSOR_UPGRADE_SIZE 16
#define PROCESSOR_CACHE_SIZE 16
-#define PROCESSOR_SERIAL_SIZE 32
-#define PROCESSOR_ASSET_TAG_SIZE 32
-#define PROCESSOR_PART_NUMBER_SIZE 32
+#define PROCESSOR_SERIAL_SIZE 65
+#define PROCESSOR_ASSET_TAG_SIZE 65
+#define PROCESSOR_PART_NUMBER_SIZE 65
#define PROCESSOR_ID_SIZE 32
#define PROCESSOR_FLAGS_ELEMENTS 32
@@ -97,6 +97,9 @@ typedef struct {
char asset_tag[PROCESSOR_ASSET_TAG_SIZE];
char part_number[PROCESSOR_PART_NUMBER_SIZE];
char id[PROCESSOR_ID_SIZE];
+ uint16_t core_count;
+ uint16_t core_enabled;
+ uint16_t thread_count;
s_dmi_cpu_flags cpu_flags;
s_signature signature;
/* The filled field have to be set to true when the dmitable implement that item */
diff --git a/com32/gplinclude/dmi/dmi_system.h b/com32/gplinclude/dmi/dmi_system.h
index 6bb053ff..5c892e00 100644
--- a/com32/gplinclude/dmi/dmi_system.h
+++ b/com32/gplinclude/dmi/dmi_system.h
@@ -13,14 +13,14 @@
#ifndef DMI_SYSTEM_H
#define DMI_SYSTEM_H
-#define SYSTEM_MANUFACTURER_SIZE 32
-#define SYSTEM_PRODUCT_NAME_SIZE 32
-#define SYSTEM_VERSION_SIZE 16
-#define SYSTEM_SERIAL_SIZE 32
+#define SYSTEM_MANUFACTURER_SIZE 65
+#define SYSTEM_PRODUCT_NAME_SIZE 65
+#define SYSTEM_VERSION_SIZE 65
+#define SYSTEM_SERIAL_SIZE 65
#define SYSTEM_UUID_SIZE 40
#define SYSTEM_WAKEUP_TYPE_SIZE 32
-#define SYSTEM_SKU_NUMBER_SIZE 32
-#define SYSTEM_FAMILY_SIZE 32
+#define SYSTEM_SKU_NUMBER_SIZE 65
+#define SYSTEM_FAMILY_SIZE 65
#define SYSTEM_BOOT_STATUS_SIZE 50
#define SYSTEM_CONFIGURATION_OPTIONS_SIZE 50
diff --git a/com32/gpllib/dmi/dmi.c b/com32/gpllib/dmi/dmi.c
index 507b11ac..ef84e1e8 100644
--- a/com32/gpllib/dmi/dmi.c
+++ b/com32/gpllib/dmi/dmi.c
@@ -299,6 +299,35 @@ static void dmi_base_board_features(uint8_t code, s_dmi * dmi)
}
}
+static void dmi_base_board_type(uint8_t code, s_dmi * dmi)
+{
+ /* 3.3.3.2 */
+ static const char *type[] = {
+ "Unknown", /* 0x01 */
+ "Other",
+ "Server Blade",
+ "Connectivity Switch",
+ "System Management Module",
+ "Processor Module",
+ "I/O Module",
+ "Memory Module",
+ "Daughter Board",
+ "Motherboard",
+ "Processor+Memory Module",
+ "Processor+I/O Module",
+ "Interconnect Board" /* 0x0D */
+ };
+
+ if (code >= 0x01 && code <= 0x0D) {
+ strlcpy(dmi->base_board.type, type[code],
+ sizeof(dmi->base_board.type));
+ } else {
+ strlcpy(dmi->base_board.type, out_of_spec,
+ sizeof(dmi->base_board.type));
+ }
+ return;
+}
+
static void dmi_processor_voltage(uint8_t code, s_dmi * dmi)
{
/* 3.3.5.4 */
@@ -652,8 +681,7 @@ void dmi_decode(struct dmi_header *h, uint16_t ver, s_dmi * dmi)
dmi_base_board_features(data[0x09], dmi);
strlcpy(dmi->base_board.location, dmi_string(h, data[0x0A]),
sizeof(dmi->base_board.location));
- strlcpy(dmi->base_board.type, dmi_string(h, data[0x0D]),
- sizeof(dmi->base_board.type));
+ dmi_base_board_type(data[0x0D], dmi);
if (h->length < 0x0F + data[0x0E] * sizeof(uint16_t))
break;
break;
@@ -743,6 +771,14 @@ void dmi_decode(struct dmi_header *h, uint16_t ver, s_dmi * dmi)
sizeof(dmi->processor.asset_tag));
strlcpy(dmi->processor.part_number, dmi_string(h, data[0x22]),
sizeof(dmi->processor.part_number));
+ dmi->processor.core_count = 0;
+ dmi->processor.core_enabled = 0;
+ dmi->processor.thread_count = 0;
+ if (h->length < 0x28)
+ break;
+ dmi->processor.core_count = data[0x23];
+ dmi->processor.core_enabled = data[0x24];
+ dmi->processor.thread_count = data[0x25];
break;
case 6: /* 3.3.7 Memory Module Information */
if (h->length < 0x0C)
diff --git a/com32/gpllib/dmi/dmi_cache.c b/com32/gpllib/dmi/dmi_cache.c
index 4c3f83ce..67a43d0b 100644
--- a/com32/gpllib/dmi/dmi_cache.c
+++ b/com32/gpllib/dmi/dmi_cache.c
@@ -125,10 +125,15 @@ const char *dmi_cache_associativity(uint8_t code)
"4-way Set-associative",
"Fully Associative",
"8-way Set-associative",
- "16-way Set-associative" /* 0x08 */
+ "16-way Set-associative", /* 0x08 */
+ "12-way Set-associative",
+ "24-way Set-associative",
+ "32-way Set-associative",
+ "48-way Set-associative",
+ "64-way Set-associative" /* 0x0D */
};
- if (code >= 0x01 && code <= 0x08)
+ if (code >= 0x01 && code <= 0x0D)
return type[code - 0x01];
return out_of_spec;
}
diff --git a/com32/gpllib/dmi/dmi_memory.c b/com32/gpllib/dmi/dmi_memory.c
index 21458293..36937539 100644
--- a/com32/gpllib/dmi/dmi_memory.c
+++ b/com32/gpllib/dmi/dmi_memory.c
@@ -124,10 +124,15 @@ const char *dmi_memory_device_type(uint8_t code)
"RDRAM",
"DDR",
"DDR2",
- "DDR2 FB-DIMM" /* 0x14 */
+ "DDR2 FB-DIMM", /* 0x14 */
+ NULL,
+ NULL,
+ NULL,
+ "DDR3", /* 0x18 */
+ "FBD2" /* 0x19 */
};
- if (code >= 0x01 && code <= 0x14)
+ if (code >= 0x01 && code <= 0x19)
return type[code - 0x01];
return out_of_spec;
}
diff --git a/com32/gpllib/dmi/dmi_processor.c b/com32/gpllib/dmi/dmi_processor.c
index 1cd9d1ba..fe2ef63a 100644
--- a/com32/gpllib/dmi/dmi_processor.c
+++ b/com32/gpllib/dmi/dmi_processor.c
@@ -49,6 +49,7 @@ const char *dmi_processor_type(uint8_t code)
const char *dmi_processor_family(uint8_t code, char *manufacturer)
{
/* 3.3.5.2 */
+ /* TODO : Need to implement code/value (see dmidecode) insteed of array to address large index */
static const char *family[256] = {
NULL, /* 0x00 */
"Other",
@@ -221,11 +222,11 @@ const char *dmi_processor_family(uint8_t code, char *manufacturer)
"Dual-Core Xeon 7100",
"Quad-Core Xeon 5400",
"Quad-Core Xeon", /* 0xAA */
- NULL,
- NULL,
- NULL,
- NULL,
- NULL, /* 0xAF */
+ "Dual-Core Xeon 5200",
+ "Dual-Core Xeon 7200",
+ "Quad-Core Xeon 7300",
+ "Quad-Core Xeon 7400",
+ "Multi-Core Xeon 7400", /* 0xAF */
"Pentium III Xeon",
"Pentium III Speedstep",
"Pentium 4",
@@ -248,8 +249,8 @@ const char *dmi_processor_family(uint8_t code, char *manufacturer)
"Core 2 Extreme Mobile",
"Core 2 Duo Mobile",
"Core 2 Solo Mobile",
- NULL,
- NULL, /* 0xC7 */
+ "Core i7",
+ "Dual-Core Celeron", /* 0xC7 */
"IBM390",
"G4",
"G5",
@@ -264,16 +265,16 @@ const char *dmi_processor_family(uint8_t code, char *manufacturer)
"C7-D",
"C7",
"Eden",
- NULL, /*0xD6 */
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
+ "Multi-Core Xeon", /*0xD6 */
+ "Dual-Core Xeon 3xxx",
+ "Quad-Core Xeon 3xxx", /*0xD8 */
NULL,
+ "Dual-Core Xeon 5xxx", /*0xDA */
+ "Quad-Core Xeon 5xxx",
NULL,
+ "Dual-Core Xeon 7xxx", /*0xDD */
+ "Quad-Core Xeon 7xxx",
+ "Multi-Core Xeon 7xxx",
NULL, /*0xE0 */
NULL,
NULL,
@@ -373,9 +374,10 @@ const char *dmi_processor_upgrade(uint8_t code)
"Socket S1",
"Socket AM2",
"Socket F (1207)"
+ "Socket LGA1366" /* 0x19 */
};
- if (code >= 0x01 && code <= 0x18)
+ if (code >= 0x01 && code <= 0x19)
return upgrade[code - 0x01];
return out_of_spec;
}
diff --git a/com32/hdt/hdt-cli-cpu.c b/com32/hdt/hdt-cli-cpu.c
index ca095a6c..6d764ce2 100644
--- a/com32/hdt/hdt-cli-cpu.c
+++ b/com32/hdt/hdt-cli-cpu.c
@@ -51,6 +51,8 @@ void main_show_cpu(int argc __unused, char **argv __unused,
more_printf(" Manufacturer : %s \n", hardware->cpu.vendor);
more_printf(" Product : %s \n", hardware->cpu.model);
more_printf(" CPU Cores : %d \n", hardware->cpu.num_cores);
+ if (hardware->dmi.processor.thread_count != 0)
+ more_printf(" CPU Threads : %d \n", hardware->dmi.processor.thread_count);
more_printf(" L2 Cache : %dK\n", hardware->cpu.l2_cache_size);
memset(features, 0, sizeof(features));
@@ -112,6 +114,10 @@ static void show_cpu(int argc __unused, char **argv __unused,
more_printf("Vendor : %s\n", hardware->cpu.vendor);
more_printf("Model : %s\n", hardware->cpu.model);
more_printf("CPU Cores : %d\n", hardware->cpu.num_cores);
+ if (hardware->dmi.processor.core_enabled != 0)
+ more_printf("CPU Enable: %d\n", hardware->dmi.processor.core_enabled);
+ if (hardware->dmi.processor.thread_count != 0)
+ more_printf("CPU Thread: %d \n", hardware->dmi.processor.thread_count);
more_printf("L1 Cache : %dK + %dK (I + D) \n",
hardware->cpu.l1_instruction_cache_size,
hardware->cpu.l1_data_cache_size);
diff --git a/com32/hdt/hdt-cli-dmi.c b/com32/hdt/hdt-cli-dmi.c
index 313445cd..45cbb240 100644
--- a/com32/hdt/hdt-cli-dmi.c
+++ b/com32/hdt/hdt-cli-dmi.c
@@ -350,6 +350,13 @@ static void show_dmi_cpu(int argc __unused, char **argv __unused,
more_printf(" Serial : %s\n", hardware->dmi.processor.serial);
more_printf(" Part Number : %s\n",
hardware->dmi.processor.part_number);
+ if (hardware->dmi.processor.core_count != 0)
+ more_printf(" Cores Count : %d\n", hardware->dmi.processor.core_count);
+ if (hardware->dmi.processor.core_enabled != 0)
+ more_printf(" Cores Enabled : %d\n", hardware->dmi.processor.core_enabled);
+ if (hardware->dmi.processor.thread_count != 0)
+ more_printf(" Threads Count : %d\n", hardware->dmi.processor.thread_count);
+
more_printf(" ID : %s\n", hardware->dmi.processor.id);
for (int i = 0; i < PROCESSOR_FLAGS_ELEMENTS; i++) {
if (((bool *) (&hardware->dmi.processor.cpu_flags))[i] == true) {
diff --git a/com32/hdt/hdt-menu-processor.c b/com32/hdt/hdt-menu-processor.c
index ad4a8bae..f28833b5 100644
--- a/com32/hdt/hdt-menu-processor.c
+++ b/com32/hdt/hdt-menu-processor.c
@@ -84,6 +84,22 @@ void compute_processor(struct s_my_menu *menu, struct s_hardware *hardware)
add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
menu->items_count++;
+ if (hardware->dmi.processor.core_enabled != 0) {
+ snprintf(buffer, sizeof buffer, "CPU Enable: %d", hardware->dmi.processor.core_enabled);
+ snprintf(statbuffer, sizeof statbuffer, "Number of CPU Enabled : %d",
+ hardware->dmi.processor.core_enabled);
+ add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
+ menu->items_count++;
+ }
+
+ if (hardware->dmi.processor.thread_count != 0) {
+ snprintf(buffer, sizeof buffer, "CPU Thread: %d", hardware->dmi.processor.thread_count);
+ snprintf(statbuffer, sizeof statbuffer, "Number of CPU Threads : %d",
+ hardware->dmi.processor.thread_count);
+ add_item(buffer, statbuffer, OPT_INACTIVE, NULL, 0);
+ menu->items_count++;
+ }
+
snprintf(buffer, sizeof buffer, "L1 Cache : %dK + %dK (I+D)",
hardware->cpu.l1_instruction_cache_size,
hardware->cpu.l1_data_cache_size);
diff --git a/com32/hdt/hdt-menu-summary.c b/com32/hdt/hdt-menu-summary.c
index d02f3c30..b9395559 100644
--- a/com32/hdt/hdt-menu-summary.c
+++ b/com32/hdt/hdt-menu-summary.c
@@ -54,8 +54,12 @@ void compute_summarymenu(struct s_my_menu *menu, struct s_hardware *hardware)
char features[SUBMENULEN + 1];
memset(features, 0, sizeof(features));
- sprintf(features, "%d cores, %dK L2 Cache", hardware->cpu.num_cores,
- hardware->cpu.l2_cache_size);
+ if (hardware->dmi.processor.thread_count != 0)
+ sprintf(buffer, ", %d thread", hardware->dmi.processor.thread_count);
+ else
+ buffer[0] = 0x00;
+ sprintf(features, "%d core%s, %dK L2 Cache", hardware->cpu.num_cores,
+ buffer, hardware->cpu.l2_cache_size);
if (hardware->cpu.flags.lm)
strcat(features, ", 64bit");
else
diff --git a/com32/lua/src/dmi.c b/com32/lua/src/dmi.c
index d0305333..c8329d33 100644
--- a/com32/lua/src/dmi.c
+++ b/com32/lua/src/dmi.c
@@ -267,6 +267,18 @@ static int dmi_gettable(lua_State *L)
lua_pushstring(L, dmi.processor.id);
lua_settable(L,-3);
+ lua_pushstring(L, "processor.core_count");
+ lua_pushnumber(L, dmi.processor.core_count);
+ lua_settable(L,-3);
+
+ lua_pushstring(L, "processor.core_enabled");
+ lua_pushnumber(L, dmi.processor.core_enabled);
+ lua_settable(L,-3);
+
+ lua_pushstring(L, "processor.thread_count");
+ lua_pushnumber(L, dmi.processor.thread_count);
+ lua_settable(L,-3);
+
/* set global variable: lua_setglobal(L, "dmitable"); */
/* return number of return values on stack */
diff --git a/com32/modules/dmitest.c b/com32/modules/dmitest.c
index b81d0cef..294585bb 100644
--- a/com32/modules/dmitest.c
+++ b/com32/modules/dmitest.c
@@ -165,6 +165,12 @@ void display_cpu(s_dmi * dmi)
moreprintf("\tCache L3 Handle %s\n", dmi->processor.cache3);
moreprintf("\tSerial %s\n", dmi->processor.serial);
moreprintf("\tPart Number %s\n", dmi->processor.part_number);
+ if (dmi->processor.core_count != 0)
+ moreprintf("\tCores Count %d\n", dmi->processor.core_count);
+ if (dmi->processor.core_enabled != 0)
+ moreprintf("\tCores Enabled %d\n", dmi->processor.core_enabled);
+ if (dmi->processor.thread_count != 0)
+ moreprintf("\tThreads Count %d\n", dmi->processor.thread_count);
moreprintf("\tID %s\n", dmi->processor.id);
display_processor_flags(dmi);
}