aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--gpxe/src/drivers/net/phantom/nx_bitops.h192
-rw-r--r--gpxe/src/drivers/net/phantom/nxhal_nic_interface.h499
-rw-r--r--gpxe/src/drivers/net/phantom/phantom.c1945
-rw-r--r--gpxe/src/drivers/net/phantom/phantom.h272
-rw-r--r--gpxe/src/drivers/net/phantom/phantom_hw.h182
-rw-r--r--gpxe/src/drivers/net/virtio-net.c492
-rw-r--r--gpxe/src/drivers/net/virtio-net.h44
-rw-r--r--gpxe/src/drivers/net/virtio-pci.h94
-rw-r--r--gpxe/src/drivers/net/virtio-ring.h93
-rw-r--r--gpxe/src/util/Option/ROM.pm459
-rw-r--r--gpxe/src/util/mergerom.pl80
11 files changed, 4352 insertions, 0 deletions
diff --git a/gpxe/src/drivers/net/phantom/nx_bitops.h b/gpxe/src/drivers/net/phantom/nx_bitops.h
new file mode 100644
index 00000000..33c8fbab
--- /dev/null
+++ b/gpxe/src/drivers/net/phantom/nx_bitops.h
@@ -0,0 +1,192 @@
+#ifndef _NX_BITOPS_H
+#define _NX_BITOPS_H
+
+/*
+ * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/**
+ * @file
+ *
+ * NetXen bit operations
+ *
+ */
+
+/** Datatype used to represent a bit in the pseudo-structures */
+typedef unsigned char pseudo_bit_t;
+
+/**
+ * Wrapper structure for pseudo_bit_t structures
+ *
+ * This structure provides a wrapper around pseudo_bit_t structures.
+ * It has the correct size, and also encapsulates type information
+ * about the underlying pseudo_bit_t-based structure, which allows the
+ * NX_FILL etc. macros to work without requiring explicit type
+ * information.
+ */
+#define NX_PSEUDO_BIT_STRUCT( _structure ) \
+ union { \
+ uint8_t bytes[ sizeof ( _structure ) / 8 ]; \
+ uint64_t qwords[ sizeof ( _structure ) / 64 ]; \
+ _structure *dummy[0]; \
+ } u;
+
+/** Get pseudo_bit_t structure type from wrapper structure pointer */
+#define NX_PSEUDO_STRUCT( _ptr ) \
+ typeof ( *((_ptr)->u.dummy[0]) )
+
+/** Bit offset of a field within a pseudo_bit_t structure */
+#define NX_BIT_OFFSET( _ptr, _field ) \
+ offsetof ( NX_PSEUDO_STRUCT ( _ptr ), _field )
+
+/** Bit width of a field within a pseudo_bit_t structure */
+#define NX_BIT_WIDTH( _ptr, _field ) \
+ sizeof ( ( ( NX_PSEUDO_STRUCT ( _ptr ) * ) NULL )->_field )
+
+/** Qword offset of a field within a pseudo_bit_t structure */
+#define NX_QWORD_OFFSET( _ptr, _field ) \
+ ( NX_BIT_OFFSET ( _ptr, _field ) / 64 )
+
+/** Qword bit offset of a field within a pseudo_bit_t structure
+ *
+ * Yes, using mod-64 would work, but would lose the check for the
+ * error of specifying a mismatched field name and qword index.
+ */
+#define NX_QWORD_BIT_OFFSET( _ptr, _index, _field ) \
+ ( NX_BIT_OFFSET ( _ptr, _field ) - ( 64 * (_index) ) )
+
+/** Bit mask for a field within a pseudo_bit_t structure */
+#define NX_BIT_MASK( _ptr, _field ) \
+ ( ( ~( ( uint64_t ) 0 ) ) >> \
+ ( 64 - NX_BIT_WIDTH ( _ptr, _field ) ) )
+
+/*
+ * Assemble native-endian qword from named fields and values
+ *
+ */
+
+#define NX_ASSEMBLE_1( _ptr, _index, _field, _value ) \
+ ( ( ( uint64_t) (_value) ) << \
+ NX_QWORD_BIT_OFFSET ( _ptr, _index, _field ) )
+
+#define NX_ASSEMBLE_2( _ptr, _index, _field, _value, ... ) \
+ ( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
+ NX_ASSEMBLE_1 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_ASSEMBLE_3( _ptr, _index, _field, _value, ... ) \
+ ( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
+ NX_ASSEMBLE_2 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_ASSEMBLE_4( _ptr, _index, _field, _value, ... ) \
+ ( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
+ NX_ASSEMBLE_3 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_ASSEMBLE_5( _ptr, _index, _field, _value, ... ) \
+ ( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
+ NX_ASSEMBLE_4 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_ASSEMBLE_6( _ptr, _index, _field, _value, ... ) \
+ ( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
+ NX_ASSEMBLE_5 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_ASSEMBLE_7( _ptr, _index, _field, _value, ... ) \
+ ( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
+ NX_ASSEMBLE_6 ( _ptr, _index, __VA_ARGS__ ) )
+
+/*
+ * Build native-endian (positive) qword bitmasks from named fields
+ *
+ */
+
+#define NX_MASK_1( _ptr, _index, _field ) \
+ ( NX_BIT_MASK ( _ptr, _field ) << \
+ NX_QWORD_BIT_OFFSET ( _ptr, _index, _field ) )
+
+#define NX_MASK_2( _ptr, _index, _field, ... ) \
+ ( NX_MASK_1 ( _ptr, _index, _field ) | \
+ NX_MASK_1 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_MASK_3( _ptr, _index, _field, ... ) \
+ ( NX_MASK_1 ( _ptr, _index, _field ) | \
+ NX_MASK_2 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_MASK_4( _ptr, _index, _field, ... ) \
+ ( NX_MASK_1 ( _ptr, _index, _field ) | \
+ NX_MASK_3 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_MASK_5( _ptr, _index, _field, ... ) \
+ ( NX_MASK_1 ( _ptr, _index, _field ) | \
+ NX_MASK_4 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_MASK_6( _ptr, _index, _field, ... ) \
+ ( NX_MASK_1 ( _ptr, _index, _field ) | \
+ NX_MASK_5 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_MASK_7( _ptr, _index, _field, ... ) \
+ ( NX_MASK_1 ( _ptr, _index, _field ) | \
+ NX_MASK_6 ( _ptr, _index, __VA_ARGS__ ) )
+
+/*
+ * Populate big-endian qwords from named fields and values
+ *
+ */
+
+#define NX_FILL( _ptr, _index, _assembled ) \
+ do { \
+ uint64_t *__ptr = &(_ptr)->u.qwords[(_index)]; \
+ uint64_t __assembled = (_assembled); \
+ *__ptr = cpu_to_le64 ( __assembled ); \
+ } while ( 0 )
+
+#define NX_FILL_1( _ptr, _index, ... ) \
+ NX_FILL ( _ptr, _index, NX_ASSEMBLE_1 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_FILL_2( _ptr, _index, ... ) \
+ NX_FILL ( _ptr, _index, NX_ASSEMBLE_2 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_FILL_3( _ptr, _index, ... ) \
+ NX_FILL ( _ptr, _index, NX_ASSEMBLE_3 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_FILL_4( _ptr, _index, ... ) \
+ NX_FILL ( _ptr, _index, NX_ASSEMBLE_4 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_FILL_5( _ptr, _index, ... ) \
+ NX_FILL ( _ptr, _index, NX_ASSEMBLE_5 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_FILL_6( _ptr, _index, ... ) \
+ NX_FILL ( _ptr, _index, NX_ASSEMBLE_6 ( _ptr, _index, __VA_ARGS__ ) )
+
+#define NX_FILL_7( _ptr, _index, ... ) \
+ NX_FILL ( _ptr, _index, NX_ASSEMBLE_7 ( _ptr, _index, __VA_ARGS__ ) )
+
+/** Extract value of named field */
+#define NX_GET64( _ptr, _field ) \
+ ( { \
+ unsigned int __index = NX_QWORD_OFFSET ( _ptr, _field ); \
+ uint64_t *__ptr = &(_ptr)->u.qwords[__index]; \
+ uint64_t __value = le64_to_cpu ( *__ptr ); \
+ __value >>= \
+ NX_QWORD_BIT_OFFSET ( _ptr, __index, _field ); \
+ __value &= NX_BIT_MASK ( _ptr, _field ); \
+ __value; \
+ } )
+
+/** Extract value of named field (for fields up to the size of a long) */
+#define NX_GET( _ptr, _field ) \
+ ( ( unsigned long ) NX_GET64 ( _ptr, _field ) )
+
+#endif /* _NX_BITOPS_H */
diff --git a/gpxe/src/drivers/net/phantom/nxhal_nic_interface.h b/gpxe/src/drivers/net/phantom/nxhal_nic_interface.h
new file mode 100644
index 00000000..aa05c725
--- /dev/null
+++ b/gpxe/src/drivers/net/phantom/nxhal_nic_interface.h
@@ -0,0 +1,499 @@
+/*
+ * Data types and structure for HAL - NIC interface.
+ *
+ */
+
+#ifndef _NXHAL_NIC_INTERFACE_H_
+#define _NXHAL_NIC_INTERFACE_H_
+
+/*****************************************************************************
+ * Simple Types
+ *****************************************************************************/
+
+typedef U32 nx_reg_addr_t;
+
+/*****************************************************************************
+ * Root crb-based firmware commands
+ *****************************************************************************/
+
+/* CRB Root Command
+
+ A single set of crbs is used across all physical/virtual
+ functions for capability queries, initialization, and
+ context creation/destruction.
+
+ There are 4 CRBS:
+ Command/Response CRB
+ Argument1 CRB
+ Argument2 CRB
+ Argument3 CRB
+ Signature CRB
+
+ The cmd/rsp crb is always intiated by the host via
+ a command code and always responded by the card with
+ a response code. The cmd and rsp codes are disjoint.
+ The sequence of use is always CMD, RSP, CLEAR CMD.
+
+ The arguments are for passing in command specific
+ and response specific parameters/data.
+
+ The signature is composed of a magic value, the
+ pci function id, and a command sequence id:
+ [7:0] = pci function
+ [15:8] = version
+ [31:16] = magic of 0xcafe
+
+ The pci function allows the card to take correct
+ action for the given particular commands.
+ The firmware will attempt to detect
+ an errant driver that has died while holding
+ the root crb hardware lock. Such an error condition
+ shows up as the cmd/rsp crb stuck in a non-clear state.
+
+ Interface Sequence:
+ Host always makes requests and firmware always responds.
+ Note that data field is always set prior to command field.
+
+ [READ] CMD/RSP CRB ARGUMENT FIELD
+ Host grab lock
+ Host -> CMD optional parameter
+ FW <- (Good) RSP-OK DATA
+ FW <- (Fail) RSP-FAIL optional failure code
+ Host -> CLEAR
+ Host release lock
+
+ [WRITE] CMD/RSP CRB ARGUMENT FIELD
+ Host grab lock
+ Host -> CMD DATA
+ FW <- (Good) RSP-OK optional write status
+ FW <- (Write) RSP-FAIL optional failure code
+ Host -> CLEAR
+ Host release lock
+
+*/
+
+
+/*****************************************************************************
+ * CMD/RSP
+ *****************************************************************************/
+
+#define NX_CDRP_SIGNATURE_TO_PCIFN(sign) ((sign) & 0xff)
+#define NX_CDRP_SIGNATURE_TO_VERSION(sign) (((sign)>>8) & 0xff)
+#define NX_CDRP_SIGNATURE_TO_MAGIC(sign) (((sign)>>16) & 0xffff)
+#define NX_CDRP_SIGNATURE_VALID(sign) \
+ ( NX_CDRP_SIGNATURE_TO_MAGIC(sign) == 0xcafe && \
+ NX_CDRP_SIGNATURE_TO_PCIFN(sign) < 8)
+#define NX_CDRP_SIGNATURE_MAKE(pcifn,version) \
+ ( ((pcifn) & 0xff) | \
+ (((version) & 0xff) << 8) | \
+ (0xcafe << 16) )
+
+#define NX_CDRP_CLEAR 0x00000000
+#define NX_CDRP_CMD_BIT 0x80000000
+
+/* All responses must have the NX_CDRP_CMD_BIT cleared
+ * in the crb NX_CDRP_CRB_OFFSET. */
+#define NX_CDRP_FORM_RSP(rsp) (rsp)
+#define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
+
+#define NX_CDRP_RSP_OK 0x00000001
+#define NX_CDRP_RSP_FAIL 0x00000002
+#define NX_CDRP_RSP_TIMEOUT 0x00000003
+
+/* All commands must have the NX_CDRP_CMD_BIT set in
+ * the crb NX_CDRP_CRB_OFFSET.
+ * The macros below do not have it explicitly set to
+ * allow their use in lookup tables */
+#define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
+#define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
+
+/* [CMD] Capability Vector [RSP] Capability Vector */
+#define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
+
+/* [CMD] - [RSP] Query Value */
+#define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
+
+/* [CMD] - [RSP] Query Value */
+#define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
+
+/* [CMD] - [RSP] Query Value */
+#define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
+
+/* [CMD] - [RSP] Query Value */
+#define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
+
+/* [CMD] - [RSP] Query Value */
+#define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
+
+/* [CMD] Rx Config DMA Addr [RSP] rcode */
+#define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
+
+/* [CMD] Rx Context Handle, Reset Kind [RSP] rcode */
+#define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
+
+/* [CMD] Tx Config DMA Addr [RSP] rcode */
+#define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
+
+/* [CMD] Tx Context Handle, Reset Kind [RSP] rcode */
+#define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
+
+/* [CMD] Stat setup dma addr - [RSP] Handle, rcode */
+#define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
+
+/* [CMD] Handle - [RSP] rcode */
+#define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
+
+/* [CMD] Handle - [RSP] rcode */
+#define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
+
+#define NX_CDRP_CMD_MAX 0x00000011
+
+/*****************************************************************************
+ * Capabilities
+ *****************************************************************************/
+
+#define NX_CAP_BIT(class, bit) (1 << bit)
+
+/* Class 0 (i.e. ARGS 1)
+ */
+#define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
+#define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
+#define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
+#define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
+#define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
+#define NX_CAP0_LRO NX_CAP_BIT(0, 5)
+#define NX_CAP0_LSO NX_CAP_BIT(0, 6)
+
+/* Class 1 (i.e. ARGS 2)
+ */
+#define NX_CAP1_NIC NX_CAP_BIT(1, 0)
+#define NX_CAP1_PXE NX_CAP_BIT(1, 1)
+#define NX_CAP1_CHIMNEY NX_CAP_BIT(1, 2)
+#define NX_CAP1_LSA NX_CAP_BIT(1, 3)
+#define NX_CAP1_RDMA NX_CAP_BIT(1, 4)
+#define NX_CAP1_ISCSI NX_CAP_BIT(1, 5)
+#define NX_CAP1_FCOE NX_CAP_BIT(1, 6)
+
+/* Class 2 (i.e. ARGS 3)
+ */
+
+/*****************************************************************************
+ * Rules
+ *****************************************************************************/
+
+typedef U32 nx_rx_rule_type_t;
+
+#define NX_RX_RULETYPE_DEFAULT 0
+#define NX_RX_RULETYPE_MAC 1
+#define NX_RX_RULETYPE_MAC_VLAN 2
+#define NX_RX_RULETYPE_MAC_RSS 3
+#define NX_RX_RULETYPE_MAC_VLAN_RSS 4
+#define NX_RX_RULETYPE_MAX 5
+
+typedef U32 nx_rx_rule_cmd_t;
+
+#define NX_RX_RULECMD_ADD 0
+#define NX_RX_RULECMD_REMOVE 1
+#define NX_RX_RULECMD_MAX 2
+
+typedef struct nx_rx_rule_arg_s {
+ union {
+ struct {
+ char mac[6];
+ } m;
+ struct {
+ char mac[6];
+ char vlan;
+ } mv;
+ struct {
+ char mac[6];
+ } mr;
+ struct {
+ char mac[6];
+ char vlan;
+ } mvr;
+ };
+ /* will be union of all the different args for rules */
+ U64 data;
+} nx_rx_rule_arg_t;
+
+typedef struct nx_rx_rule_s {
+ U32 id;
+ U32 active;
+ nx_rx_rule_arg_t arg;
+ nx_rx_rule_type_t type;
+} nx_rx_rule_t;
+
+/* MSG - REQUIRES TX CONTEXT */
+
+/* The rules can be added/deleted from both the
+ * host and card sides so rq/rsp are similar.
+ */
+typedef struct nx_hostmsg_rx_rule_s {
+ nx_rx_rule_cmd_t cmd;
+ nx_rx_rule_t rule;
+} nx_hostmsg_rx_rule_t;
+
+typedef struct nx_cardmsg_rx_rule_s {
+ nx_rcode_t rcode;
+ nx_rx_rule_cmd_t cmd;
+ nx_rx_rule_t rule;
+} nx_cardmsg_rx_rule_t;
+
+
+/*****************************************************************************
+ * Common to Rx/Tx contexts
+ *****************************************************************************/
+
+/*
+ * Context states
+ */
+
+typedef U32 nx_host_ctx_state_t;
+
+#define NX_HOST_CTX_STATE_FREED 0 /* Invalid state */
+#define NX_HOST_CTX_STATE_ALLOCATED 1 /* Not committed */
+/* The following states imply FW is aware of context */
+#define NX_HOST_CTX_STATE_ACTIVE 2
+#define NX_HOST_CTX_STATE_DISABLED 3
+#define NX_HOST_CTX_STATE_QUIESCED 4
+#define NX_HOST_CTX_STATE_MAX 5
+
+/*
+ * Interrupt mask crb use must be set identically on the Tx
+ * and Rx context configs across a pci function
+ */
+
+/* Rx and Tx have unique interrupt/crb */
+#define NX_HOST_INT_CRB_MODE_UNIQUE 0
+/* Rx and Tx share a common interrupt/crb */
+#define NX_HOST_INT_CRB_MODE_SHARED 1 /* <= LEGACY */
+/* Rx does not use a crb */
+#define NX_HOST_INT_CRB_MODE_NORX 2
+/* Tx does not use a crb */
+#define NX_HOST_INT_CRB_MODE_NOTX 3
+/* Neither Rx nor Tx use a crb */
+#define NX_HOST_INT_CRB_MODE_NORXTX 4
+
+/*
+ * Destroy Rx/Tx
+ */
+
+#define NX_DESTROY_CTX_RESET 0
+#define NX_DESTROY_CTX_D3_RESET 1
+#define NX_DESTROY_CTX_MAX 2
+
+
+/*****************************************************************************
+ * Tx
+ *****************************************************************************/
+
+/*
+ * Components of the host-request for Tx context creation.
+ * CRB - DOES NOT REQUIRE Rx/TX CONTEXT
+ */
+
+typedef struct nx_hostrq_cds_ring_s {
+ U64 host_phys_addr; /* Ring base addr */
+ U32 ring_size; /* Ring entries */
+ U32 rsvd; /* Padding */
+} nx_hostrq_cds_ring_t;
+
+typedef struct nx_hostrq_tx_ctx_s {
+ U64 host_rsp_dma_addr; /* Response dma'd here */
+ U64 cmd_cons_dma_addr; /* */
+ U64 dummy_dma_addr; /* */
+ U32 capabilities[4]; /* Flag bit vector */
+ U32 host_int_crb_mode; /* Interrupt crb usage */
+ U32 rsvd1; /* Padding */
+ U16 rsvd2; /* Padding */
+ U16 interrupt_ctl;
+ U16 msi_index;
+ U16 rsvd3; /* Padding */
+ nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
+ U8 reserved[128]; /* future expansion */
+} nx_hostrq_tx_ctx_t;
+
+typedef struct nx_cardrsp_cds_ring_s {
+ U32 host_producer_crb; /* Crb to use */
+ U32 interrupt_crb; /* Crb to use */
+} nx_cardrsp_cds_ring_t;
+
+typedef struct nx_cardrsp_tx_ctx_s {
+ U32 host_ctx_state; /* Starting state */
+ U16 context_id; /* Handle for context */
+ U8 phys_port; /* Physical id of port */
+ U8 virt_port; /* Virtual/Logical id of port */
+ nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
+ U8 reserved[128]; /* future expansion */
+} nx_cardrsp_tx_ctx_t;
+
+#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) \
+ ( sizeof(HOSTRQ_TX))
+
+#define SIZEOF_CARDRSP_TX(CARDRSP_TX) \
+ ( sizeof(CARDRSP_TX))
+
+/*****************************************************************************
+ * Rx
+ *****************************************************************************/
+
+/*
+ * RDS ring mapping to producer crbs
+ */
+
+/* Each ring has a unique crb */
+#define NX_HOST_RDS_CRB_MODE_UNIQUE 0 /* <= LEGACY */
+
+/* All configured RDS Rings share common crb:
+ 1 Ring - same as unique
+ 2 Rings - 16, 16
+ 3 Rings - 10, 10, 10 */
+#define NX_HOST_RDS_CRB_MODE_SHARED 1
+
+/* Bit usage is specified per-ring using the
+ ring's size. Sum of bit lengths must be <= 32.
+ Packing is [Ring N] ... [Ring 1][Ring 0] */
+#define NX_HOST_RDS_CRB_MODE_CUSTOM 2
+#define NX_HOST_RDS_CRB_MODE_MAX 3
+
+
+/*
+ * RDS Ting Types
+ */
+
+#define NX_RDS_RING_TYPE_NORMAL 0
+#define NX_RDS_RING_TYPE_JUMBO 1
+#define NX_RDS_RING_TYPE_LRO 2
+#define NX_RDS_RING_TYPE_MAX 3
+
+/*
+ * Components of the host-request for Rx context creation.
+ * CRB - DOES NOT REQUIRE Rx/TX CONTEXT
+ */
+
+typedef struct nx_hostrq_sds_ring_s {
+ U64 host_phys_addr; /* Ring base addr */
+ U32 ring_size; /* Ring entries */
+ U16 msi_index;
+ U16 rsvd; /* Padding */
+} nx_hostrq_sds_ring_t;
+
+typedef struct nx_hostrq_rds_ring_s {
+ U64 host_phys_addr; /* Ring base addr */
+ U64 buff_size; /* Packet buffer size */
+ U32 ring_size; /* Ring entries */
+ U32 ring_kind; /* Class of ring */
+} nx_hostrq_rds_ring_t;
+
+typedef struct nx_hostrq_rx_ctx_s {
+ U64 host_rsp_dma_addr; /* Response dma'd here */
+ U32 capabilities[4]; /* Flag bit vector */
+ U32 host_int_crb_mode; /* Interrupt crb usage */
+ U32 host_rds_crb_mode; /* RDS crb usage */
+ /* These ring offsets are relative to data[0] below */
+ U32 rds_ring_offset; /* Offset to RDS config */
+ U32 sds_ring_offset; /* Offset to SDS config */
+ U16 num_rds_rings; /* Count of RDS rings */
+ U16 num_sds_rings; /* Count of SDS rings */
+ U16 rsvd1; /* Padding */
+ U16 rsvd2; /* Padding */
+ U8 reserved[128]; /* reserve space for future expansion*/
+ /* MUST BE 64-bit aligned.
+ The following is packed:
+ - N hostrq_rds_rings
+ - N hostrq_sds_rings */
+ char data[0];
+} nx_hostrq_rx_ctx_t;
+
+typedef struct nx_cardrsp_rds_ring_s {
+ U32 host_producer_crb; /* Crb to use */
+ U32 rsvd1; /* Padding */
+} nx_cardrsp_rds_ring_t;
+
+typedef struct nx_cardrsp_sds_ring_s {
+ U32 host_consumer_crb; /* Crb to use */
+ U32 interrupt_crb; /* Crb to use */
+} nx_cardrsp_sds_ring_t;
+
+typedef struct nx_cardrsp_rx_ctx_s {
+ /* These ring offsets are relative to data[0] below */
+ U32 rds_ring_offset; /* Offset to RDS config */
+ U32 sds_ring_offset; /* Offset to SDS config */
+ U32 host_ctx_state; /* Starting State */
+ U32 num_fn_per_port; /* How many PCI fn share the port */
+ U16 num_rds_rings; /* Count of RDS rings */
+ U16 num_sds_rings; /* Count of SDS rings */
+ U16 context_id; /* Handle for context */
+ U8 phys_port; /* Physical id of port */
+ U8 virt_port; /* Virtual/Logical id of port */
+ U8 reserved[128]; /* save space for future expansion */
+ /* MUST BE 64-bit aligned.
+ The following is packed:
+ - N cardrsp_rds_rings
+ - N cardrs_sds_rings */
+ char data[0];
+} nx_cardrsp_rx_ctx_t;
+
+#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
+ ( sizeof(HOSTRQ_RX) + \
+ (rds_rings)*(sizeof (nx_hostrq_rds_ring_t)) + \
+ (sds_rings)*(sizeof (nx_hostrq_sds_ring_t)) )
+
+#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
+ ( sizeof(CARDRSP_RX) + \
+ (rds_rings)*(sizeof (nx_cardrsp_rds_ring_t)) + \
+ (sds_rings)*(sizeof (nx_cardrsp_sds_ring_t)) )
+
+
+/*****************************************************************************
+ * Statistics
+ *****************************************************************************/
+
+/*
+ * The model of statistics update to use
+ */
+
+#define NX_STATISTICS_MODE_INVALID 0
+
+/* Permanent setup; Updates are only sent on explicit request
+ (NX_CDRP_CMD_GET_STATISTICS) */
+#define NX_STATISTICS_MODE_PULL 1
+
+/* Permanent setup; Updates are sent automatically and on
+ explicit request (NX_CDRP_CMD_GET_STATISTICS) */
+#define NX_STATISTICS_MODE_PUSH 2
+
+/* One time stat update. */
+#define NX_STATISTICS_MODE_SINGLE_SHOT 3
+
+#define NX_STATISTICS_MODE_MAX 4
+
+/*
+ * What set of stats
+ */
+#define NX_STATISTICS_TYPE_INVALID 0
+#define NX_STATISTICS_TYPE_NIC_RX_CORE 1
+#define NX_STATISTICS_TYPE_NIC_TX_CORE 2
+#define NX_STATISTICS_TYPE_NIC_RX_ALL 3
+#define NX_STATISTICS_TYPE_NIC_TX_ALL 4
+#define NX_STATISTICS_TYPE_MAX 5
+
+
+/*
+ * Request to setup statistics gathering.
+ * CRB - DOES NOT REQUIRE Rx/TX CONTEXT
+ */
+
+typedef struct nx_hostrq_stat_setup_s {
+ U64 host_stat_buffer; /* Where to dma stats */
+ U32 host_stat_size; /* Size of stat buffer */
+ U16 context_id; /* Which context */
+ U16 stat_type; /* What class of stats */
+ U16 stat_mode; /* When to update */
+ U16 stat_interval; /* Frequency of update */
+} nx_hostrq_stat_setup_t;
+
+
+
+#endif /* _NXHAL_NIC_INTERFACE_H_ */
diff --git a/gpxe/src/drivers/net/phantom/phantom.c b/gpxe/src/drivers/net/phantom/phantom.c
new file mode 100644
index 00000000..509a7096
--- /dev/null
+++ b/gpxe/src/drivers/net/phantom/phantom.c
@@ -0,0 +1,1945 @@
+/*
+ * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
+ * Copyright (C) 2008 NetXen, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <assert.h>
+#include <byteswap.h>
+#include <gpxe/pci.h>
+#include <gpxe/malloc.h>
+#include <gpxe/iobuf.h>
+#include <gpxe/netdevice.h>
+#include <gpxe/if_ether.h>
+#include <gpxe/ethernet.h>
+#include <gpxe/spi.h>
+#include "phantom.h"
+
+/**
+ * @file
+ *
+ * NetXen Phantom NICs
+ *
+ */
+
+/** Maximum time to wait for SPI lock */
+#define PHN_SPI_LOCK_TIMEOUT_MS 100
+
+/** Maximum time to wait for SPI command to be issued */
+#define PHN_SPI_CMD_TIMEOUT_MS 100
+
+/** Maximum time to wait for command PEG to initialise
+ *
+ * BUGxxxx
+ *
+ * The command PEG will currently report initialisation complete only
+ * when at least one PHY has detected a link (so that the global PHY
+ * clock can be set to 10G/1G as appropriate). This can take a very,
+ * very long time.
+ *
+ * A future firmware revision should decouple PHY initialisation from
+ * firmware initialisation, at which point the command PEG will report
+ * initialisation complete much earlier, and this timeout can be
+ * reduced.
+ */
+#define PHN_CMDPEG_INIT_TIMEOUT_SEC 50
+
+/** Maximum time to wait for receive PEG to initialise */
+#define PHN_RCVPEG_INIT_TIMEOUT_SEC 2
+
+/** Maximum time to wait for firmware to accept a command */
+#define PHN_ISSUE_CMD_TIMEOUT_MS 2000
+
+/** Maximum time to wait for test memory */
+#define PHN_TEST_MEM_TIMEOUT_MS 100
+
+/** Link state poll frequency
+ *
+ * The link state will be checked once in every N calls to poll().
+ */
+#define PHN_LINK_POLL_FREQUENCY 4096
+
+/** Number of RX descriptors */
+#define PHN_NUM_RDS 32
+
+/** RX maximum fill level. Must be strictly less than PHN_NUM_RDS. */
+#define PHN_RDS_MAX_FILL 16
+
+/** RX buffer size */
+#define PHN_RX_BUFSIZE ( 32 /* max LL padding added by card */ + \
+ ETH_FRAME_LEN )
+
+/** Number of RX status descriptors */
+#define PHN_NUM_SDS 32
+
+/** Number of TX descriptors */
+#define PHN_NUM_CDS 8
+
+/** A Phantom descriptor ring set */
+struct phantom_descriptor_rings {
+ /** RX descriptors */
+ struct phantom_rds rds[PHN_NUM_RDS];
+ /** RX status descriptors */
+ struct phantom_sds sds[PHN_NUM_SDS];
+ /** TX descriptors */
+ union phantom_cds cds[PHN_NUM_CDS];
+ /** TX consumer index */
+ volatile uint32_t cmd_cons;
+};
+
+/** A Phantom NIC port */
+struct phantom_nic_port {
+ /** Phantom NIC containing this port */
+ struct phantom_nic *phantom;
+ /** Port number */
+ unsigned int port;
+
+
+ /** RX context ID */
+ uint16_t rx_context_id;
+ /** RX descriptor producer CRB offset */
+ unsigned long rds_producer_crb;
+ /** RX status descriptor consumer CRB offset */
+ unsigned long sds_consumer_crb;
+
+ /** RX producer index */
+ unsigned int rds_producer_idx;
+ /** RX consumer index */
+ unsigned int rds_consumer_idx;
+ /** RX status consumer index */
+ unsigned int sds_consumer_idx;
+ /** RX I/O buffers */
+ struct io_buffer *rds_iobuf[PHN_RDS_MAX_FILL];
+
+
+ /** TX context ID */
+ uint16_t tx_context_id;
+ /** TX descriptor producer CRB offset */
+ unsigned long cds_producer_crb;
+
+ /** TX producer index */
+ unsigned int cds_producer_idx;
+ /** TX consumer index */
+ unsigned int cds_consumer_idx;
+ /** TX I/O buffers */
+ struct io_buffer *cds_iobuf[PHN_NUM_CDS];
+
+
+ /** Link state poll timer */
+ unsigned long link_poll_timer;
+
+
+ /** Descriptor rings */
+ struct phantom_descriptor_rings *desc;
+};
+
+/** RX context creation request and response buffers */
+struct phantom_create_rx_ctx_rqrsp {
+ struct {
+ struct nx_hostrq_rx_ctx_s rx_ctx;
+ struct nx_hostrq_rds_ring_s rds;
+ struct nx_hostrq_sds_ring_s sds;
+ } __unm_dma_aligned hostrq;
+ struct {
+ struct nx_cardrsp_rx_ctx_s rx_ctx;
+ struct nx_cardrsp_rds_ring_s rds;
+ struct nx_cardrsp_sds_ring_s sds;
+ } __unm_dma_aligned cardrsp;
+};
+
+/** TX context creation request and response buffers */
+struct phantom_create_tx_ctx_rqrsp {
+ struct {
+ struct nx_hostrq_tx_ctx_s tx_ctx;
+ } __unm_dma_aligned hostrq;
+ struct {
+ struct nx_cardrsp_tx_ctx_s tx_ctx;
+ } __unm_dma_aligned cardrsp;
+};
+
+/** A Phantom DMA buffer area */
+union phantom_dma_buffer {
+ /** Dummy area required for (read-only) self-tests */
+ uint8_t dummy_dma[UNM_DUMMY_DMA_SIZE];
+ /** RX context creation request and response buffers */
+ struct phantom_create_rx_ctx_rqrsp create_rx_ctx;
+ /** TX context creation request and response buffers */
+ struct phantom_create_tx_ctx_rqrsp create_tx_ctx;
+};
+
+/** A Phantom NIC */
+struct phantom_nic {
+ /** BAR 0 */
+ void *bar0;
+ /** Current CRB window */
+ unsigned long crb_window;
+ /** CRB window access method */
+ unsigned long ( *crb_access ) ( struct phantom_nic *phantom,
+ unsigned long reg );
+
+ /** Number of ports */
+ int num_ports;
+ /** Per-port network devices */
+ struct net_device *netdev[UNM_FLASH_NUM_PORTS];
+
+ /** DMA buffers */
+ union phantom_dma_buffer *dma_buf;
+
+ /** Flash memory SPI bus */
+ struct spi_bus spi_bus;
+ /** Flash memory SPI device */
+ struct spi_device flash;
+
+ /** Last known link state */
+ uint32_t link_state;
+};
+
+/***************************************************************************
+ *
+ * CRB register access
+ *
+ */
+
+/**
+ * Prepare for access to CRB register via 128MB BAR
+ *
+ * @v phantom Phantom NIC
+ * @v reg Register offset within abstract address space
+ * @ret offset Register offset within PCI BAR0
+ */
+static unsigned long phantom_crb_access_128m ( struct phantom_nic *phantom,
+ unsigned long reg ) {
+ static const uint32_t reg_window[] = {
+ [UNM_CRB_BLK_PCIE] = 0x0000000,
+ [UNM_CRB_BLK_CAM] = 0x2000000,
+ [UNM_CRB_BLK_ROMUSB] = 0x2000000,
+ [UNM_CRB_BLK_TEST] = 0x0000000,
+ };
+ static const uint32_t reg_bases[] = {
+ [UNM_CRB_BLK_PCIE] = 0x6100000,
+ [UNM_CRB_BLK_CAM] = 0x6200000,
+ [UNM_CRB_BLK_ROMUSB] = 0x7300000,
+ [UNM_CRB_BLK_TEST] = 0x6200000,
+ };
+ unsigned int block = UNM_CRB_BLK ( reg );
+ unsigned long offset = UNM_CRB_OFFSET ( reg );
+ uint32_t window = reg_window[block];
+ uint32_t verify_window;
+
+ if ( phantom->crb_window != window ) {
+
+ /* Write to the CRB window register */
+ writel ( window, phantom->bar0 + UNM_128M_CRB_WINDOW );
+
+ /* Ensure that the write has reached the card */
+ verify_window = readl ( phantom->bar0 + UNM_128M_CRB_WINDOW );
+ assert ( verify_window == window );
+
+ /* Record new window */
+ phantom->crb_window = window;
+ }
+
+ return ( reg_bases[block] + offset );
+}
+
+/**
+ * Prepare for access to CRB register via 32MB BAR
+ *
+ * @v phantom Phantom NIC
+ * @v reg Register offset within abstract address space
+ * @ret offset Register offset within PCI BAR0
+ */
+static unsigned long phantom_crb_access_32m ( struct phantom_nic *phantom,
+ unsigned long reg ) {
+ static const uint32_t reg_window[] = {
+ [UNM_CRB_BLK_PCIE] = 0x0000000,
+ [UNM_CRB_BLK_CAM] = 0x2000000,
+ [UNM_CRB_BLK_ROMUSB] = 0x2000000,
+ [UNM_CRB_BLK_TEST] = 0x0000000,
+ };
+ static const uint32_t reg_bases[] = {
+ [UNM_CRB_BLK_PCIE] = 0x0100000,
+ [UNM_CRB_BLK_CAM] = 0x0200000,
+ [UNM_CRB_BLK_ROMUSB] = 0x1300000,
+ [UNM_CRB_BLK_TEST] = 0x0200000,
+ };
+ unsigned int block = UNM_CRB_BLK ( reg );
+ unsigned long offset = UNM_CRB_OFFSET ( reg );
+ uint32_t window = reg_window[block];
+ uint32_t verify_window;
+
+ if ( phantom->crb_window != window ) {
+
+ /* Write to the CRB window register */
+ writel ( window, phantom->bar0 + UNM_32M_CRB_WINDOW );
+
+ /* Ensure that the write has reached the card */
+ verify_window = readl ( phantom->bar0 + UNM_32M_CRB_WINDOW );
+ assert ( verify_window == window );
+
+ /* Record new window */
+ phantom->crb_window = window;
+ }
+
+ return ( reg_bases[block] + offset );
+}
+
+/**
+ * Prepare for access to CRB register via 2MB BAR
+ *
+ * @v phantom Phantom NIC
+ * @v reg Register offset within abstract address space
+ * @ret offset Register offset within PCI BAR0
+ */
+static unsigned long phantom_crb_access_2m ( struct phantom_nic *phantom,
+ unsigned long reg ) {
+ static const uint32_t reg_window_hi[] = {
+ [UNM_CRB_BLK_PCIE] = 0x77300000,
+ [UNM_CRB_BLK_CAM] = 0x41600000,
+ [UNM_CRB_BLK_ROMUSB] = 0x42100000,
+ [UNM_CRB_BLK_TEST] = 0x29500000,
+ };
+ unsigned int block = UNM_CRB_BLK ( reg );
+ unsigned long offset = UNM_CRB_OFFSET ( reg );
+ uint32_t window = ( reg_window_hi[block] | ( offset & 0x000f0000 ) );
+ uint32_t verify_window;
+
+ if ( phantom->crb_window != window ) {
+
+ /* Write to the CRB window register */
+ writel ( window, phantom->bar0 + UNM_2M_CRB_WINDOW );
+
+ /* Ensure that the write has reached the card */
+ verify_window = readl ( phantom->bar0 + UNM_2M_CRB_WINDOW );
+ assert ( verify_window == window );
+
+ /* Record new window */
+ phantom->crb_window = window;
+ }
+
+ return ( 0x1e0000 + ( offset & 0xffff ) );
+}
+
+/**
+ * Read from Phantom CRB register
+ *
+ * @v phantom Phantom NIC
+ * @v reg Register offset within abstract address space
+ * @ret value Register value
+ */
+static uint32_t phantom_readl ( struct phantom_nic *phantom,
+ unsigned long reg ) {
+ unsigned long offset;
+
+ offset = phantom->crb_access ( phantom, reg );
+ return readl ( phantom->bar0 + offset );
+}
+
+/**
+ * Write to Phantom CRB register
+ *
+ * @v phantom Phantom NIC
+ * @v value Register value
+ * @v reg Register offset within abstract address space
+ */
+static void phantom_writel ( struct phantom_nic *phantom, uint32_t value,
+ unsigned long reg ) {
+ unsigned long offset;
+
+ offset = phantom->crb_access ( phantom, reg );
+ writel ( value, phantom->bar0 + offset );
+}
+
+/**
+ * Write to Phantom CRB HI/LO register pair
+ *
+ * @v phantom Phantom NIC
+ * @v value Register value
+ * @v lo_offset LO register offset within CRB
+ * @v hi_offset HI register offset within CRB
+ */
+static inline void phantom_write_hilo ( struct phantom_nic *phantom,
+ uint64_t value,
+ unsigned long lo_offset,
+ unsigned long hi_offset ) {
+ uint32_t lo = ( value & 0xffffffffUL );
+ uint32_t hi = ( value >> 32 );
+
+ phantom_writel ( phantom, lo, lo_offset );
+ phantom_writel ( phantom, hi, hi_offset );
+}
+
+/***************************************************************************
+ *
+ * Firmware message buffer access (for debug)
+ *
+ */
+
+/**
+ * Read from Phantom test memory
+ *
+ * @v phantom Phantom NIC
+ * @v offset Offset within test memory
+ * @v buf 8-byte buffer to fill
+ * @ret rc Return status code
+ */
+static int phantom_read_test_mem ( struct phantom_nic *phantom,
+ uint64_t offset, uint32_t buf[2] ) {
+ unsigned int retries;
+ uint32_t test_control;
+
+ phantom_write_hilo ( phantom, offset, UNM_TEST_ADDR_LO,
+ UNM_TEST_ADDR_HI );
+ phantom_writel ( phantom, UNM_TEST_CONTROL_ENABLE, UNM_TEST_CONTROL );
+ phantom_writel ( phantom,
+ ( UNM_TEST_CONTROL_ENABLE | UNM_TEST_CONTROL_START ),
+ UNM_TEST_CONTROL );
+
+ for ( retries = 0 ; retries < PHN_TEST_MEM_TIMEOUT_MS ; retries++ ) {
+ test_control = phantom_readl ( phantom, UNM_TEST_CONTROL );
+ if ( ( test_control & UNM_TEST_CONTROL_BUSY ) == 0 ) {
+ buf[0] = phantom_readl ( phantom, UNM_TEST_RDDATA_LO );
+ buf[1] = phantom_readl ( phantom, UNM_TEST_RDDATA_HI );
+ return 0;
+ }
+ mdelay ( 1 );
+ }
+
+ DBGC ( phantom, "Phantom %p timed out waiting for test memory\n",
+ phantom );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Dump Phantom firmware dmesg log
+ *
+ * @v phantom Phantom NIC
+ * @v log Log number
+ */
+static void phantom_dmesg ( struct phantom_nic *phantom, unsigned int log ) {
+ uint32_t head;
+ uint32_t tail;
+ uint32_t len;
+ uint32_t sig;
+ uint32_t offset;
+ union {
+ uint8_t bytes[8];
+ uint32_t dwords[2];
+ } buf;
+ unsigned int i;
+ int rc;
+
+ /* Optimise out for non-debug builds */
+ if ( ! DBG_LOG )
+ return;
+
+ head = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_HEAD ( log ) );
+ len = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_LEN ( log ) );
+ tail = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_TAIL ( log ) );
+ sig = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_SIG ( log ) );
+ DBGC ( phantom, "Phantom %p firmware dmesg buffer %d (%08lx-%08lx)\n",
+ phantom, log, head, tail );
+ assert ( ( head & 0x07 ) == 0 );
+ if ( sig != UNM_CAM_RAM_DMESG_SIG_MAGIC ) {
+ DBGC ( phantom, "Warning: bad signature %08lx (want %08lx)\n",
+ sig, UNM_CAM_RAM_DMESG_SIG_MAGIC );
+ }
+
+ for ( offset = head ; offset < tail ; offset += 8 ) {
+ if ( ( rc = phantom_read_test_mem ( phantom, offset,
+ buf.dwords ) ) != 0 ) {
+ DBGC ( phantom, "Phantom %p could not read from test "
+ "memory: %s\n", phantom, strerror ( rc ) );
+ break;
+ }
+ for ( i = 0 ; ( ( i < sizeof ( buf ) ) &&
+ ( offset + i ) < tail ) ; i++ ) {
+ DBG ( "%c", buf.bytes[i] );
+ }
+ }
+ DBG ( "\n" );
+}
+
+/**
+ * Dump Phantom firmware dmesg logs
+ *
+ * @v phantom Phantom NIC
+ */
+static void __attribute__ (( unused ))
+phantom_dmesg_all ( struct phantom_nic *phantom ) {
+ unsigned int i;
+
+ for ( i = 0 ; i < UNM_CAM_RAM_NUM_DMESG_BUFFERS ; i++ )
+ phantom_dmesg ( phantom, i );
+}
+
+/***************************************************************************
+ *
+ * SPI bus access (for flash memory)
+ *
+ */
+
+/**
+ * Acquire Phantom SPI lock
+ *
+ * @v phantom Phantom NIC
+ * @ret rc Return status code
+ */
+static int phantom_spi_lock ( struct phantom_nic *phantom ) {
+ unsigned int retries;
+ uint32_t pcie_sem2_lock;
+
+ for ( retries = 0 ; retries < PHN_SPI_LOCK_TIMEOUT_MS ; retries++ ) {
+ pcie_sem2_lock = phantom_readl ( phantom, UNM_PCIE_SEM2_LOCK );
+ if ( pcie_sem2_lock != 0 )
+ return 0;
+ mdelay ( 1 );
+ }
+
+ DBGC ( phantom, "Phantom %p timed out waiting for SPI lock\n",
+ phantom );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Wait for Phantom SPI command to complete
+ *
+ * @v phantom Phantom NIC
+ * @ret rc Return status code
+ */
+static int phantom_spi_wait ( struct phantom_nic *phantom ) {
+ unsigned int retries;
+ uint32_t glb_status;
+
+ for ( retries = 0 ; retries < PHN_SPI_CMD_TIMEOUT_MS ; retries++ ) {
+ glb_status = phantom_readl ( phantom, UNM_ROMUSB_GLB_STATUS );
+ if ( glb_status & UNM_ROMUSB_GLB_STATUS_ROM_DONE )
+ return 0;
+ mdelay ( 1 );
+ }
+
+ DBGC ( phantom, "Phantom %p timed out waiting for SPI command\n",
+ phantom );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Release Phantom SPI lock
+ *
+ * @v phantom Phantom NIC
+ */
+static void phantom_spi_unlock ( struct phantom_nic *phantom ) {
+ phantom_readl ( phantom, UNM_PCIE_SEM2_UNLOCK );
+}
+
+/**
+ * Read/write data via Phantom SPI bus
+ *
+ * @v bus SPI bus
+ * @v device SPI device
+ * @v command Command
+ * @v address Address to read/write (<0 for no address)
+ * @v data_out TX data buffer (or NULL)
+ * @v data_in RX data buffer (or NULL)
+ * @v len Length of data buffer(s)
+ * @ret rc Return status code
+ */
+static int phantom_spi_rw ( struct spi_bus *bus,
+ struct spi_device *device,
+ unsigned int command, int address,
+ const void *data_out, void *data_in,
+ size_t len ) {
+ struct phantom_nic *phantom =
+ container_of ( bus, struct phantom_nic, spi_bus );
+ uint32_t data;
+ int rc;
+
+ DBGCP ( phantom, "Phantom %p SPI command %x at %x+%zx\n",
+ phantom, command, address, len );
+ if ( data_out )
+ DBGCP_HDA ( phantom, address, data_out, len );
+
+ /* We support only exactly 4-byte reads */
+ if ( len != UNM_SPI_BLKSIZE ) {
+ DBGC ( phantom, "Phantom %p invalid SPI length %zx\n",
+ phantom, len );
+ return -EINVAL;
+ }
+
+ /* Acquire SPI lock */
+ if ( ( rc = phantom_spi_lock ( phantom ) ) != 0 )
+ goto err_lock;
+
+ /* Issue SPI command as per the PRM */
+ if ( data_out ) {
+ memcpy ( &data, data_out, sizeof ( data ) );
+ phantom_writel ( phantom, data, UNM_ROMUSB_ROM_WDATA );
+ }
+ phantom_writel ( phantom, address, UNM_ROMUSB_ROM_ADDRESS );
+ phantom_writel ( phantom, ( device->address_len / 8 ),
+ UNM_ROMUSB_ROM_ABYTE_CNT );
+ udelay ( 100 ); /* according to PRM */
+ phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT );
+ phantom_writel ( phantom, command, UNM_ROMUSB_ROM_INSTR_OPCODE );
+
+ /* Wait for SPI command to complete */
+ if ( ( rc = phantom_spi_wait ( phantom ) ) != 0 )
+ goto err_wait;
+
+ /* Reset address byte count and dummy byte count, because the
+ * PRM asks us to.
+ */
+ phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_ABYTE_CNT );
+ udelay ( 100 ); /* according to PRM */
+ phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT );
+
+ /* Read data, if applicable */
+ if ( data_in ) {
+ data = phantom_readl ( phantom, UNM_ROMUSB_ROM_RDATA );
+ memcpy ( data_in, &data, sizeof ( data ) );
+ DBGCP_HDA ( phantom, address, data_in, len );
+ }
+
+ err_wait:
+ phantom_spi_unlock ( phantom );
+ err_lock:
+ return rc;
+}
+
+/***************************************************************************
+ *
+ * Firmware interface
+ *
+ */
+
+/**
+ * Wait for firmware to accept command
+ *
+ * @v phantom Phantom NIC
+ * @ret rc Return status code
+ */
+static int phantom_wait_for_cmd ( struct phantom_nic *phantom ) {
+ unsigned int retries;
+ uint32_t cdrp;
+
+ for ( retries = 0 ; retries < PHN_ISSUE_CMD_TIMEOUT_MS ; retries++ ) {
+ mdelay ( 1 );
+ cdrp = phantom_readl ( phantom, UNM_NIC_REG_NX_CDRP );
+ if ( NX_CDRP_IS_RSP ( cdrp ) ) {
+ switch ( NX_CDRP_FORM_RSP ( cdrp ) ) {
+ case NX_CDRP_RSP_OK:
+ return 0;
+ case NX_CDRP_RSP_FAIL:
+ return -EIO;
+ case NX_CDRP_RSP_TIMEOUT:
+ return -ETIMEDOUT;
+ default:
+ return -EPROTO;
+ }
+ }
+ }
+
+ DBGC ( phantom, "Phantom %p timed out waiting for firmware to accept "
+ "command\n", phantom );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Issue command to firmware
+ *
+ * @v phantom_port Phantom NIC port
+ * @v command Firmware command
+ * @v arg1 Argument 1
+ * @v arg2 Argument 2
+ * @v arg3 Argument 3
+ * @ret rc Return status code
+ */
+static int phantom_issue_cmd ( struct phantom_nic_port *phantom_port,
+ uint32_t command, uint32_t arg1, uint32_t arg2,
+ uint32_t arg3 ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ uint32_t signature;
+ int rc;
+
+ /* Issue command */
+ signature = NX_CDRP_SIGNATURE_MAKE ( phantom_port->port,
+ NXHAL_VERSION );
+ DBGC2 ( phantom, "Phantom %p port %d issuing command %08lx (%08lx, "
+ "%08lx, %08lx)\n", phantom, phantom_port->port,
+ command, arg1, arg2, arg3 );
+ phantom_writel ( phantom, signature, UNM_NIC_REG_NX_SIGN );
+ phantom_writel ( phantom, arg1, UNM_NIC_REG_NX_ARG1 );
+ phantom_writel ( phantom, arg2, UNM_NIC_REG_NX_ARG2 );
+ phantom_writel ( phantom, arg3, UNM_NIC_REG_NX_ARG3 );
+ phantom_writel ( phantom, NX_CDRP_FORM_CMD ( command ),
+ UNM_NIC_REG_NX_CDRP );
+
+ /* Wait for command to be accepted */
+ if ( ( rc = phantom_wait_for_cmd ( phantom ) ) != 0 ) {
+ DBGC ( phantom, "Phantom %p could not issue command: %s\n",
+ phantom, strerror ( rc ) );
+ return rc;
+ }
+
+ return 0;
+}
+
+/**
+ * Issue buffer-format command to firmware
+ *
+ * @v phantom_port Phantom NIC port
+ * @v command Firmware command
+ * @v buffer Buffer to pass to firmware
+ * @v len Length of buffer
+ * @ret rc Return status code
+ */
+static int phantom_issue_buf_cmd ( struct phantom_nic_port *phantom_port,
+ uint32_t command, void *buffer,
+ size_t len ) {
+ uint64_t physaddr;
+
+ physaddr = virt_to_bus ( buffer );
+ return phantom_issue_cmd ( phantom_port, command, ( physaddr >> 32 ),
+ ( physaddr & 0xffffffffUL ), len );
+}
+
+/**
+ * Create Phantom RX context
+ *
+ * @v phantom_port Phantom NIC port
+ * @ret rc Return status code
+ */
+static int phantom_create_rx_ctx ( struct phantom_nic_port *phantom_port ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ struct phantom_create_rx_ctx_rqrsp *buf;
+ int rc;
+
+ /* Prepare request */
+ buf = &phantom->dma_buf->create_rx_ctx;
+ memset ( buf, 0, sizeof ( *buf ) );
+ buf->hostrq.rx_ctx.host_rsp_dma_addr =
+ cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
+ buf->hostrq.rx_ctx.capabilities[0] =
+ cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
+ buf->hostrq.rx_ctx.host_int_crb_mode =
+ cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
+ buf->hostrq.rx_ctx.host_rds_crb_mode =
+ cpu_to_le32 ( NX_HOST_RDS_CRB_MODE_UNIQUE );
+ buf->hostrq.rx_ctx.rds_ring_offset = cpu_to_le32 ( 0 );
+ buf->hostrq.rx_ctx.sds_ring_offset =
+ cpu_to_le32 ( sizeof ( buf->hostrq.rds ) );
+ buf->hostrq.rx_ctx.num_rds_rings = cpu_to_le16 ( 1 );
+ buf->hostrq.rx_ctx.num_sds_rings = cpu_to_le16 ( 1 );
+ buf->hostrq.rds.host_phys_addr =
+ cpu_to_le64 ( virt_to_bus ( phantom_port->desc->rds ) );
+ buf->hostrq.rds.buff_size = cpu_to_le64 ( PHN_RX_BUFSIZE );
+ buf->hostrq.rds.ring_size = cpu_to_le32 ( PHN_NUM_RDS );
+ buf->hostrq.rds.ring_kind = cpu_to_le32 ( NX_RDS_RING_TYPE_NORMAL );
+ buf->hostrq.sds.host_phys_addr =
+ cpu_to_le64 ( virt_to_bus ( phantom_port->desc->sds ) );
+ buf->hostrq.sds.ring_size = cpu_to_le32 ( PHN_NUM_SDS );
+
+ DBGC ( phantom, "Phantom %p port %d creating RX context\n",
+ phantom, phantom_port->port );
+ DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
+ &buf->hostrq, sizeof ( buf->hostrq ) );
+
+ /* Issue request */
+ if ( ( rc = phantom_issue_buf_cmd ( phantom_port,
+ NX_CDRP_CMD_CREATE_RX_CTX,
+ &buf->hostrq,
+ sizeof ( buf->hostrq ) ) ) != 0 ) {
+ DBGC ( phantom, "Phantom %p port %d could not create RX "
+ "context: %s\n",
+ phantom, phantom_port->port, strerror ( rc ) );
+ DBGC ( phantom, "Request:\n" );
+ DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
+ &buf->hostrq, sizeof ( buf->hostrq ) );
+ DBGC ( phantom, "Response:\n" );
+ DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
+ &buf->cardrsp, sizeof ( buf->cardrsp ) );
+ return rc;
+ }
+
+ /* Retrieve context parameters */
+ phantom_port->rx_context_id =
+ le16_to_cpu ( buf->cardrsp.rx_ctx.context_id );
+ phantom_port->rds_producer_crb =
+ ( UNM_CAM_RAM +
+ le32_to_cpu ( buf->cardrsp.rds.host_producer_crb ));
+ phantom_port->sds_consumer_crb =
+ ( UNM_CAM_RAM +
+ le32_to_cpu ( buf->cardrsp.sds.host_consumer_crb ));
+
+ DBGC ( phantom, "Phantom %p port %d created RX context (id %04x, "
+ "port phys %02x virt %02x)\n", phantom, phantom_port->port,
+ phantom_port->rx_context_id, buf->cardrsp.rx_ctx.phys_port,
+ buf->cardrsp.rx_ctx.virt_port );
+ DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
+ &buf->cardrsp, sizeof ( buf->cardrsp ) );
+ DBGC ( phantom, "Phantom %p port %d RDS producer CRB is %08lx\n",
+ phantom, phantom_port->port, phantom_port->rds_producer_crb );
+ DBGC ( phantom, "Phantom %p port %d SDS consumer CRB is %08lx\n",
+ phantom, phantom_port->port, phantom_port->sds_consumer_crb );
+
+ return 0;
+}
+
+/**
+ * Destroy Phantom RX context
+ *
+ * @v phantom_port Phantom NIC port
+ * @ret rc Return status code
+ */
+static void phantom_destroy_rx_ctx ( struct phantom_nic_port *phantom_port ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ int rc;
+
+ DBGC ( phantom, "Phantom %p port %d destroying RX context (id %04x)\n",
+ phantom, phantom_port->port, phantom_port->rx_context_id );
+
+ /* Issue request */
+ if ( ( rc = phantom_issue_cmd ( phantom_port,
+ NX_CDRP_CMD_DESTROY_RX_CTX,
+ phantom_port->rx_context_id,
+ NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
+ DBGC ( phantom, "Phantom %p port %d could not destroy RX "
+ "context: %s\n",
+ phantom, phantom_port->port, strerror ( rc ) );
+ /* We're probably screwed */
+ return;
+ }
+
+ /* Clear context parameters */
+ phantom_port->rx_context_id = 0;
+ phantom_port->rds_producer_crb = 0;
+ phantom_port->sds_consumer_crb = 0;
+
+ /* Reset software counters */
+ phantom_port->rds_producer_idx = 0;
+ phantom_port->rds_consumer_idx = 0;
+ phantom_port->sds_consumer_idx = 0;
+}
+
+/**
+ * Create Phantom TX context
+ *
+ * @v phantom_port Phantom NIC port
+ * @ret rc Return status code
+ */
+static int phantom_create_tx_ctx ( struct phantom_nic_port *phantom_port ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ struct phantom_create_tx_ctx_rqrsp *buf;
+ int rc;
+
+ /* Prepare request */
+ buf = &phantom->dma_buf->create_tx_ctx;
+ memset ( buf, 0, sizeof ( *buf ) );
+ buf->hostrq.tx_ctx.host_rsp_dma_addr =
+ cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
+ buf->hostrq.tx_ctx.cmd_cons_dma_addr =
+ cpu_to_le64 ( virt_to_bus ( &phantom_port->desc->cmd_cons ) );
+ buf->hostrq.tx_ctx.dummy_dma_addr =
+ cpu_to_le64 ( virt_to_bus ( phantom->dma_buf->dummy_dma ) );
+ buf->hostrq.tx_ctx.capabilities[0] =
+ cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
+ buf->hostrq.tx_ctx.host_int_crb_mode =
+ cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
+ buf->hostrq.tx_ctx.cds_ring.host_phys_addr =
+ cpu_to_le64 ( virt_to_bus ( phantom_port->desc->cds ) );
+ buf->hostrq.tx_ctx.cds_ring.ring_size = cpu_to_le32 ( PHN_NUM_CDS );
+
+ DBGC ( phantom, "Phantom %p port %d creating TX context\n",
+ phantom, phantom_port->port );
+ DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
+ &buf->hostrq, sizeof ( buf->hostrq ) );
+
+ /* Issue request */
+ if ( ( rc = phantom_issue_buf_cmd ( phantom_port,
+ NX_CDRP_CMD_CREATE_TX_CTX,
+ &buf->hostrq,
+ sizeof ( buf->hostrq ) ) ) != 0 ) {
+ DBGC ( phantom, "Phantom %p port %d could not create TX "
+ "context: %s\n",
+ phantom, phantom_port->port, strerror ( rc ) );
+ DBGC ( phantom, "Request:\n" );
+ DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
+ &buf->hostrq, sizeof ( buf->hostrq ) );
+ DBGC ( phantom, "Response:\n" );
+ DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
+ &buf->cardrsp, sizeof ( buf->cardrsp ) );
+ return rc;
+ }
+
+ /* Retrieve context parameters */
+ phantom_port->tx_context_id =
+ le16_to_cpu ( buf->cardrsp.tx_ctx.context_id );
+ phantom_port->cds_producer_crb =
+ ( UNM_CAM_RAM +
+ le32_to_cpu(buf->cardrsp.tx_ctx.cds_ring.host_producer_crb));
+
+ DBGC ( phantom, "Phantom %p port %d created TX context (id %04x, "
+ "port phys %02x virt %02x)\n", phantom, phantom_port->port,
+ phantom_port->tx_context_id, buf->cardrsp.tx_ctx.phys_port,
+ buf->cardrsp.tx_ctx.virt_port );
+ DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
+ &buf->cardrsp, sizeof ( buf->cardrsp ) );
+ DBGC ( phantom, "Phantom %p port %d CDS producer CRB is %08lx\n",
+ phantom, phantom_port->port, phantom_port->cds_producer_crb );
+
+ return 0;
+}
+
+/**
+ * Destroy Phantom TX context
+ *
+ * @v phantom_port Phantom NIC port
+ * @ret rc Return status code
+ */
+static void phantom_destroy_tx_ctx ( struct phantom_nic_port *phantom_port ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ int rc;
+
+ DBGC ( phantom, "Phantom %p port %d destroying TX context (id %04x)\n",
+ phantom, phantom_port->port, phantom_port->tx_context_id );
+
+ /* Issue request */
+ if ( ( rc = phantom_issue_cmd ( phantom_port,
+ NX_CDRP_CMD_DESTROY_TX_CTX,
+ phantom_port->tx_context_id,
+ NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
+ DBGC ( phantom, "Phantom %p port %d could not destroy TX "
+ "context: %s\n",
+ phantom, phantom_port->port, strerror ( rc ) );
+ /* We're probably screwed */
+ return;
+ }
+
+ /* Clear context parameters */
+ phantom_port->tx_context_id = 0;
+ phantom_port->cds_producer_crb = 0;
+
+ /* Reset software counters */
+ phantom_port->cds_producer_idx = 0;
+ phantom_port->cds_consumer_idx = 0;
+}
+
+/***************************************************************************
+ *
+ * Descriptor ring management
+ *
+ */
+
+/**
+ * Allocate Phantom RX descriptor
+ *
+ * @v phantom_port Phantom NIC port
+ * @ret index RX descriptor index, or negative error
+ */
+static int phantom_alloc_rds ( struct phantom_nic_port *phantom_port ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ unsigned int rds_producer_idx;
+ unsigned int next_rds_producer_idx;
+
+ /* Check for space in the ring. RX descriptors are consumed
+ * out of order, but they are *read* by the hardware in strict
+ * order. We maintain a pessimistic consumer index, which is
+ * guaranteed never to be an overestimate of the number of
+ * descriptors read by the hardware.
+ */
+ rds_producer_idx = phantom_port->rds_producer_idx;
+ next_rds_producer_idx = ( ( rds_producer_idx + 1 ) % PHN_NUM_RDS );
+ if ( next_rds_producer_idx == phantom_port->rds_consumer_idx ) {
+ DBGC ( phantom, "Phantom %p port %d RDS ring full (index %d "
+ "not consumed)\n", phantom, phantom_port->port,
+ next_rds_producer_idx );
+ return -ENOBUFS;
+ }
+
+ return rds_producer_idx;
+}
+
+/**
+ * Post Phantom RX descriptor
+ *
+ * @v phantom_port Phantom NIC port
+ * @v rds RX descriptor
+ */
+static void phantom_post_rds ( struct phantom_nic_port *phantom_port,
+ struct phantom_rds *rds ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ unsigned int rds_producer_idx;
+ unsigned int next_rds_producer_idx;
+ struct phantom_rds *entry;
+
+ /* Copy descriptor to ring */
+ rds_producer_idx = phantom_port->rds_producer_idx;
+ entry = &phantom_port->desc->rds[rds_producer_idx];
+ memcpy ( entry, rds, sizeof ( *entry ) );
+ DBGC2 ( phantom, "Phantom %p port %d posting RDS %ld (slot %d):\n",
+ phantom, phantom_port->port, NX_GET ( rds, handle ),
+ rds_producer_idx );
+ DBGC2_HDA ( phantom, virt_to_bus ( entry ), entry, sizeof ( *entry ) );
+
+ /* Update producer index */
+ next_rds_producer_idx = ( ( rds_producer_idx + 1 ) % PHN_NUM_RDS );
+ phantom_port->rds_producer_idx = next_rds_producer_idx;
+ wmb();
+ phantom_writel ( phantom, phantom_port->rds_producer_idx,
+ phantom_port->rds_producer_crb );
+}
+
+/**
+ * Allocate Phantom TX descriptor
+ *
+ * @v phantom_port Phantom NIC port
+ * @ret index TX descriptor index, or negative error
+ */
+static int phantom_alloc_cds ( struct phantom_nic_port *phantom_port ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ unsigned int cds_producer_idx;
+ unsigned int next_cds_producer_idx;
+
+ /* Check for space in the ring. TX descriptors are consumed
+ * in strict order, so we just check for a collision against
+ * the consumer index.
+ */
+ cds_producer_idx = phantom_port->cds_producer_idx;
+ next_cds_producer_idx = ( ( cds_producer_idx + 1 ) % PHN_NUM_CDS );
+ if ( next_cds_producer_idx == phantom_port->cds_consumer_idx ) {
+ DBGC ( phantom, "Phantom %p port %d CDS ring full (index %d "
+ "not consumed)\n", phantom, phantom_port->port,
+ next_cds_producer_idx );
+ return -ENOBUFS;
+ }
+
+ return cds_producer_idx;
+}
+
+/**
+ * Post Phantom TX descriptor
+ *
+ * @v phantom_port Phantom NIC port
+ * @v cds TX descriptor
+ */
+static void phantom_post_cds ( struct phantom_nic_port *phantom_port,
+ union phantom_cds *cds ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ unsigned int cds_producer_idx;
+ unsigned int next_cds_producer_idx;
+ union phantom_cds *entry;
+
+ /* Copy descriptor to ring */
+ cds_producer_idx = phantom_port->cds_producer_idx;
+ entry = &phantom_port->desc->cds[cds_producer_idx];
+ memcpy ( entry, cds, sizeof ( *entry ) );
+ DBGC2 ( phantom, "Phantom %p port %d posting CDS %d:\n",
+ phantom, phantom_port->port, cds_producer_idx );
+ DBGC2_HDA ( phantom, virt_to_bus ( entry ), entry, sizeof ( *entry ) );
+
+ /* Update producer index */
+ next_cds_producer_idx = ( ( cds_producer_idx + 1 ) % PHN_NUM_CDS );
+ phantom_port->cds_producer_idx = next_cds_producer_idx;
+ wmb();
+ phantom_writel ( phantom, phantom_port->cds_producer_idx,
+ phantom_port->cds_producer_crb );
+}
+
+/***************************************************************************
+ *
+ * MAC address management
+ *
+ */
+
+/**
+ * Add/remove MAC address
+ *
+ * @v phantom_port Phantom NIC port
+ * @v ll_addr MAC address to add or remove
+ * @v opcode MAC request opcode
+ * @ret rc Return status code
+ */
+static int phantom_update_macaddr ( struct phantom_nic_port *phantom_port,
+ const uint8_t *ll_addr,
+ unsigned int opcode ) {
+ union phantom_cds cds;
+ int index;
+
+ /* Get descriptor ring entry */
+ index = phantom_alloc_cds ( phantom_port );
+ if ( index < 0 )
+ return index;
+
+ /* Fill descriptor ring entry */
+ memset ( &cds, 0, sizeof ( cds ) );
+ NX_FILL_1 ( &cds, 0,
+ nic_request.common.opcode, UNM_NIC_REQUEST );
+ NX_FILL_2 ( &cds, 1,
+ nic_request.header.opcode, UNM_MAC_EVENT,
+ nic_request.header.context_id, phantom_port->port );
+ NX_FILL_7 ( &cds, 2,
+ nic_request.body.mac_request.opcode, opcode,
+ nic_request.body.mac_request.mac_addr_0, ll_addr[0],
+ nic_request.body.mac_request.mac_addr_1, ll_addr[1],
+ nic_request.body.mac_request.mac_addr_2, ll_addr[2],
+ nic_request.body.mac_request.mac_addr_3, ll_addr[3],
+ nic_request.body.mac_request.mac_addr_4, ll_addr[4],
+ nic_request.body.mac_request.mac_addr_5, ll_addr[5] );
+
+ /* Post descriptor */
+ phantom_post_cds ( phantom_port, &cds );
+
+ return 0;
+}
+
+/**
+ * Add MAC address
+ *
+ * @v phantom_port Phantom NIC port
+ * @v ll_addr MAC address to add or remove
+ * @ret rc Return status code
+ */
+static inline int phantom_add_macaddr ( struct phantom_nic_port *phantom_port,
+ const uint8_t *ll_addr ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+
+ DBGC ( phantom, "Phantom %p port %d adding MAC address %s\n",
+ phantom, phantom_port->port, eth_ntoa ( ll_addr ) );
+
+ return phantom_update_macaddr ( phantom_port, ll_addr, UNM_MAC_ADD );
+}
+
+/**
+ * Remove MAC address
+ *
+ * @v phantom_port Phantom NIC port
+ * @v ll_addr MAC address to add or remove
+ * @ret rc Return status code
+ */
+static inline int phantom_del_macaddr ( struct phantom_nic_port *phantom_port,
+ const uint8_t *ll_addr ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+
+ DBGC ( phantom, "Phantom %p port %d removing MAC address %s\n",
+ phantom, phantom_port->port, eth_ntoa ( ll_addr ) );
+
+ return phantom_update_macaddr ( phantom_port, ll_addr, UNM_MAC_DEL );
+}
+
+/***************************************************************************
+ *
+ * Link state detection
+ *
+ */
+
+/**
+ * Poll link state
+ *
+ * @v phantom Phantom NIC
+ */
+static void phantom_poll_link_state ( struct phantom_nic *phantom ) {
+ struct net_device *netdev;
+ struct phantom_nic_port *phantom_port;
+ uint32_t xg_state_p3;
+ unsigned int link;
+ int i;
+
+ /* Read link state */
+ xg_state_p3 = phantom_readl ( phantom, UNM_NIC_REG_XG_STATE_P3 );
+
+ /* If there is no change, do nothing */
+ if ( phantom->link_state == xg_state_p3 )
+ return;
+
+ /* Record new link state */
+ DBGC ( phantom, "Phantom %p new link state %08lx (was %08lx)\n",
+ phantom, xg_state_p3, phantom->link_state );
+ phantom->link_state = xg_state_p3;
+
+ /* Indicate per-port link state to gPXE */
+ for ( i = 0 ; i < phantom->num_ports ; i++ ) {
+ netdev = phantom->netdev[i];
+ phantom_port = netdev_priv ( netdev );
+ link = UNM_NIC_REG_XG_STATE_P3_LINK ( phantom_port->port,
+ phantom->link_state );
+ switch ( link ) {
+ case UNM_NIC_REG_XG_STATE_P3_LINK_UP:
+ DBGC ( phantom, "Phantom %p port %d link is up\n",
+ phantom, phantom_port->port );
+ netdev_link_up ( netdev );
+ break;
+ case UNM_NIC_REG_XG_STATE_P3_LINK_DOWN:
+ DBGC ( phantom, "Phantom %p port %d link is down\n",
+ phantom, phantom_port->port );
+ netdev_link_down ( netdev );
+ break;
+ default:
+ DBGC ( phantom, "Phantom %p port %d bad link state "
+ "%d\n", phantom, phantom_port->port, link );
+ break;
+ }
+ }
+}
+
+/***************************************************************************
+ *
+ * Main driver body
+ *
+ */
+
+/**
+ * Refill descriptor ring
+ *
+ * @v netdev Net device
+ */
+static void phantom_refill_rx_ring ( struct net_device *netdev ) {
+ struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
+ struct io_buffer *iobuf;
+ struct phantom_rds rds;
+ unsigned int handle;
+ int index;
+
+ for ( handle = 0 ; handle < PHN_RDS_MAX_FILL ; handle++ ) {
+
+ /* Skip this index if the descriptor has not yet been
+ * consumed.
+ */
+ if ( phantom_port->rds_iobuf[handle] != NULL )
+ continue;
+
+ /* Allocate descriptor ring entry */
+ index = phantom_alloc_rds ( phantom_port );
+ assert ( PHN_RDS_MAX_FILL < PHN_NUM_RDS );
+ assert ( index >= 0 ); /* Guaranteed by MAX_FILL < NUM_RDS ) */
+
+ /* Try to allocate an I/O buffer */
+ iobuf = alloc_iob ( PHN_RX_BUFSIZE );
+ if ( ! iobuf ) {
+ /* Failure is non-fatal; we will retry later */
+ netdev_rx_err ( netdev, NULL, -ENOMEM );
+ break;
+ }
+
+ /* Fill descriptor ring entry */
+ memset ( &rds, 0, sizeof ( rds ) );
+ NX_FILL_2 ( &rds, 0,
+ handle, handle,
+ length, iob_len ( iobuf ) );
+ NX_FILL_1 ( &rds, 1,
+ dma_addr, virt_to_bus ( iobuf->data ) );
+
+ /* Record I/O buffer */
+ assert ( phantom_port->rds_iobuf[handle] == NULL );
+ phantom_port->rds_iobuf[handle] = iobuf;
+
+ /* Post descriptor */
+ phantom_post_rds ( phantom_port, &rds );
+ }
+}
+
+/**
+ * Open NIC
+ *
+ * @v netdev Net device
+ * @ret rc Return status code
+ */
+static int phantom_open ( struct net_device *netdev ) {
+ struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
+ int rc;
+
+ /* Allocate and zero descriptor rings */
+ phantom_port->desc = malloc_dma ( sizeof ( *(phantom_port->desc) ),
+ UNM_DMA_BUFFER_ALIGN );
+ if ( ! phantom_port->desc ) {
+ rc = -ENOMEM;
+ goto err_alloc_desc;
+ }
+ memset ( phantom_port->desc, 0, sizeof ( *(phantom_port->desc) ) );
+
+ /* Create RX context */
+ if ( ( rc = phantom_create_rx_ctx ( phantom_port ) ) != 0 )
+ goto err_create_rx_ctx;
+
+ /* Create TX context */
+ if ( ( rc = phantom_create_tx_ctx ( phantom_port ) ) != 0 )
+ goto err_create_tx_ctx;
+
+ /* Fill the RX descriptor ring */
+ phantom_refill_rx_ring ( netdev );
+
+ /* Add MAC addresses
+ *
+ * BUG5583
+ *
+ * We would like to be able to enable receiving all multicast
+ * packets (or, failing that, promiscuous mode), but the
+ * firmware doesn't currently support this.
+ */
+ if ( ( rc = phantom_add_macaddr ( phantom_port,
+ netdev->ll_protocol->ll_broadcast ) ) != 0 )
+ goto err_add_macaddr_broadcast;
+ if ( ( rc = phantom_add_macaddr ( phantom_port,
+ netdev->ll_addr ) ) != 0 )
+ goto err_add_macaddr_unicast;
+
+ return 0;
+
+ phantom_del_macaddr ( phantom_port, netdev->ll_addr );
+ err_add_macaddr_unicast:
+ phantom_del_macaddr ( phantom_port,
+ netdev->ll_protocol->ll_broadcast );
+ err_add_macaddr_broadcast:
+ phantom_destroy_tx_ctx ( phantom_port );
+ err_create_tx_ctx:
+ phantom_destroy_rx_ctx ( phantom_port );
+ err_create_rx_ctx:
+ free_dma ( phantom_port->desc, sizeof ( *(phantom_port->desc) ) );
+ phantom_port->desc = NULL;
+ err_alloc_desc:
+ return rc;
+}
+
+/**
+ * Close NIC
+ *
+ * @v netdev Net device
+ */
+static void phantom_close ( struct net_device *netdev ) {
+ struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
+ struct io_buffer *iobuf;
+ unsigned int i;
+
+ /* Shut down the port */
+ phantom_del_macaddr ( phantom_port, netdev->ll_addr );
+ phantom_del_macaddr ( phantom_port,
+ netdev->ll_protocol->ll_broadcast );
+ phantom_destroy_tx_ctx ( phantom_port );
+ phantom_destroy_rx_ctx ( phantom_port );
+ free_dma ( phantom_port->desc, sizeof ( *(phantom_port->desc) ) );
+ phantom_port->desc = NULL;
+
+ /* Flush any uncompleted descriptors */
+ for ( i = 0 ; i < PHN_RDS_MAX_FILL ; i++ ) {
+ iobuf = phantom_port->rds_iobuf[i];
+ if ( iobuf ) {
+ free_iob ( iobuf );
+ phantom_port->rds_iobuf[i] = NULL;
+ }
+ }
+ for ( i = 0 ; i < PHN_NUM_CDS ; i++ ) {
+ iobuf = phantom_port->cds_iobuf[i];
+ if ( iobuf ) {
+ netdev_tx_complete_err ( netdev, iobuf, -ECANCELED );
+ phantom_port->cds_iobuf[i] = NULL;
+ }
+ }
+}
+
+/**
+ * Transmit packet
+ *
+ * @v netdev Network device
+ * @v iobuf I/O buffer
+ * @ret rc Return status code
+ */
+static int phantom_transmit ( struct net_device *netdev,
+ struct io_buffer *iobuf ) {
+ struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
+ union phantom_cds cds;
+ int index;
+
+ /* Get descriptor ring entry */
+ index = phantom_alloc_cds ( phantom_port );
+ if ( index < 0 )
+ return index;
+
+ /* Fill descriptor ring entry */
+ memset ( &cds, 0, sizeof ( cds ) );
+ NX_FILL_3 ( &cds, 0,
+ tx.opcode, UNM_TX_ETHER_PKT,
+ tx.num_buffers, 1,
+ tx.length, iob_len ( iobuf ) );
+ NX_FILL_2 ( &cds, 2,
+ tx.port, phantom_port->port,
+ tx.context_id, phantom_port->port );
+ NX_FILL_1 ( &cds, 4,
+ tx.buffer1_dma_addr, virt_to_bus ( iobuf->data ) );
+ NX_FILL_1 ( &cds, 5,
+ tx.buffer1_length, iob_len ( iobuf ) );
+
+ /* Record I/O buffer */
+ assert ( phantom_port->cds_iobuf[index] == NULL );
+ phantom_port->cds_iobuf[index] = iobuf;
+
+ /* Post descriptor */
+ phantom_post_cds ( phantom_port, &cds );
+
+ return 0;
+}
+
+/**
+ * Poll for received packets
+ *
+ * @v netdev Network device
+ */
+static void phantom_poll ( struct net_device *netdev ) {
+ struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
+ struct phantom_nic *phantom = phantom_port->phantom;
+ struct io_buffer *iobuf;
+ unsigned int cds_consumer_idx;
+ unsigned int raw_new_cds_consumer_idx;
+ unsigned int new_cds_consumer_idx;
+ unsigned int rds_consumer_idx;
+ unsigned int sds_consumer_idx;
+ struct phantom_sds *sds;
+ unsigned int sds_handle;
+ unsigned int sds_opcode;
+
+ /* Check for TX completions */
+ cds_consumer_idx = phantom_port->cds_consumer_idx;
+ raw_new_cds_consumer_idx = phantom_port->desc->cmd_cons;
+ new_cds_consumer_idx = le32_to_cpu ( raw_new_cds_consumer_idx );
+ while ( cds_consumer_idx != new_cds_consumer_idx ) {
+ DBGC2 ( phantom, "Phantom %p port %d CDS %d complete\n",
+ phantom, phantom_port->port, cds_consumer_idx );
+ /* Completions may be for commands other than TX, so
+ * there may not always be an associated I/O buffer.
+ */
+ if ( ( iobuf = phantom_port->cds_iobuf[cds_consumer_idx] ) ) {
+ netdev_tx_complete ( netdev, iobuf );
+ phantom_port->cds_iobuf[cds_consumer_idx] = NULL;
+ }
+ cds_consumer_idx = ( ( cds_consumer_idx + 1 ) % PHN_NUM_CDS );
+ phantom_port->cds_consumer_idx = cds_consumer_idx;
+ }
+
+ /* Check for received packets */
+ rds_consumer_idx = phantom_port->rds_consumer_idx;
+ sds_consumer_idx = phantom_port->sds_consumer_idx;
+ while ( 1 ) {
+ sds = &phantom_port->desc->sds[sds_consumer_idx];
+ if ( NX_GET ( sds, owner ) == 0 )
+ break;
+
+ DBGC2 ( phantom, "Phantom %p port %d SDS %d status:\n",
+ phantom, phantom_port->port, sds_consumer_idx );
+ DBGC2_HDA ( phantom, virt_to_bus ( sds ), sds, sizeof (*sds) );
+
+ /* Check received opcode */
+ sds_opcode = NX_GET ( sds, opcode );
+ if ( ( sds_opcode == UNM_RXPKT_DESC ) ||
+ ( sds_opcode == UNM_SYN_OFFLOAD ) ) {
+
+ /* Sanity check: ensure that all of the SDS
+ * descriptor has been written.
+ */
+ if ( NX_GET ( sds, total_length ) == 0 ) {
+ DBGC ( phantom, "Phantom %p port %d SDS %d "
+ "incomplete; deferring\n", phantom,
+ phantom_port->port, sds_consumer_idx );
+ /* Leave for next poll() */
+ break;
+ }
+
+ /* Process received packet */
+ sds_handle = NX_GET ( sds, handle );
+ iobuf = phantom_port->rds_iobuf[sds_handle];
+ assert ( iobuf != NULL );
+ iob_put ( iobuf, NX_GET ( sds, total_length ) );
+ iob_pull ( iobuf, NX_GET ( sds, pkt_offset ) );
+ DBGC2 ( phantom, "Phantom %p port %d RDS %d "
+ "complete\n",
+ phantom, phantom_port->port, sds_handle );
+ netdev_rx ( netdev, iobuf );
+ phantom_port->rds_iobuf[sds_handle] = NULL;
+
+ /* Update RDS consumer counter. This is a
+ * lower bound for the number of descriptors
+ * that have been read by the hardware, since
+ * the hardware must have read at least one
+ * descriptor for each completion that we
+ * receive.
+ */
+ rds_consumer_idx =
+ ( ( rds_consumer_idx + 1 ) % PHN_NUM_RDS );
+ phantom_port->rds_consumer_idx = rds_consumer_idx;
+
+ } else {
+
+ DBGC ( phantom, "Phantom %p port %d unexpected SDS "
+ "opcode %02x\n",
+ phantom, phantom_port->port, sds_opcode );
+ DBGC_HDA ( phantom, virt_to_bus ( sds ),
+ sds, sizeof ( *sds ) );
+ }
+
+ /* Clear status descriptor */
+ memset ( sds, 0, sizeof ( *sds ) );
+
+ /* Update SDS consumer index */
+ sds_consumer_idx = ( ( sds_consumer_idx + 1 ) % PHN_NUM_SDS );
+ phantom_port->sds_consumer_idx = sds_consumer_idx;
+ wmb();
+ phantom_writel ( phantom, phantom_port->sds_consumer_idx,
+ phantom_port->sds_consumer_crb );
+ }
+
+ /* Refill the RX descriptor ring */
+ phantom_refill_rx_ring ( netdev );
+
+ /* Occasionally poll the link state */
+ if ( phantom_port->link_poll_timer-- == 0 ) {
+ phantom_poll_link_state ( phantom );
+ /* Reset the link poll timer */
+ phantom_port->link_poll_timer = PHN_LINK_POLL_FREQUENCY;
+ }
+}
+
+/**
+ * Enable/disable interrupts
+ *
+ * @v netdev Network device
+ * @v enable Interrupts should be enabled
+ */
+static void phantom_irq ( struct net_device *netdev, int enable ) {
+ struct phantom_nic_port *phantom_port = netdev_priv ( netdev );
+ struct phantom_nic *phantom = phantom_port->phantom;
+ static const unsigned long sw_int_mask_reg[UNM_FLASH_NUM_PORTS] = {
+ UNM_NIC_REG_SW_INT_MASK_0,
+ UNM_NIC_REG_SW_INT_MASK_1,
+ UNM_NIC_REG_SW_INT_MASK_2,
+ UNM_NIC_REG_SW_INT_MASK_3
+ };
+
+ phantom_writel ( phantom,
+ ( enable ? 1 : 0 ),
+ sw_int_mask_reg[phantom_port->port] );
+}
+
+/** Phantom net device operations */
+static struct net_device_operations phantom_operations = {
+ .open = phantom_open,
+ .close = phantom_close,
+ .transmit = phantom_transmit,
+ .poll = phantom_poll,
+ .irq = phantom_irq,
+};
+
+/**
+ * Map Phantom CRB window
+ *
+ * @v phantom Phantom NIC
+ * @ret rc Return status code
+ */
+static int phantom_map_crb ( struct phantom_nic *phantom,
+ struct pci_device *pci ) {
+ unsigned long bar0_start;
+ unsigned long bar0_size;
+
+ /* CRB window is always in the last 32MB of BAR0 (which may be
+ * a 32MB or a 128MB BAR).
+ */
+ bar0_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_0 );
+ bar0_size = pci_bar_size ( pci, PCI_BASE_ADDRESS_0 );
+ DBGC ( phantom, "Phantom %p BAR0 is %08lx+%lx\n",
+ phantom, bar0_start, bar0_size );
+
+ switch ( bar0_size ) {
+ case ( 128 * 1024 * 1024 ) :
+ DBGC ( phantom, "Phantom %p has 128MB BAR\n", phantom );
+ phantom->crb_access = phantom_crb_access_128m;
+ break;
+ case ( 32 * 1024 * 1024 ) :
+ DBGC ( phantom, "Phantom %p has 32MB BAR\n", phantom );
+ phantom->crb_access = phantom_crb_access_32m;
+ break;
+ case ( 2 * 1024 * 1024 ) :
+ DBGC ( phantom, "Phantom %p has 2MB BAR\n", phantom );
+ phantom->crb_access = phantom_crb_access_2m;
+ break;
+ default:
+ DBGC ( phantom, "Phantom %p has bad BAR size\n", phantom );
+ return -EINVAL;
+ }
+
+ phantom->bar0 = ioremap ( bar0_start, bar0_size );
+ if ( ! phantom->bar0 ) {
+ DBGC ( phantom, "Phantom %p could not map BAR0\n", phantom );
+ return -EIO;
+ }
+
+ /* Mark current CRB window as invalid, so that the first
+ * read/write will set the current window.
+ */
+ phantom->crb_window = -1UL;
+
+ return 0;
+}
+
+/**
+ * Read Phantom flash contents
+ *
+ * @v phantom Phantom NIC
+ * @ret rc Return status code
+ */
+static int phantom_read_flash ( struct phantom_nic *phantom ) {
+ struct unm_board_info board_info;
+ int rc;
+
+ /* Initialise flash access */
+ phantom->spi_bus.rw = phantom_spi_rw;
+ phantom->flash.bus = &phantom->spi_bus;
+ init_m25p32 ( &phantom->flash );
+ /* Phantom doesn't support greater than 4-byte block sizes */
+ phantom->flash.nvs.block_size = UNM_SPI_BLKSIZE;
+
+ /* Read and verify board information */
+ if ( ( rc = nvs_read ( &phantom->flash.nvs, UNM_BRDCFG_START,
+ &board_info, sizeof ( board_info ) ) ) != 0 ) {
+ DBGC ( phantom, "Phantom %p could not read board info: %s\n",
+ phantom, strerror ( rc ) );
+ return rc;
+ }
+ if ( board_info.magic != UNM_BDINFO_MAGIC ) {
+ DBGC ( phantom, "Phantom %p has bad board info magic %lx\n",
+ phantom, board_info.magic );
+ DBGC_HD ( phantom, &board_info, sizeof ( board_info ) );
+ return -EINVAL;
+ }
+ if ( board_info.header_version != UNM_BDINFO_VERSION ) {
+ DBGC ( phantom, "Phantom %p has bad board info version %lx\n",
+ phantom, board_info.header_version );
+ DBGC_HD ( phantom, &board_info, sizeof ( board_info ) );
+ return -EINVAL;
+ }
+
+ /* Identify board type and number of ports */
+ switch ( board_info.board_type ) {
+ case UNM_BRDTYPE_P3_4_GB:
+ case UNM_BRDTYPE_P3_4_GB_MM:
+ phantom->num_ports = 4;
+ break;
+ case UNM_BRDTYPE_P3_HMEZ:
+ case UNM_BRDTYPE_P3_IMEZ:
+ case UNM_BRDTYPE_P3_10G_CX4:
+ case UNM_BRDTYPE_P3_10G_CX4_LP:
+ case UNM_BRDTYPE_P3_10G_SFP_PLUS:
+ case UNM_BRDTYPE_P3_XG_LOM:
+ phantom->num_ports = 2;
+ break;
+ case UNM_BRDTYPE_P3_10000_BASE_T:
+ case UNM_BRDTYPE_P3_10G_XFP:
+ phantom->num_ports = 1;
+ break;
+ default:
+ DBGC ( phantom, "Phantom %p unrecognised board type %#lx; "
+ "assuming single-port\n",
+ phantom, board_info.board_type );
+ phantom->num_ports = 1;
+ break;
+ }
+ DBGC ( phantom, "Phantom %p board type is %#lx (%d ports)\n",
+ phantom, board_info.board_type, phantom->num_ports );
+
+ return 0;
+}
+
+/**
+ * Initialise the Phantom command PEG
+ *
+ * @v phantom Phantom NIC
+ * @ret rc Return status code
+ */
+static int phantom_init_cmdpeg ( struct phantom_nic *phantom ) {
+ uint32_t cold_boot;
+ uint32_t sw_reset;
+ physaddr_t dummy_dma_phys;
+ unsigned int retries;
+ uint32_t cmdpeg_state;
+ uint32_t last_cmdpeg_state = 0;
+
+ /* If this was a cold boot, check that the hardware came up ok */
+ cold_boot = phantom_readl ( phantom, UNM_CAM_RAM_COLD_BOOT );
+ if ( cold_boot == UNM_CAM_RAM_COLD_BOOT_MAGIC ) {
+ DBGC ( phantom, "Phantom %p coming up from cold boot\n",
+ phantom );
+ sw_reset = phantom_readl ( phantom, UNM_ROMUSB_GLB_SW_RESET );
+ if ( sw_reset != UNM_ROMUSB_GLB_SW_RESET_MAGIC ) {
+ DBGC ( phantom, "Phantom %p reset failed: %08lx\n",
+ phantom, sw_reset );
+ return -EIO;
+ }
+ } else {
+ DBGC ( phantom, "Phantom %p coming up from warm boot "
+ "(%08lx)\n", phantom, cold_boot );
+ }
+ /* Clear cold-boot flag */
+ phantom_writel ( phantom, 0, UNM_CAM_RAM_COLD_BOOT );
+
+ /* Set port modes */
+ phantom_writel ( phantom, UNM_CAM_RAM_PORT_MODE_AUTO_NEG,
+ UNM_CAM_RAM_PORT_MODE );
+ phantom_writel ( phantom, UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G,
+ UNM_CAM_RAM_WOL_PORT_MODE );
+
+ /* Pass dummy DMA area to card */
+ dummy_dma_phys = virt_to_bus ( phantom->dma_buf->dummy_dma );
+ DBGC ( phantom, "Phantom %p dummy DMA at %08lx\n",
+ phantom, dummy_dma_phys );
+ phantom_write_hilo ( phantom, dummy_dma_phys,
+ UNM_NIC_REG_DUMMY_BUF_ADDR_LO,
+ UNM_NIC_REG_DUMMY_BUF_ADDR_HI );
+ phantom_writel ( phantom, UNM_NIC_REG_DUMMY_BUF_INIT,
+ UNM_NIC_REG_DUMMY_BUF );
+
+ /* Tell the hardware that tuning is complete */
+ phantom_writel ( phantom, 1, UNM_ROMUSB_GLB_PEGTUNE_DONE );
+
+ /* Wait for command PEG to finish initialising */
+ DBGC ( phantom, "Phantom %p initialising command PEG (will take up to "
+ "%d seconds)...\n", phantom, PHN_CMDPEG_INIT_TIMEOUT_SEC );
+ for ( retries = 0; retries < PHN_CMDPEG_INIT_TIMEOUT_SEC; retries++ ) {
+ cmdpeg_state = phantom_readl ( phantom,
+ UNM_NIC_REG_CMDPEG_STATE );
+ if ( cmdpeg_state != last_cmdpeg_state ) {
+ DBGC ( phantom, "Phantom %p command PEG state is "
+ "%08lx after %d seconds...\n",
+ phantom, cmdpeg_state, retries );
+ last_cmdpeg_state = cmdpeg_state;
+ }
+ if ( cmdpeg_state == UNM_NIC_REG_CMDPEG_STATE_INITIALIZED ) {
+ /* Acknowledge the PEG initialisation */
+ phantom_writel ( phantom,
+ UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK,
+ UNM_NIC_REG_CMDPEG_STATE );
+ return 0;
+ }
+ mdelay ( 1000 );
+ }
+
+ DBGC ( phantom, "Phantom %p timed out waiting for command PEG to "
+ "initialise (status %08lx)\n", phantom, cmdpeg_state );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Read Phantom MAC address
+ *
+ * @v phanton_port Phantom NIC port
+ * @v ll_addr Buffer to fill with MAC address
+ */
+static void phantom_get_macaddr ( struct phantom_nic_port *phantom_port,
+ uint8_t *ll_addr ) {
+ struct phantom_nic *phantom = phantom_port->phantom;
+ union {
+ uint8_t mac_addr[2][ETH_ALEN];
+ uint32_t dwords[3];
+ } u;
+ unsigned long offset;
+ int i;
+
+ /* Read the three dwords that include this MAC address and one other */
+ offset = ( UNM_CAM_RAM_MAC_ADDRS +
+ ( 12 * ( phantom_port->port / 2 ) ) );
+ for ( i = 0 ; i < 3 ; i++, offset += 4 ) {
+ u.dwords[i] = phantom_readl ( phantom, offset );
+ }
+
+ /* Copy out the relevant MAC address */
+ for ( i = 0 ; i < ETH_ALEN ; i++ ) {
+ ll_addr[ ETH_ALEN - i - 1 ] =
+ u.mac_addr[ phantom_port->port & 1 ][i];
+ }
+ DBGC ( phantom, "Phantom %p port %d MAC address is %s\n",
+ phantom, phantom_port->port, eth_ntoa ( ll_addr ) );
+}
+
+/**
+ * Initialise Phantom receive PEG
+ *
+ * @v phantom Phantom NIC
+ * @ret rc Return status code
+ */
+static int phantom_init_rcvpeg ( struct phantom_nic *phantom ) {
+ unsigned int retries;
+ uint32_t rcvpeg_state;
+ uint32_t last_rcvpeg_state = 0;
+
+ DBGC ( phantom, "Phantom %p initialising receive PEG (will take up to "
+ "%d seconds)...\n", phantom, PHN_RCVPEG_INIT_TIMEOUT_SEC );
+ for ( retries = 0; retries < PHN_RCVPEG_INIT_TIMEOUT_SEC; retries++ ) {
+ rcvpeg_state = phantom_readl ( phantom,
+ UNM_NIC_REG_RCVPEG_STATE );
+ if ( rcvpeg_state != last_rcvpeg_state ) {
+ DBGC ( phantom, "Phantom %p receive PEG state is "
+ "%08lx after %d seconds...\n",
+ phantom, rcvpeg_state, retries );
+ last_rcvpeg_state = rcvpeg_state;
+ }
+ if ( rcvpeg_state == UNM_NIC_REG_RCVPEG_STATE_INITIALIZED )
+ return 0;
+ mdelay ( 1000 );
+ }
+
+ DBGC ( phantom, "Phantom %p timed out waiting for receive PEG to "
+ "initialise (status %08lx)\n", phantom, rcvpeg_state );
+ return -ETIMEDOUT;
+}
+
+/**
+ * Probe PCI device
+ *
+ * @v pci PCI device
+ * @v id PCI ID
+ * @ret rc Return status code
+ */
+static int phantom_probe ( struct pci_device *pci,
+ const struct pci_device_id *id __unused ) {
+ struct phantom_nic *phantom;
+ struct net_device *netdev;
+ struct phantom_nic_port *phantom_port;
+ int i;
+ int rc;
+
+ /* Phantom NICs expose multiple PCI functions, used for
+ * virtualisation. Ignore everything except function 0.
+ */
+ if ( PCI_FUNC ( pci->devfn ) != 0 )
+ return -ENODEV;
+
+ /* Allocate Phantom device */
+ phantom = zalloc ( sizeof ( *phantom ) );
+ if ( ! phantom ) {
+ rc = -ENOMEM;
+ goto err_alloc_phantom;
+ }
+ pci_set_drvdata ( pci, phantom );
+
+ /* Fix up PCI device */
+ adjust_pci_device ( pci );
+
+ /* Map CRB */
+ if ( ( rc = phantom_map_crb ( phantom, pci ) ) != 0 )
+ goto err_map_crb;
+
+ /* Read flash information */
+ if ( ( rc = phantom_read_flash ( phantom ) ) != 0 )
+ goto err_read_flash;
+
+ /* Allocate net devices for each port */
+ for ( i = 0 ; i < phantom->num_ports ; i++ ) {
+ netdev = alloc_etherdev ( sizeof ( *phantom_port ) );
+ if ( ! netdev ) {
+ rc = -ENOMEM;
+ goto err_alloc_etherdev;
+ }
+ phantom->netdev[i] = netdev;
+ netdev_init ( netdev, &phantom_operations );
+ phantom_port = netdev_priv ( netdev );
+ netdev->dev = &pci->dev;
+ phantom_port->phantom = phantom;
+ phantom_port->port = i;
+ }
+
+ /* Allocate dummy DMA buffer and perform initial hardware handshake */
+ phantom->dma_buf = malloc_dma ( sizeof ( *(phantom->dma_buf) ),
+ UNM_DMA_BUFFER_ALIGN );
+ if ( ! phantom->dma_buf )
+ goto err_dma_buf;
+ if ( ( rc = phantom_init_cmdpeg ( phantom ) ) != 0 )
+ goto err_init_cmdpeg;
+
+ /* Initialise the receive firmware */
+ if ( ( rc = phantom_init_rcvpeg ( phantom ) ) != 0 )
+ goto err_init_rcvpeg;
+
+ /* Read MAC addresses */
+ for ( i = 0 ; i < phantom->num_ports ; i++ ) {
+ phantom_port = netdev_priv ( phantom->netdev[i] );
+ phantom_get_macaddr ( phantom_port,
+ phantom->netdev[i]->ll_addr );
+ }
+
+ /* Register network devices */
+ for ( i = 0 ; i < phantom->num_ports ; i++ ) {
+ if ( ( rc = register_netdev ( phantom->netdev[i] ) ) != 0 ) {
+ DBGC ( phantom, "Phantom %p could not register port "
+ "%d: %s\n", phantom, i, strerror ( rc ) );
+ goto err_register_netdev;
+ }
+ }
+
+ return 0;
+
+ i = ( phantom->num_ports - 1 );
+ err_register_netdev:
+ for ( ; i >= 0 ; i-- )
+ unregister_netdev ( phantom->netdev[i] );
+ err_init_rcvpeg:
+ err_init_cmdpeg:
+ free_dma ( phantom->dma_buf, sizeof ( *(phantom->dma_buf) ) );
+ phantom->dma_buf = NULL;
+ err_dma_buf:
+ i = ( phantom->num_ports - 1 );
+ err_alloc_etherdev:
+ for ( ; i >= 0 ; i-- ) {
+ netdev_nullify ( phantom->netdev[i] );
+ netdev_put ( phantom->netdev[i] );
+ }
+ err_read_flash:
+ err_map_crb:
+ free ( phantom );
+ err_alloc_phantom:
+ return rc;
+}
+
+/**
+ * Remove PCI device
+ *
+ * @v pci PCI device
+ */
+static void phantom_remove ( struct pci_device *pci ) {
+ struct phantom_nic *phantom = pci_get_drvdata ( pci );
+ int i;
+
+ for ( i = ( phantom->num_ports - 1 ) ; i >= 0 ; i-- )
+ unregister_netdev ( phantom->netdev[i] );
+ free_dma ( phantom->dma_buf, sizeof ( *(phantom->dma_buf) ) );
+ phantom->dma_buf = NULL;
+ for ( i = ( phantom->num_ports - 1 ) ; i >= 0 ; i-- ) {
+ netdev_nullify ( phantom->netdev[i] );
+ netdev_put ( phantom->netdev[i] );
+ }
+ free ( phantom );
+}
+
+/** Phantom PCI IDs */
+static struct pci_device_id phantom_nics[] = {
+ PCI_ROM ( 0x4040, 0x0100, "nx", "NX" ),
+};
+
+/** Phantom PCI driver */
+struct pci_driver phantom_driver __pci_driver = {
+ .ids = phantom_nics,
+ .id_count = ( sizeof ( phantom_nics ) / sizeof ( phantom_nics[0] ) ),
+ .probe = phantom_probe,
+ .remove = phantom_remove,
+};
diff --git a/gpxe/src/drivers/net/phantom/phantom.h b/gpxe/src/drivers/net/phantom/phantom.h
new file mode 100644
index 00000000..3c759989
--- /dev/null
+++ b/gpxe/src/drivers/net/phantom/phantom.h
@@ -0,0 +1,272 @@
+#ifndef _PHANTOM_H
+#define _PHANTOM_H
+
+/*
+ * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
+ * Copyright (C) 2008 NetXen, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/**
+ * @file
+ *
+ * NetXen Phantom NICs
+ *
+ */
+
+#include <stdint.h>
+
+/* Drag in hardware definitions */
+#include "nx_bitops.h"
+#include "phantom_hw.h"
+struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
+struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
+union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
+
+/* Drag in firmware interface definitions */
+typedef uint8_t U8;
+typedef uint16_t U16;
+typedef uint32_t U32;
+typedef uint64_t U64;
+typedef uint32_t nx_rcode_t;
+#define NXHAL_VERSION 1
+#include "nxhal_nic_interface.h"
+
+/** SPI controller maximum block size */
+#define UNM_SPI_BLKSIZE 4
+
+/** DMA buffer alignment */
+#define UNM_DMA_BUFFER_ALIGN 16
+
+/** Mark structure as DMA-aligned */
+#define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
+
+/** Dummy DMA buffer size */
+#define UNM_DUMMY_DMA_SIZE 1024
+
+/******************************************************************************
+ *
+ * Register definitions
+ *
+ */
+
+#define UNM_128M_CRB_WINDOW 0x6110210UL
+#define UNM_32M_CRB_WINDOW 0x0110210UL
+#define UNM_2M_CRB_WINDOW 0x0130060UL
+
+/**
+ * Phantom register blocks
+ *
+ * The upper address bits vary between cards. We define an abstract
+ * address space in which the upper 8 bits of the 32-bit register
+ * address encode the register block. This gets translated to a bus
+ * address by the phantom_crb_access_xxx() methods.
+ */
+enum unm_reg_blocks {
+ UNM_CRB_BLK_PCIE,
+ UNM_CRB_BLK_CAM,
+ UNM_CRB_BLK_ROMUSB,
+ UNM_CRB_BLK_TEST,
+};
+#define UNM_CRB_BASE(blk) ( (blk) << 24 )
+#define UNM_CRB_BLK(reg) ( (reg) >> 24 )
+#define UNM_CRB_OFFSET(reg) ( (reg) & 0x00ffffff )
+
+#define UNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
+#define UNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 )
+#define UNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 )
+
+#define UNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
+
+#define UNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 )
+#define UNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 )
+#define UNM_CAM_RAM_PORT_MODE_AUTO_NEG 4
+#define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G 5
+#define UNM_CAM_RAM_DMESG_HEAD(n) ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
+#define UNM_CAM_RAM_DMESG_LEN(n) ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
+#define UNM_CAM_RAM_DMESG_TAIL(n) ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
+#define UNM_CAM_RAM_DMESG_SIG(n) ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
+#define UNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL
+#define UNM_CAM_RAM_NUM_DMESG_BUFFERS 5
+#define UNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 )
+#define UNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 )
+#define UNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc )
+#define UNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL
+
+#define UNM_NIC_REG ( UNM_CRB_CAM + 0x02200 )
+#define UNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 )
+#define UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c )
+#define UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 )
+#define UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 )
+#define UNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 )
+#define UNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c )
+#define UNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 )
+#define UNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 )
+#define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED 0xff01
+#define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f
+#define UNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc )
+#define UNM_NIC_REG_DUMMY_BUF_INIT 0
+#define UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 )
+#define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
+ ( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
+#define UNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01
+#define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN 0x02
+#define UNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c )
+#define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED 0xff01
+#define UNM_NIC_REG_SW_INT_MASK_0 ( UNM_NIC_REG + 0x001d8 )
+#define UNM_NIC_REG_SW_INT_MASK_1 ( UNM_NIC_REG + 0x001e0 )
+#define UNM_NIC_REG_SW_INT_MASK_2 ( UNM_NIC_REG + 0x001e4 )
+#define UNM_NIC_REG_SW_INT_MASK_3 ( UNM_NIC_REG + 0x001e8 )
+
+#define UNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
+
+#define UNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 )
+#define UNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 )
+#define UNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 )
+#define UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 )
+#define UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL
+#define UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c )
+
+#define UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 )
+#define UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 )
+#define UNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 )
+#define UNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c )
+#define UNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 )
+#define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 )
+#define UNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 )
+
+#define UNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
+
+#define UNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 )
+#define UNM_TEST_CONTROL_START 0x01
+#define UNM_TEST_CONTROL_ENABLE 0x02
+#define UNM_TEST_CONTROL_BUSY 0x08
+#define UNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 )
+#define UNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 )
+#define UNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 )
+#define UNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac )
+
+/******************************************************************************
+ *
+ * Flash layout
+ *
+ */
+
+/* Board configuration */
+
+#define UNM_BRDCFG_START 0x4000
+
+struct unm_board_info {
+ uint32_t header_version;
+ uint32_t board_mfg;
+ uint32_t board_type;
+ uint32_t board_num;
+ uint32_t chip_id;
+ uint32_t chip_minor;
+ uint32_t chip_major;
+ uint32_t chip_pkg;
+ uint32_t chip_lot;
+ uint32_t port_mask;
+ uint32_t peg_mask;
+ uint32_t icache_ok;
+ uint32_t dcache_ok;
+ uint32_t casper_ok;
+ uint32_t mac_addr_lo_0;
+ uint32_t mac_addr_lo_1;
+ uint32_t mac_addr_lo_2;
+ uint32_t mac_addr_lo_3;
+ uint32_t mn_sync_mode;
+ uint32_t mn_sync_shift_cclk;
+ uint32_t mn_sync_shift_mclk;
+ uint32_t mn_wb_en;
+ uint32_t mn_crystal_freq;
+ uint32_t mn_speed;
+ uint32_t mn_org;
+ uint32_t mn_depth;
+ uint32_t mn_ranks_0;
+ uint32_t mn_ranks_1;
+ uint32_t mn_rd_latency_0;
+ uint32_t mn_rd_latency_1;
+ uint32_t mn_rd_latency_2;
+ uint32_t mn_rd_latency_3;
+ uint32_t mn_rd_latency_4;
+ uint32_t mn_rd_latency_5;
+ uint32_t mn_rd_latency_6;
+ uint32_t mn_rd_latency_7;
+ uint32_t mn_rd_latency_8;
+ uint32_t mn_dll_val[18];
+ uint32_t mn_mode_reg;
+ uint32_t mn_ext_mode_reg;
+ uint32_t mn_timing_0;
+ uint32_t mn_timing_1;
+ uint32_t mn_timing_2;
+ uint32_t sn_sync_mode;
+ uint32_t sn_pt_mode;
+ uint32_t sn_ecc_en;
+ uint32_t sn_wb_en;
+ uint32_t sn_crystal_freq;
+ uint32_t sn_speed;
+ uint32_t sn_org;
+ uint32_t sn_depth;
+ uint32_t sn_dll_tap;
+ uint32_t sn_rd_latency;
+ uint32_t mac_addr_hi_0;
+ uint32_t mac_addr_hi_1;
+ uint32_t mac_addr_hi_2;
+ uint32_t mac_addr_hi_3;
+ uint32_t magic;
+ uint32_t mn_rdimm;
+ uint32_t mn_dll_override;
+};
+
+#define UNM_BDINFO_VERSION 1
+#define UNM_BRDTYPE_P3_HMEZ 0x0022
+#define UNM_BRDTYPE_P3_10G_CX4_LP 0x0023
+#define UNM_BRDTYPE_P3_4_GB 0x0024
+#define UNM_BRDTYPE_P3_IMEZ 0x0025
+#define UNM_BRDTYPE_P3_10G_SFP_PLUS 0x0026
+#define UNM_BRDTYPE_P3_10000_BASE_T 0x0027
+#define UNM_BRDTYPE_P3_XG_LOM 0x0028
+#define UNM_BRDTYPE_P3_4_GB_MM 0x0029
+#define UNM_BRDTYPE_P3_10G_CX4 0x0031
+#define UNM_BRDTYPE_P3_10G_XFP 0x0032
+#define UNM_BDINFO_MAGIC 0x12345678
+
+/* User defined region */
+
+#define UNM_USER_START 0x3e8000
+
+#define UNM_FLASH_NUM_PORTS 4
+#define UNM_FLASH_NUM_MAC_PER_PORT 32
+
+struct unm_user_info {
+ uint8_t flash_md5[16 * 64];
+ uint32_t bootld_version;
+ uint32_t bootld_size;
+ uint32_t image_version;
+ uint32_t image_size;
+ uint32_t primary_status;
+ uint32_t secondary_present;
+ /* MAC address , 4 ports, 32 address per port */
+ uint64_t mac_addr[UNM_FLASH_NUM_PORTS * UNM_FLASH_NUM_MAC_PER_PORT];
+ uint32_t sub_sys_id;
+ uint8_t serial_num[32];
+ uint32_t bios_version;
+ uint32_t pxe_enable;
+ uint32_t vlan_tag[UNM_FLASH_NUM_PORTS];
+};
+
+#endif /* _PHANTOM_H */
diff --git a/gpxe/src/drivers/net/phantom/phantom_hw.h b/gpxe/src/drivers/net/phantom/phantom_hw.h
new file mode 100644
index 00000000..e2c3e537
--- /dev/null
+++ b/gpxe/src/drivers/net/phantom/phantom_hw.h
@@ -0,0 +1,182 @@
+#ifndef _PHANTOM_HW_H
+#define _PHANTOM_HW_H
+
+/*
+ * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
+ * Copyright (C) 2008 NetXen, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/**
+ * @file
+ *
+ * Phantom hardware definitions
+ *
+ */
+
+/** A Phantom RX descriptor */
+struct phantom_rds_pb {
+ pseudo_bit_t handle[16]; /**< Reference handle */
+ pseudo_bit_t flags[16]; /**< Flags */
+ pseudo_bit_t length[32]; /**< Buffer length */
+
+ /* --------------------------------------------------------------- */
+
+ pseudo_bit_t dma_addr[64]; /**< Buffer DMA address */
+
+};
+
+/** A Phantom RX status descriptor */
+struct phantom_sds_pb {
+ pseudo_bit_t port[4]; /**< Port number */
+ pseudo_bit_t status[4]; /**< Checksum status */
+ pseudo_bit_t type[4]; /**< Type */
+ pseudo_bit_t total_length[16]; /**< Total packet length */
+ pseudo_bit_t handle[16]; /**< Reference handle */
+ pseudo_bit_t protocol[4]; /**< Protocol */
+ pseudo_bit_t pkt_offset[5]; /**< Offset to packet start */
+ pseudo_bit_t desc_cnt[3]; /**< Descriptor count */
+ pseudo_bit_t owner[2]; /**< Owner */
+ pseudo_bit_t opcode[6]; /**< Opcode */
+
+ /* --------------------------------------------------------------- */
+
+ pseudo_bit_t hash_value[32]; /**< RSS hash value */
+ pseudo_bit_t hash_type[8]; /**< RSS hash type */
+ pseudo_bit_t lro[8]; /**< LRO data */
+};
+
+/** Phantom RX status opcodes */
+enum phantom_sds_opcode {
+ UNM_SYN_OFFLOAD = 0x03,
+ UNM_RXPKT_DESC = 0x04,
+};
+
+/** A Phantom TX descriptor */
+struct phantom_tx_cds_pb {
+ pseudo_bit_t tcp_hdr_offset[8]; /**< TCP header offset (LSO) */
+ pseudo_bit_t ip_hdr_offset[8]; /**< IP header offset (LSO) */
+ pseudo_bit_t flags[7]; /**< Flags */
+ pseudo_bit_t opcode[6]; /**< Opcode */
+ pseudo_bit_t hw_rsvd_0[3]; /**< (Reserved) */
+ pseudo_bit_t num_buffers[8]; /**< Total number of buffers */
+ pseudo_bit_t length[24]; /**< Total length */
+
+ /* --------------------------------------------------------------- */
+
+ pseudo_bit_t buffer2_dma_addr[64]; /**< Buffer 2 DMA address */
+
+ /* --------------------------------------------------------------- */
+
+ pseudo_bit_t handle[16]; /**< Reference handle (n/a) */
+ pseudo_bit_t port_mss[16]; /**< TCP MSS (LSO) */
+ pseudo_bit_t port[4]; /**< Port */
+ pseudo_bit_t context_id[4]; /**< Context ID */
+ pseudo_bit_t total_hdr_length[8]; /**< MAC+IP+TCP header (LSO) */
+ pseudo_bit_t conn_id[16]; /**< IPSec connection ID */
+
+ /* --------------------------------------------------------------- */
+
+ pseudo_bit_t buffer3_dma_addr[64]; /**< Buffer 3 DMA address */
+
+ /* --------------------------------------------------------------- */
+
+ pseudo_bit_t buffer1_dma_addr[64]; /**< Buffer 1 DMA address */
+
+ /* --------------------------------------------------------------- */
+
+ pseudo_bit_t buffer1_length[16]; /**< Buffer 1 length */
+ pseudo_bit_t buffer2_length[16]; /**< Buffer 2 length */
+ pseudo_bit_t buffer3_length[16]; /**< Buffer 3 length */
+ pseudo_bit_t buffer4_length[16]; /**< Buffer 4 length */
+
+ /* --------------------------------------------------------------- */
+
+ pseudo_bit_t buffer4_dma_addr[64]; /**< Buffer 4 DMA address */
+
+ /* --------------------------------------------------------------- */
+
+ pseudo_bit_t hw_rsvd_1[64]; /**< (Reserved) */
+};
+
+/** A Phantom MAC address request body */
+struct phantom_nic_request_body_mac_request_pb {
+ pseudo_bit_t opcode[8]; /**< Opcode */
+ pseudo_bit_t tag[8]; /**< Tag */
+ pseudo_bit_t mac_addr_0[8]; /**< MAC address byte 0 */
+ pseudo_bit_t mac_addr_1[8]; /**< MAC address byte 1 */
+ pseudo_bit_t mac_addr_2[8]; /**< MAC address byte 2 */
+ pseudo_bit_t mac_addr_3[8]; /**< MAC address byte 3 */
+ pseudo_bit_t mac_addr_4[8]; /**< MAC address byte 4 */
+ pseudo_bit_t mac_addr_5[8]; /**< MAC address byte 5 */
+};
+
+/** Phantom MAC request opcodes */
+enum phantom_mac_request_opcode {
+ UNM_MAC_ADD = 0x01, /**< Add MAC address */
+ UNM_MAC_DEL = 0x02, /**< Delete MAC address */
+};
+
+/** A Phantom NIC request command descriptor */
+struct phantom_nic_request_cds_pb {
+ struct {
+ pseudo_bit_t dst_minor[18];
+ pseudo_bit_t dst_subq[1];
+ pseudo_bit_t dst_major[4];
+ pseudo_bit_t opcode[6];
+ pseudo_bit_t hw_rsvd_0[3];
+ pseudo_bit_t msginfo[24];
+ pseudo_bit_t hw_rsvd_1[2];
+ pseudo_bit_t qmsg_type[6];
+ } common;
+
+ /* --------------------------------------------------------------- */
+
+ struct {
+ pseudo_bit_t opcode[8];
+ pseudo_bit_t comp_id [8];
+ pseudo_bit_t context_id[16];
+ pseudo_bit_t need_completion[1];
+ pseudo_bit_t hw_rsvd_0[23];
+ pseudo_bit_t sub_opcode[8];
+ } header;
+
+ /* --------------------------------------------------------------- */
+
+ union {
+ struct phantom_nic_request_body_mac_request_pb mac_request;
+ pseudo_bit_t padding[384];
+ } body;
+};
+
+/** Phantom NIC request opcodes */
+enum phantom_nic_request_opcode {
+ UNM_MAC_EVENT = 0x01, /**< Add/delete MAC address */
+};
+
+/** A Phantom command descriptor */
+union phantom_cds_pb {
+ struct phantom_tx_cds_pb tx;
+ struct phantom_nic_request_cds_pb nic_request;
+};
+
+/** Phantom command descriptor opcodes */
+enum phantom_cds_opcode {
+ UNM_TX_ETHER_PKT = 0x01, /**< Transmit raw Ethernet */
+ UNM_NIC_REQUEST = 0x14, /**< NIC request */
+};
+
+#endif /* _PHANTOM_HW_H */
diff --git a/gpxe/src/drivers/net/virtio-net.c b/gpxe/src/drivers/net/virtio-net.c
new file mode 100644
index 00000000..4ec154df
--- /dev/null
+++ b/gpxe/src/drivers/net/virtio-net.c
@@ -0,0 +1,492 @@
+/* virtio-net.c - etherboot driver for virtio network interface
+ *
+ * (c) Copyright 2008 Bull S.A.S.
+ *
+ * Author: Laurent Vivier <Laurent.Vivier@bull.net>
+ *
+ * some parts from Linux Virtio PCI driver
+ *
+ * Copyright IBM Corp. 2007
+ * Authors: Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * some parts from Linux Virtio Ring
+ *
+ * Copyright Rusty Russell IBM Corporation 2007
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ *
+ */
+
+#include "etherboot.h"
+#include "nic.h"
+#include "virtio-ring.h"
+#include "virtio-pci.h"
+#include "virtio-net.h"
+
+#define BUG() do { \
+ printf("BUG: failure at %s:%d/%s()!\n", \
+ __FILE__, __LINE__, __FUNCTION__); \
+ while(1); \
+} while (0)
+#define BUG_ON(condition) do { if (condition) BUG(); } while (0)
+
+/* Ethernet header */
+
+struct eth_hdr {
+ unsigned char dst_addr[ETH_ALEN];
+ unsigned char src_addr[ETH_ALEN];
+ unsigned short type;
+};
+
+struct eth_frame {
+ struct eth_hdr hdr;
+ unsigned char data[ETH_FRAME_LEN];
+};
+
+typedef unsigned char virtio_queue_t[PAGE_MASK + vring_size(MAX_QUEUE_NUM)];
+
+/* TX: virtio header and eth buffer */
+
+static struct virtio_net_hdr tx_virtio_hdr;
+static struct eth_frame tx_eth_frame;
+
+/* RX: virtio headers and buffers */
+
+#define RX_BUF_NB 6
+static struct virtio_net_hdr rx_hdr[RX_BUF_NB];
+static unsigned char rx_buffer[RX_BUF_NB][ETH_FRAME_LEN];
+
+/* virtio queues and vrings */
+
+enum {
+ RX_INDEX = 0,
+ TX_INDEX,
+ QUEUE_NB
+};
+
+static virtio_queue_t queue[QUEUE_NB];
+static struct vring vring[QUEUE_NB];
+static u16 free_head[QUEUE_NB];
+static u16 last_used_idx[QUEUE_NB];
+static u16 vdata[QUEUE_NB][MAX_QUEUE_NUM];
+
+/*
+ * Virtio PCI interface
+ *
+ */
+
+static int vp_find_vq(struct nic *nic, int queue_index)
+{
+ struct vring * vr = &vring[queue_index];
+ u16 num;
+
+ /* select the queue */
+
+ outw(queue_index, nic->ioaddr + VIRTIO_PCI_QUEUE_SEL);
+
+ /* check if the queue is available */
+
+ num = inw(nic->ioaddr + VIRTIO_PCI_QUEUE_NUM);
+ if (!num) {
+ printf("ERROR: queue size is 0\n");
+ return -1;
+ }
+
+ if (num > MAX_QUEUE_NUM) {
+ printf("ERROR: queue size %d > %d\n", num, MAX_QUEUE_NUM);
+ return -1;
+ }
+
+ /* check if the queue is already active */
+
+ if (inl(nic->ioaddr + VIRTIO_PCI_QUEUE_PFN)) {
+ printf("ERROR: queue already active\n");
+ return -1;
+ }
+
+ /* initialize the queue */
+
+ vring_init(vr, num, (unsigned char*)&queue[queue_index]);
+
+ /* activate the queue
+ *
+ * NOTE: vr->desc is initialized by vring_init()
+ */
+
+ outl((unsigned long)virt_to_phys(vr->desc) >> PAGE_SHIFT,
+ nic->ioaddr + VIRTIO_PCI_QUEUE_PFN);
+
+ return num;
+}
+
+/*
+ * Virtual ring management
+ *
+ */
+
+static void vring_enable_cb(int queue_index)
+{
+ vring[queue_index].avail->flags &= ~VRING_AVAIL_F_NO_INTERRUPT;
+}
+
+static void vring_disable_cb(int queue_index)
+{
+ vring[queue_index].avail->flags |= VRING_AVAIL_F_NO_INTERRUPT;
+}
+
+/*
+ * vring_free
+ *
+ * put at the begin of the free list the current desc[head]
+ */
+
+static void vring_detach(int queue_index, unsigned int head)
+{
+ struct vring *vr = &vring[queue_index];
+ unsigned int i;
+
+ /* find end of given descriptor */
+
+ i = head;
+ while (vr->desc[i].flags & VRING_DESC_F_NEXT)
+ i = vr->desc[i].next;
+
+ /* link it with free list and point to it */
+
+ vr->desc[i].next = free_head[queue_index];
+ wmb();
+ free_head[queue_index] = head;
+}
+
+/*
+ * vring_more_used
+ *
+ * is there some used buffers ?
+ *
+ */
+
+static inline int vring_more_used(int queue_index)
+{
+ wmb();
+ return last_used_idx[queue_index] != vring[queue_index].used->idx;
+}
+
+/*
+ * vring_get_buf
+ *
+ * get a buffer from the used list
+ *
+ */
+
+static int vring_get_buf(int queue_index, unsigned int *len)
+{
+ struct vring *vr = &vring[queue_index];
+ struct vring_used_elem *elem;
+ u32 id;
+ int ret;
+
+ elem = &vr->used->ring[last_used_idx[queue_index] % vr->num];
+ wmb();
+ id = elem->id;
+ if (len != NULL)
+ *len = elem->len;
+
+ ret = vdata[queue_index][id];
+
+ vring_detach(queue_index, id);
+
+ last_used_idx[queue_index]++;
+
+ return ret;
+}
+
+static void vring_add_buf(int queue_index, int index, int num_added)
+{
+ struct vring *vr = &vring[queue_index];
+ int i, avail, head;
+
+ BUG_ON(queue_index >= QUEUE_NB);
+
+ head = free_head[queue_index];
+ i = head;
+
+ if (queue_index == TX_INDEX) {
+
+ BUG_ON(index != 0);
+
+ /* add header into vring */
+
+ vr->desc[i].flags = VRING_DESC_F_NEXT;
+ vr->desc[i].addr = (u64)virt_to_phys(&tx_virtio_hdr);
+ vr->desc[i].len = sizeof(struct virtio_net_hdr);
+ i = vr->desc[i].next;
+
+ /* add frame buffer into vring */
+
+ vr->desc[i].flags = 0;
+ vr->desc[i].addr = (u64)virt_to_phys(&tx_eth_frame);
+ vr->desc[i].len = ETH_FRAME_LEN;
+ i = vr->desc[i].next;
+
+ } else if (queue_index == RX_INDEX) {
+
+ BUG_ON(index >= RX_BUF_NB);
+
+ /* add header into vring */
+
+ vr->desc[i].flags = VRING_DESC_F_NEXT|VRING_DESC_F_WRITE;
+ vr->desc[i].addr = (u64)virt_to_phys(&rx_hdr[index]);
+ vr->desc[i].len = sizeof(struct virtio_net_hdr);
+ i = vr->desc[i].next;
+
+ /* add frame buffer into vring */
+
+ vr->desc[i].flags = VRING_DESC_F_WRITE;
+ vr->desc[i].addr = (u64)virt_to_phys(&rx_buffer[index]);
+ vr->desc[i].len = ETH_FRAME_LEN;
+ i = vr->desc[i].next;
+ }
+
+ free_head[queue_index] = i;
+
+ vdata[queue_index][head] = index;
+
+ avail = (vr->avail->idx + num_added) % vr->num;
+ vr->avail->ring[avail] = head;
+ wmb();
+}
+
+static void vring_kick(struct nic *nic, int queue_index, int num_added)
+{
+ struct vring *vr = &vring[queue_index];
+
+ wmb();
+ vr->avail->idx += num_added;
+
+ mb();
+ if (!(vr->used->flags & VRING_USED_F_NO_NOTIFY))
+ vp_notify(nic, queue_index);
+}
+
+/*
+ * virtnet_disable
+ *
+ * Turn off ethernet interface
+ *
+ */
+
+static void virtnet_disable(struct nic *nic)
+{
+ int i;
+
+ for (i = 0; i < QUEUE_NB; i++) {
+ vring_disable_cb(i);
+ vp_del_vq(nic, i);
+ }
+ vp_reset(nic);
+}
+
+/*
+ * virtnet_poll
+ *
+ * Wait for a frame
+ *
+ * return true if there is a packet ready to read
+ *
+ * nic->packet should contain data on return
+ * nic->packetlen should contain length of data
+ *
+ */
+static int virtnet_poll(struct nic *nic, int retrieve)
+{
+ unsigned int len;
+ u16 token;
+ struct virtio_net_hdr *hdr;
+
+ if (!vring_more_used(RX_INDEX))
+ return 0;
+
+ if (!retrieve)
+ return 1;
+
+ token = vring_get_buf(RX_INDEX, &len);
+
+ BUG_ON(len > sizeof(struct virtio_net_hdr) + ETH_FRAME_LEN);
+
+ hdr = &rx_hdr[token]; /* FIXME: check flags */
+ len -= sizeof(struct virtio_net_hdr);
+
+ nic->packetlen = len;
+ memcpy(nic->packet, (char *)rx_buffer[token], nic->packetlen);
+
+ /* add buffer to desc */
+
+ vring_add_buf(RX_INDEX, token, 0);
+ vring_kick(nic, RX_INDEX, 1);
+
+ return 1;
+}
+
+/*
+ *
+ * virtnet_transmit
+ *
+ * Transmit a frame
+ *
+ */
+
+static void virtnet_transmit(struct nic *nic, const char *destaddr,
+ unsigned int type, unsigned int len, const char *data)
+{
+ /*
+ * from http://www.etherboot.org/wiki/dev/devmanual :
+ * "You do not need more than one transmit buffer."
+ */
+
+ /* FIXME: initialize header according to vp_get_features() */
+
+ tx_virtio_hdr.flags = 0;
+ tx_virtio_hdr.csum_offset = 0;
+ tx_virtio_hdr.csum_start = 0;
+ tx_virtio_hdr.gso_type = VIRTIO_NET_HDR_GSO_NONE;
+ tx_virtio_hdr.gso_size = 0;
+ tx_virtio_hdr.hdr_len = 0;
+
+ /* add ethernet frame into vring */
+
+ BUG_ON(len > sizeof(tx_eth_frame.data));
+
+ memcpy(tx_eth_frame.hdr.dst_addr, destaddr, ETH_ALEN);
+ memcpy(tx_eth_frame.hdr.src_addr, nic->node_addr, ETH_ALEN);
+ tx_eth_frame.hdr.type = htons(type);
+ memcpy(tx_eth_frame.data, data, len);
+
+ vring_add_buf(TX_INDEX, 0, 0);
+
+ /*
+ * http://www.etherboot.org/wiki/dev/devmanual
+ *
+ * "You should ensure the packet is fully transmitted
+ * before returning from this routine"
+ */
+
+ while (vring_more_used(TX_INDEX)) {
+ mb();
+ udelay(10);
+ }
+
+ vring_kick(nic, TX_INDEX, 1);
+
+ /* free desc */
+
+ (void)vring_get_buf(TX_INDEX, NULL);
+}
+
+static void virtnet_irq(struct nic *nic __unused, irq_action_t action)
+{
+ switch ( action ) {
+ case DISABLE :
+ vring_disable_cb(RX_INDEX);
+ vring_disable_cb(TX_INDEX);
+ break;
+ case ENABLE :
+ vring_enable_cb(RX_INDEX);
+ vring_enable_cb(TX_INDEX);
+ break;
+ case FORCE :
+ break;
+ }
+}
+
+static void provide_buffers(struct nic *nic)
+{
+ int i;
+
+ for (i = 0; i < RX_BUF_NB; i++)
+ vring_add_buf(RX_INDEX, i, i);
+
+ /* nofify */
+
+ vring_kick(nic, RX_INDEX, i);
+}
+
+static struct nic_operations virtnet_operations = {
+ .connect = dummy_connect,
+ .poll = virtnet_poll,
+ .transmit = virtnet_transmit,
+ .irq = virtnet_irq,
+};
+
+/*
+ * virtnet_probe
+ *
+ * Look for a virtio network adapter
+ *
+ */
+
+static int virtnet_probe(struct nic *nic, struct pci_device *pci)
+{
+ u32 features;
+ int i;
+
+ /* Mask the bit that says "this is an io addr" */
+
+ nic->ioaddr = pci->ioaddr & ~3;
+
+ /* Copy IRQ from PCI information */
+
+ nic->irqno = pci->irq;
+
+ printf("I/O address 0x%08x, IRQ #%d\n", nic->ioaddr, nic->irqno);
+
+ adjust_pci_device(pci);
+
+ vp_reset(nic);
+
+ features = vp_get_features(nic);
+ if (features & (1 << VIRTIO_NET_F_MAC)) {
+ vp_get(nic, offsetof(struct virtio_net_config, mac),
+ nic->node_addr, ETH_ALEN);
+ printf("MAC address ");
+ for (i = 0; i < ETH_ALEN; i++) {
+ printf("%02x%c", nic->node_addr[i],
+ (i == ETH_ALEN - 1) ? '\n' : ':');
+ }
+ }
+
+ /* initialize emit/receive queue */
+
+ for (i = 0; i < QUEUE_NB; i++) {
+ free_head[i] = 0;
+ last_used_idx[i] = 0;
+ memset((char*)&queue[i], 0, sizeof(queue[i]));
+ if (vp_find_vq(nic, i) == -1)
+ printf("Cannot register queue #%d\n", i);
+ }
+
+ /* provide some receive buffers */
+
+ provide_buffers(nic);
+
+ /* define NIC interface */
+
+ nic->nic_op = &virtnet_operations;
+
+ /* driver is ready */
+
+ vp_set_features(nic, features & (1 << VIRTIO_NET_F_MAC));
+ vp_set_status(nic, VIRTIO_CONFIG_S_DRIVER | VIRTIO_CONFIG_S_DRIVER_OK);
+
+ return 1;
+}
+
+static struct pci_device_id virtnet_nics[] = {
+PCI_ROM(0x1af4, 0x1000, "virtio-net", "Virtio Network Interface"),
+};
+
+PCI_DRIVER ( virtnet_driver, virtnet_nics, PCI_NO_CLASS );
+
+DRIVER ( "VIRTIO-NET", nic_driver, pci_driver, virtnet_driver,
+ virtnet_probe, virtnet_disable );
diff --git a/gpxe/src/drivers/net/virtio-net.h b/gpxe/src/drivers/net/virtio-net.h
new file mode 100644
index 00000000..3abef28e
--- /dev/null
+++ b/gpxe/src/drivers/net/virtio-net.h
@@ -0,0 +1,44 @@
+#ifndef _VIRTIO_NET_H_
+# define _VIRTIO_NET_H_
+
+/* The feature bitmap for virtio net */
+#define VIRTIO_NET_F_CSUM 0 /* Host handles pkts w/ partial csum */
+#define VIRTIO_NET_F_GUEST_CSUM 1 /* Guest handles pkts w/ partial csum */
+#define VIRTIO_NET_F_MAC 5 /* Host has given MAC address. */
+#define VIRTIO_NET_F_GSO 6 /* Host handles pkts w/ any GSO type */
+#define VIRTIO_NET_F_GUEST_TSO4 7 /* Guest can handle TSOv4 in. */
+#define VIRTIO_NET_F_GUEST_TSO6 8 /* Guest can handle TSOv6 in. */
+#define VIRTIO_NET_F_GUEST_ECN 9 /* Guest can handle TSO[6] w/ ECN in. */
+#define VIRTIO_NET_F_GUEST_UFO 10 /* Guest can handle UFO in. */
+#define VIRTIO_NET_F_HOST_TSO4 11 /* Host can handle TSOv4 in. */
+#define VIRTIO_NET_F_HOST_TSO6 12 /* Host can handle TSOv6 in. */
+#define VIRTIO_NET_F_HOST_ECN 13 /* Host can handle TSO[6] w/ ECN in. */
+#define VIRTIO_NET_F_HOST_UFO 14 /* Host can handle UFO in. */
+
+struct virtio_net_config
+{
+ /* The config defining mac address (if VIRTIO_NET_F_MAC) */
+ u8 mac[6];
+} __attribute__((packed));
+
+/* This is the first element of the scatter-gather list. If you don't
+ * specify GSO or CSUM features, you can simply ignore the header. */
+
+struct virtio_net_hdr
+{
+#define VIRTIO_NET_HDR_F_NEEDS_CSUM 1 // Use csum_start, csum_offset
+ uint8_t flags;
+#define VIRTIO_NET_HDR_GSO_NONE 0 // Not a GSO frame
+#define VIRTIO_NET_HDR_GSO_TCPV4 1 // GSO frame, IPv4 TCP (TSO)
+/* FIXME: Do we need this? If they said they can handle ECN, do they care? */
+#define VIRTIO_NET_HDR_GSO_TCPV4_ECN 2 // GSO frame, IPv4 TCP w/ ECN
+#define VIRTIO_NET_HDR_GSO_UDP 3 // GSO frame, IPv4 UDP (UFO)
+#define VIRTIO_NET_HDR_GSO_TCPV6 4 // GSO frame, IPv6 TCP
+#define VIRTIO_NET_HDR_GSO_ECN 0x80 // TCP has ECN set
+ uint8_t gso_type;
+ uint16_t hdr_len;
+ uint16_t gso_size;
+ uint16_t csum_start;
+ uint16_t csum_offset;
+};
+#endif /* _VIRTIO_NET_H_ */
diff --git a/gpxe/src/drivers/net/virtio-pci.h b/gpxe/src/drivers/net/virtio-pci.h
new file mode 100644
index 00000000..ba0604d5
--- /dev/null
+++ b/gpxe/src/drivers/net/virtio-pci.h
@@ -0,0 +1,94 @@
+#ifndef _VIRTIO_PCI_H_
+# define _VIRTIO_PCI_H_
+
+/* A 32-bit r/o bitmask of the features supported by the host */
+#define VIRTIO_PCI_HOST_FEATURES 0
+
+/* A 32-bit r/w bitmask of features activated by the guest */
+#define VIRTIO_PCI_GUEST_FEATURES 4
+
+/* A 32-bit r/w PFN for the currently selected queue */
+#define VIRTIO_PCI_QUEUE_PFN 8
+
+/* A 16-bit r/o queue size for the currently selected queue */
+#define VIRTIO_PCI_QUEUE_NUM 12
+
+/* A 16-bit r/w queue selector */
+#define VIRTIO_PCI_QUEUE_SEL 14
+
+/* A 16-bit r/w queue notifier */
+#define VIRTIO_PCI_QUEUE_NOTIFY 16
+
+/* An 8-bit device status register. */
+#define VIRTIO_PCI_STATUS 18
+
+/* An 8-bit r/o interrupt status register. Reading the value will return the
+ * current contents of the ISR and will also clear it. This is effectively
+ * a read-and-acknowledge. */
+#define VIRTIO_PCI_ISR 19
+
+/* The bit of the ISR which indicates a device configuration change. */
+#define VIRTIO_PCI_ISR_CONFIG 0x2
+
+/* The remaining space is defined by each driver as the per-driver
+ * configuration space */
+#define VIRTIO_PCI_CONFIG 20
+
+/* Virtio ABI version, this must match exactly */
+#define VIRTIO_PCI_ABI_VERSION 0
+
+static inline u32 vp_get_features(struct nic *nic)
+{
+ return inl(nic->ioaddr + VIRTIO_PCI_HOST_FEATURES);
+}
+
+static inline void vp_set_features(struct nic *nic, u32 features)
+{
+ outl(features, nic->ioaddr + VIRTIO_PCI_GUEST_FEATURES);
+}
+
+static inline void vp_get(struct nic *nic, unsigned offset,
+ void *buf, unsigned len)
+{
+ u8 *ptr = buf;
+ unsigned i;
+
+ for (i = 0; i < len; i++)
+ ptr[i] = inb(nic->ioaddr + VIRTIO_PCI_CONFIG + offset + i);
+}
+
+static inline u8 vp_get_status(struct nic *nic)
+{
+ return inb(nic->ioaddr + VIRTIO_PCI_STATUS);
+}
+
+static inline void vp_set_status(struct nic *nic, u8 status)
+{
+ if (status == 0) /* reset */
+ return;
+ outb(status, nic->ioaddr + VIRTIO_PCI_STATUS);
+}
+
+
+static inline void vp_reset(struct nic *nic)
+{
+ outb(0, nic->ioaddr + VIRTIO_PCI_STATUS);
+ (void)inb(nic->ioaddr + VIRTIO_PCI_ISR);
+}
+
+static inline void vp_notify(struct nic *nic, int queue_index)
+{
+ outw(queue_index, nic->ioaddr + VIRTIO_PCI_QUEUE_NOTIFY);
+}
+
+static inline void vp_del_vq(struct nic *nic, int queue_index)
+{
+ /* select the queue */
+
+ outw(queue_index, nic->ioaddr + VIRTIO_PCI_QUEUE_SEL);
+
+ /* deactivate the queue */
+
+ outl(0, nic->ioaddr + VIRTIO_PCI_QUEUE_PFN);
+}
+#endif /* _VIRTIO_PCI_H_ */
diff --git a/gpxe/src/drivers/net/virtio-ring.h b/gpxe/src/drivers/net/virtio-ring.h
new file mode 100644
index 00000000..33060b11
--- /dev/null
+++ b/gpxe/src/drivers/net/virtio-ring.h
@@ -0,0 +1,93 @@
+#ifndef _VIRTIO_RING_H_
+# define _VIRTIO_RING_H_
+#define PAGE_SHIFT (12)
+#define PAGE_SIZE (1<<PAGE_SHIFT)
+#define PAGE_MASK (PAGE_SIZE-1)
+
+/* Status byte for guest to report progress, and synchronize features. */
+/* We have seen device and processed generic fields (VIRTIO_CONFIG_F_VIRTIO) */
+#define VIRTIO_CONFIG_S_ACKNOWLEDGE 1
+/* We have found a driver for the device. */
+#define VIRTIO_CONFIG_S_DRIVER 2
+/* Driver has used its parts of the config, and is happy */
+#define VIRTIO_CONFIG_S_DRIVER_OK 4
+/* We've given up on this device. */
+#define VIRTIO_CONFIG_S_FAILED 0x80
+
+#define MAX_QUEUE_NUM (512)
+
+#define VRING_DESC_F_NEXT 1
+#define VRING_DESC_F_WRITE 2
+
+#define VRING_AVAIL_F_NO_INTERRUPT 1
+
+#define VRING_USED_F_NO_NOTIFY 1
+
+struct vring_desc
+{
+ u64 addr;
+ u32 len;
+ u16 flags;
+ u16 next;
+};
+
+struct vring_avail
+{
+ u16 flags;
+ u16 idx;
+ u16 ring[0];
+};
+
+struct vring_used_elem
+{
+ u32 id;
+ u32 len;
+};
+
+struct vring_used
+{
+ u16 flags;
+ u16 idx;
+ struct vring_used_elem ring[];
+};
+
+struct vring {
+ unsigned int num;
+ struct vring_desc *desc;
+ struct vring_avail *avail;
+ struct vring_used *used;
+};
+
+static inline void vring_init(struct vring *vr,
+ unsigned int num, unsigned char *queue)
+{
+ unsigned int i;
+ unsigned long pa;
+
+ vr->num = num;
+
+ /* physical address of desc must be page aligned */
+
+ pa = virt_to_phys(queue);
+ pa = (pa + PAGE_MASK) & ~PAGE_MASK;
+ vr->desc = phys_to_virt(pa);
+
+ vr->avail = (struct vring_avail *)&vr->desc[num];
+
+ /* physical address of used must be page aligned */
+
+ pa = virt_to_phys(&vr->avail->ring[num]);
+ pa = (pa + PAGE_MASK) & ~PAGE_MASK;
+ vr->used = phys_to_virt(pa);
+
+ for (i = 0; i < num - 1; i++)
+ vr->desc[i].next = i + 1;
+ vr->desc[i].next = 0;
+}
+
+#define vring_size(num) \
+ (((((sizeof(struct vring_desc) * num) + \
+ (sizeof(struct vring_avail) + sizeof(u16) * num)) \
+ + PAGE_MASK) & ~PAGE_MASK) + \
+ (sizeof(struct vring_used) + sizeof(struct vring_used_elem) * num))
+#endif /* _VIRTIO_RING_H_ */
diff --git a/gpxe/src/util/Option/ROM.pm b/gpxe/src/util/Option/ROM.pm
new file mode 100644
index 00000000..f5c33f8a
--- /dev/null
+++ b/gpxe/src/util/Option/ROM.pm
@@ -0,0 +1,459 @@
+package Option::ROM;
+
+# Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of the
+# License, or any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+=head1 NAME
+
+Option::ROM - Option ROM manipulation
+
+=head1 SYNOPSIS
+
+ use Option::ROM;
+
+ # Load a ROM image
+ my $rom = new Option::ROM;
+ $rom->load ( "rtl8139.rom" );
+
+ # Modify the PCI device ID
+ $rom->pci_header->{device_id} = 0x1234;
+ $rom->fix_checksum();
+
+ # Write ROM image out to a new file
+ $rom->save ( "rtl8139-modified.rom" );
+
+=head1 DESCRIPTION
+
+C<Option::ROM> provides a mechanism for manipulating Option ROM
+images.
+
+=head1 METHODS
+
+=cut
+
+##############################################################################
+#
+# Option::ROM::Fields
+#
+##############################################################################
+
+package Option::ROM::Fields;
+
+use strict;
+use warnings;
+use Carp;
+use bytes;
+
+sub TIEHASH {
+ my $class = shift;
+ my $self = shift;
+
+ bless $self, $class;
+ return $self;
+}
+
+sub FETCH {
+ my $self = shift;
+ my $key = shift;
+
+ return undef unless $self->EXISTS ( $key );
+ my $raw = substr ( ${$self->{data}},
+ ( $self->{offset} + $self->{fields}->{$key}->{offset} ),
+ $self->{fields}->{$key}->{length} );
+ return unpack ( $self->{fields}->{$key}->{pack}, $raw );
+}
+
+sub STORE {
+ my $self = shift;
+ my $key = shift;
+ my $value = shift;
+
+ croak "Nonexistent field \"$key\"" unless $self->EXISTS ( $key );
+ my $raw = pack ( $self->{fields}->{$key}->{pack}, $value );
+ substr ( ${$self->{data}},
+ ( $self->{offset} + $self->{fields}->{$key}->{offset} ),
+ $self->{fields}->{$key}->{length} ) = $raw;
+}
+
+sub DELETE {
+ my $self = shift;
+ my $key = shift;
+
+ $self->STORE ( $key, 0 );
+}
+
+sub CLEAR {
+ my $self = shift;
+
+ foreach my $key ( keys %{$self->{fields}} ) {
+ $self->DELETE ( $key );
+ }
+}
+
+sub EXISTS {
+ my $self = shift;
+ my $key = shift;
+
+ return ( exists $self->{fields}->{$key} &&
+ ( ( $self->{fields}->{$key}->{offset} +
+ $self->{fields}->{$key}->{length} ) <= $self->{length} ) );
+}
+
+sub FIRSTKEY {
+ my $self = shift;
+
+ keys %{$self->{fields}};
+ return each %{$self->{fields}};
+}
+
+sub NEXTKEY {
+ my $self = shift;
+ my $lastkey = shift;
+
+ return each %{$self->{fields}};
+}
+
+sub SCALAR {
+ my $self = shift;
+
+ return 1;
+}
+
+sub UNTIE {
+ my $self = shift;
+}
+
+sub DESTROY {
+ my $self = shift;
+}
+
+sub checksum {
+ my $self = shift;
+
+ my $raw = substr ( ${$self->{data}}, $self->{offset}, $self->{length} );
+ return unpack ( "%8C*", $raw );
+}
+
+##############################################################################
+#
+# Option::ROM
+#
+##############################################################################
+
+package Option::ROM;
+
+use strict;
+use warnings;
+use Carp;
+use bytes;
+use Exporter 'import';
+
+use constant ROM_SIGNATURE => 0xaa55;
+use constant PCI_SIGNATURE => 'PCIR';
+use constant PNP_SIGNATURE => '$PnP';
+
+our @EXPORT_OK = qw ( ROM_SIGNATURE PCI_SIGNATURE PNP_SIGNATURE );
+our %EXPORT_TAGS = ( all => [ @EXPORT_OK ] );
+
+=pod
+
+=item C<< new () >>
+
+Construct a new C<Option::ROM> object.
+
+=cut
+
+sub new {
+ my $class = shift;
+
+ my $hash = {};
+ tie %$hash, "Option::ROM::Fields", {
+ data => undef,
+ offset => 0x00,
+ length => 0x20,
+ fields => {
+ signature => { offset => 0x00, length => 0x02, pack => "S" },
+ length => { offset => 0x02, length => 0x01, pack => "C" },
+ checksum => { offset => 0x06, length => 0x01, pack => "C" },
+ undi_header => { offset => 0x16, length => 0x02, pack => "S" },
+ pci_header => { offset => 0x18, length => 0x02, pack => "S" },
+ pnp_header => { offset => 0x1a, length => 0x02, pack => "S" },
+ },
+ };
+ bless $hash, $class;
+ return $hash;
+}
+
+=pod
+
+=item C<< load ( $filename ) >>
+
+Load option ROM contents from the file C<$filename>.
+
+=cut
+
+sub load {
+ my $hash = shift;
+ my $self = tied(%$hash);
+ my $filename = shift;
+
+ $self->{filename} = $filename;
+
+ open my $fh, "<$filename"
+ or croak "Cannot open $filename for reading: $!";
+ read $fh, my $data, ( 128 * 1024 ); # 128kB is theoretical max size
+ $self->{data} = \$data;
+ close $fh;
+}
+
+=pod
+
+=item C<< save ( [ $filename ] ) >>
+
+Write the ROM data back out to the file C<$filename>. If C<$filename>
+is omitted, the file used in the call to C<load()> will be used.
+
+=cut
+
+sub save {
+ my $hash = shift;
+ my $self = tied(%$hash);
+ my $filename = shift;
+
+ $filename ||= $self->{filename};
+
+ open my $fh, ">$filename"
+ or croak "Cannot open $filename for writing: $!";
+ print $fh ${$self->{data}};
+ close $fh;
+}
+
+=pod
+
+=item C<< length () >>
+
+Length of option ROM data. This is the length of the file, not the
+length from the ROM header length field.
+
+=cut
+
+sub length {
+ my $hash = shift;
+ my $self = tied(%$hash);
+
+ return length ${$self->{data}};
+}
+
+=pod
+
+=item C<< pci_header () >>
+
+Return a C<Option::ROM::PCI> object representing the ROM's PCI header,
+if present.
+
+=cut
+
+sub pci_header {
+ my $hash = shift;
+ my $self = tied(%$hash);
+
+ my $offset = $hash->{pci_header};
+ return undef unless $offset != 0;
+
+ return Option::ROM::PCI->new ( $self->{data}, $offset );
+}
+
+=pod
+
+=item C<< pnp_header () >>
+
+Return a C<Option::ROM::PnP> object representing the ROM's PnP header,
+if present.
+
+=cut
+
+sub pnp_header {
+ my $hash = shift;
+ my $self = tied(%$hash);
+
+ my $offset = $hash->{pnp_header};
+ return undef unless $offset != 0;
+
+ return Option::ROM::PnP->new ( $self->{data}, $offset );
+}
+
+=pod
+
+=item C<< checksum () >>
+
+Calculate the byte checksum of the ROM.
+
+=cut
+
+sub checksum {
+ my $hash = shift;
+ my $self = tied(%$hash);
+
+ return unpack ( "%8C*", ${$self->{data}} );
+}
+
+=pod
+
+=item C<< fix_checksum () >>
+
+Fix the byte checksum of the ROM.
+
+=cut
+
+sub fix_checksum {
+ my $hash = shift;
+ my $self = tied(%$hash);
+
+ $hash->{checksum} = ( ( $hash->{checksum} - $hash->checksum() ) & 0xff );
+}
+
+##############################################################################
+#
+# Option::ROM::PCI
+#
+##############################################################################
+
+package Option::ROM::PCI;
+
+use strict;
+use warnings;
+use Carp;
+use bytes;
+
+sub new {
+ my $class = shift;
+ my $data = shift;
+ my $offset = shift;
+
+ my $hash = {};
+ tie %$hash, "Option::ROM::Fields", {
+ data => $data,
+ offset => $offset,
+ length => 0x0c,
+ fields => {
+ signature => { offset => 0x00, length => 0x04, pack => "a4" },
+ vendor_id => { offset => 0x04, length => 0x02, pack => "S" },
+ device_id => { offset => 0x06, length => 0x02, pack => "S" },
+ device_list => { offset => 0x08, length => 0x02, pack => "S" },
+ struct_length => { offset => 0x0a, length => 0x02, pack => "S" },
+ struct_revision =>{ offset => 0x0c, length => 0x01, pack => "C" },
+ base_class => { offset => 0x0d, length => 0x01, pack => "C" },
+ sub_class => { offset => 0x0e, length => 0x01, pack => "C" },
+ prog_intf => { offset => 0x0f, length => 0x01, pack => "C" },
+ image_length => { offset => 0x10, length => 0x02, pack => "S" },
+ revision => { offset => 0x12, length => 0x02, pack => "S" },
+ code_type => { offset => 0x14, length => 0x01, pack => "C" },
+ last_image => { offset => 0x15, length => 0x01, pack => "C" },
+ runtime_length => { offset => 0x16, length => 0x02, pack => "S" },
+ conf_header => { offset => 0x18, length => 0x02, pack => "S" },
+ clp_entry => { offset => 0x1a, length => 0x02, pack => "S" },
+ },
+ };
+ bless $hash, $class;
+
+ # Retrieve true length of structure
+ my $self = tied ( %$hash );
+ $self->{length} = $hash->{struct_length};
+
+ return $hash;
+}
+
+##############################################################################
+#
+# Option::ROM::PnP
+#
+##############################################################################
+
+package Option::ROM::PnP;
+
+use strict;
+use warnings;
+use Carp;
+use bytes;
+
+sub new {
+ my $class = shift;
+ my $data = shift;
+ my $offset = shift;
+
+ my $hash = {};
+ tie %$hash, "Option::ROM::Fields", {
+ data => $data,
+ offset => $offset,
+ length => 0x06,
+ fields => {
+ signature => { offset => 0x00, length => 0x04, pack => "a4" },
+ struct_revision =>{ offset => 0x04, length => 0x01, pack => "C" },
+ struct_length => { offset => 0x05, length => 0x01, pack => "C" },
+ checksum => { offset => 0x09, length => 0x01, pack => "C" },
+ manufacturer => { offset => 0x0e, length => 0x02, pack => "S" },
+ product => { offset => 0x10, length => 0x02, pack => "S" },
+ bcv => { offset => 0x16, length => 0x02, pack => "S" },
+ bdv => { offset => 0x18, length => 0x02, pack => "S" },
+ bev => { offset => 0x1a, length => 0x02, pack => "S" },
+ },
+ };
+ bless $hash, $class;
+
+ # Retrieve true length of structure
+ my $self = tied ( %$hash );
+ $self->{length} = ( $hash->{struct_length} * 16 );
+
+ return $hash;
+}
+
+sub checksum {
+ my $hash = shift;
+ my $self = tied(%$hash);
+
+ return $self->checksum();
+}
+
+sub fix_checksum {
+ my $hash = shift;
+ my $self = tied(%$hash);
+
+ $hash->{checksum} = ( ( $hash->{checksum} - $hash->checksum() ) & 0xff );
+}
+
+sub manufacturer {
+ my $hash = shift;
+ my $self = tied(%$hash);
+
+ my $manufacturer = $hash->{manufacturer};
+ return undef unless $manufacturer;
+
+ my $raw = substr ( ${$self->{data}}, $manufacturer );
+ return unpack ( "Z*", $raw );
+}
+
+sub product {
+ my $hash = shift;
+ my $self = tied(%$hash);
+
+ my $product = $hash->{product};
+ return undef unless $product;
+
+ my $raw = substr ( ${$self->{data}}, $product );
+ return unpack ( "Z*", $raw );
+}
+
+1;
diff --git a/gpxe/src/util/mergerom.pl b/gpxe/src/util/mergerom.pl
new file mode 100644
index 00000000..ce1befb7
--- /dev/null
+++ b/gpxe/src/util/mergerom.pl
@@ -0,0 +1,80 @@
+#!/usr/bin/perl -w
+#
+# Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of the
+# License, or any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+use strict;
+use warnings;
+
+use FindBin;
+use lib "$FindBin::Bin";
+use Option::ROM qw ( :all );
+
+my @romfiles = @ARGV;
+my @roms = map { my $rom = new Option::ROM; $rom->load($_); $rom } @romfiles;
+
+my $baserom = shift @roms;
+my $offset = $baserom->length;
+
+foreach my $rom ( @roms ) {
+
+ # Update base length
+ $baserom->{length} += $rom->{length};
+
+ # Update PCI header, if present in both
+ my $baserom_pci = $baserom->pci_header;
+ my $rom_pci = $rom->pci_header;
+ if ( $baserom_pci && $rom_pci ) {
+
+ # Update PCI lengths
+ $baserom_pci->{image_length} += $rom_pci->{image_length};
+ if ( exists $baserom_pci->{runtime_length} ) {
+ if ( exists $rom_pci->{runtime_length} ) {
+ $baserom_pci->{runtime_length} += $rom_pci->{runtime_length};
+ } else {
+ $baserom_pci->{runtime_length} += $rom_pci->{image_length};
+ }
+ }
+
+ # Merge CLP entry point
+ if ( exists ( $baserom_pci->{clp_entry} ) &&
+ exists ( $rom_pci->{clp_entry} ) ) {
+ $baserom_pci->{clp_entry} = ( $offset + $rom_pci->{clp_entry} )
+ if $rom_pci->{clp_entry};
+ }
+ }
+
+ # Update PnP header, if present in both
+ my $baserom_pnp = $baserom->pnp_header;
+ my $rom_pnp = $rom->pnp_header;
+ if ( $baserom_pnp && $rom_pnp ) {
+ $baserom_pnp->{bcv} = ( $offset + $rom_pnp->{bcv} ) if $rom_pnp->{bcv};
+ $baserom_pnp->{bdv} = ( $offset + $rom_pnp->{bdv} ) if $rom_pnp->{bdv};
+ $baserom_pnp->{bev} = ( $offset + $rom_pnp->{bev} ) if $rom_pnp->{bev};
+ }
+
+ # Fix checksum for this ROM segment
+ $rom->fix_checksum();
+
+ $offset += $rom->length;
+}
+
+$baserom->pnp_header->fix_checksum() if $baserom->pnp_header;
+$baserom->fix_checksum();
+$baserom->save ( "-" );
+foreach my $rom ( @roms ) {
+ $rom->save ( "-" );
+}