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authorH. Peter Anvin <hpa@zytor.com>2008-09-07 22:41:29 -0700
committerH. Peter Anvin <hpa@zytor.com>2008-09-07 22:41:29 -0700
commitc14f98ab23dbc912aa9db26d86434a4d2bd80a5f (patch)
treea0b1d6fd48ad30f8af19a88d11a8f4e61cebf52f /gpxe/src/drivers/net
parent3506d7fb195922b04c941650b1512440bdcc89e4 (diff)
downloadsyslinux.git-c14f98ab23dbc912aa9db26d86434a4d2bd80a5f.tar.gz
syslinux.git-c14f98ab23dbc912aa9db26d86434a4d2bd80a5f.tar.xz
syslinux.git-c14f98ab23dbc912aa9db26d86434a4d2bd80a5f.zip
gPXE: update gPXE to current git
Update gPXE to current git. gpxe-for-syslinux e3ef2094cfa26f874c5f8dbd687eb311830efcf0 gpxe main tree 8223084afc206000312611a3fcfa30a28500d1a3
Diffstat (limited to 'gpxe/src/drivers/net')
-rw-r--r--gpxe/src/drivers/net/forcedeth.c4
-rw-r--r--gpxe/src/drivers/net/ipoib.c43
-rw-r--r--gpxe/src/drivers/net/phantom/phantom.c19
-rw-r--r--gpxe/src/drivers/net/phantom/phantom.h1
-rw-r--r--gpxe/src/drivers/net/tg3.c73
-rw-r--r--gpxe/src/drivers/net/tg3.h18
6 files changed, 108 insertions, 50 deletions
diff --git a/gpxe/src/drivers/net/forcedeth.c b/gpxe/src/drivers/net/forcedeth.c
index f6195885..54fadbd7 100644
--- a/gpxe/src/drivers/net/forcedeth.c
+++ b/gpxe/src/drivers/net/forcedeth.c
@@ -82,6 +82,7 @@ static unsigned long BASE;
#define PCI_DEVICE_ID_NVIDIA_NVENET_9 0x0057
#define PCI_DEVICE_ID_NVIDIA_NVENET_10 0x0037
#define PCI_DEVICE_ID_NVIDIA_NVENET_11 0x0038
+#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373
/*
@@ -1338,6 +1339,8 @@ static int forcedeth_probe ( struct nic *nic, struct pci_device *pci ) {
else
np->tx_flags |= NV_TX2_LASTPACKET1;
break;
+ case 0x0373:
+ /* Fall Through */
case 0x0086:
/* Fall Through */
case 0x008c:
@@ -1420,6 +1423,7 @@ PCI_ROM(0x10de, 0x0056, "nforce8", "nForce NVENET_8 Ethernet Controller"),
PCI_ROM(0x10de, 0x0057, "nforce9", "nForce NVENET_9 Ethernet Controller"),
PCI_ROM(0x10de, 0x0037, "nforce10", "nForce NVENET_10 Ethernet Controller"),
PCI_ROM(0x10de, 0x0038, "nforce11", "nForce NVENET_11 Ethernet Controller"),
+PCI_ROM(0x10de, 0x0373, "nforce15", "nForce NVENET_15 Ethernet Controller")
};
PCI_DRIVER ( forcedeth_driver, forcedeth_nics, PCI_NO_CLASS );
diff --git a/gpxe/src/drivers/net/ipoib.c b/gpxe/src/drivers/net/ipoib.c
index e3baa14f..16b2a0c8 100644
--- a/gpxe/src/drivers/net/ipoib.c
+++ b/gpxe/src/drivers/net/ipoib.c
@@ -153,18 +153,17 @@ static struct ipoib_mac ipoib_broadcast = {
};
/**
- * Transmit IPoIB packet
+ * Add IPoIB link-layer header
*
* @v iobuf I/O buffer
* @v netdev Network device
* @v net_protocol Network-layer protocol
* @v ll_dest Link-layer destination address
- *
- * Prepends the IPoIB link-layer header and transmits the packet.
*/
-static int ipoib_tx ( struct io_buffer *iobuf, struct net_device *netdev,
- struct net_protocol *net_protocol,
- const void *ll_dest ) {
+static int ipoib_push ( struct io_buffer *iobuf,
+ struct net_device *netdev __unused,
+ struct net_protocol *net_protocol,
+ const void *ll_dest ) {
struct ipoib_hdr *ipoib_hdr =
iob_push ( iobuf, sizeof ( *ipoib_hdr ) );
@@ -174,36 +173,38 @@ static int ipoib_tx ( struct io_buffer *iobuf, struct net_device *netdev,
ipoib_hdr->real.proto = net_protocol->net_proto;
ipoib_hdr->real.reserved = 0;
- /* Hand off to network device */
- return netdev_tx ( netdev, iobuf );
+ return 0;
}
/**
- * Process received IPoIB packet
- *
- * @v iobuf I/O buffer
- * @v netdev Network device
+ * Remove IPoIB link-layer header
*
- * Strips off the IPoIB link-layer header and passes up to the
- * network-layer protocol.
+ * @v iobuf I/O buffer
+ * @v netdev Network device
+ * @v net_proto Network-layer protocol, in network-byte order
+ * @v ll_source Source link-layer address
+ * @ret rc Return status code
*/
-static int ipoib_rx ( struct io_buffer *iobuf, struct net_device *netdev ) {
+static int ipoib_pull ( struct io_buffer *iobuf,
+ struct net_device *netdev __unused,
+ uint16_t *net_proto, const void **ll_source ) {
struct ipoib_hdr *ipoib_hdr = iobuf->data;
/* Sanity check */
if ( iob_len ( iobuf ) < sizeof ( *ipoib_hdr ) ) {
DBG ( "IPoIB packet too short for link-layer header\n" );
DBG_HD ( iobuf->data, iob_len ( iobuf ) );
- free_iob ( iobuf );
return -EINVAL;
}
/* Strip off IPoIB header */
iob_pull ( iobuf, sizeof ( *ipoib_hdr ) );
- /* Hand off to network-layer protocol */
- return net_rx ( iobuf, netdev, ipoib_hdr->real.proto,
- &ipoib_hdr->pseudo.peer );
+ /* Fill in required fields */
+ *net_proto = ipoib_hdr->real.proto;
+ *ll_source = &ipoib_hdr->pseudo.peer;
+
+ return 0;
}
/**
@@ -231,8 +232,8 @@ struct ll_protocol ipoib_protocol __ll_protocol = {
.ll_addr_len = IPOIB_ALEN,
.ll_header_len = IPOIB_HLEN,
.ll_broadcast = ( uint8_t * ) &ipoib_broadcast,
- .tx = ipoib_tx,
- .rx = ipoib_rx,
+ .push = ipoib_push,
+ .pull = ipoib_pull,
.ntoa = ipoib_ntoa,
};
diff --git a/gpxe/src/drivers/net/phantom/phantom.c b/gpxe/src/drivers/net/phantom/phantom.c
index 509a7096..5644c96d 100644
--- a/gpxe/src/drivers/net/phantom/phantom.c
+++ b/gpxe/src/drivers/net/phantom/phantom.c
@@ -1554,9 +1554,6 @@ static int phantom_map_crb ( struct phantom_nic *phantom,
unsigned long bar0_start;
unsigned long bar0_size;
- /* CRB window is always in the last 32MB of BAR0 (which may be
- * a 32MB or a 128MB BAR).
- */
bar0_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_0 );
bar0_size = pci_bar_size ( pci, PCI_BASE_ADDRESS_0 );
DBGC ( phantom, "Phantom %p BAR0 is %08lx+%lx\n",
@@ -1711,7 +1708,8 @@ static int phantom_init_cmdpeg ( struct phantom_nic *phantom ) {
UNM_NIC_REG_DUMMY_BUF );
/* Tell the hardware that tuning is complete */
- phantom_writel ( phantom, 1, UNM_ROMUSB_GLB_PEGTUNE_DONE );
+ phantom_writel ( phantom, UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC,
+ UNM_ROMUSB_GLB_PEGTUNE_DONE );
/* Wait for command PEG to finish initialising */
DBGC ( phantom, "Phantom %p initialising command PEG (will take up to "
@@ -1859,6 +1857,19 @@ static int phantom_probe ( struct pci_device *pci,
phantom_port->port = i;
}
+ /* BUG5945 - need to hack PCI config space on P3 B1 silicon.
+ * B2 will have this fixed; remove this hack when B1 is no
+ * longer in use.
+ */
+ for ( i = 0 ; i < 8 ; i++ ) {
+ uint32_t temp;
+ pci->devfn = PCI_DEVFN ( PCI_SLOT ( pci->devfn ), i );
+ pci_read_config_dword ( pci, 0xc8, &temp );
+ pci_read_config_dword ( pci, 0xc8, &temp );
+ pci_write_config_dword ( pci, 0xc8, 0xf1000 );
+ }
+ pci->devfn = PCI_DEVFN ( PCI_SLOT ( pci->devfn ), 0 );
+
/* Allocate dummy DMA buffer and perform initial hardware handshake */
phantom->dma_buf = malloc_dma ( sizeof ( *(phantom->dma_buf) ),
UNM_DMA_BUFFER_ALIGN );
diff --git a/gpxe/src/drivers/net/phantom/phantom.h b/gpxe/src/drivers/net/phantom/phantom.h
index 3c759989..110c1226 100644
--- a/gpxe/src/drivers/net/phantom/phantom.h
+++ b/gpxe/src/drivers/net/phantom/phantom.h
@@ -139,6 +139,7 @@ enum unm_reg_blocks {
#define UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 )
#define UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL
#define UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c )
+#define UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC 0x31
#define UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 )
#define UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 )
diff --git a/gpxe/src/drivers/net/tg3.c b/gpxe/src/drivers/net/tg3.c
index 5d1bf407..82b37fab 100644
--- a/gpxe/src/drivers/net/tg3.c
+++ b/gpxe/src/drivers/net/tg3.c
@@ -1431,7 +1431,8 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit
unsigned int i;
uint32_t val;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
switch(ofs) {
case RCVLSC_MODE:
case DMAC_MODE:
@@ -1439,7 +1440,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit
case BUFMGR_MODE:
case MEMARB_MODE:
/* We can't enable/disable these bits of the
- * 5705, just say success.
+ * 5705 or 5787, just say success.
*/
return 0;
default:
@@ -1470,6 +1471,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit
static int tg3_abort_hw(struct tg3 *tp)
{
int i, err;
+ uint32_t val;
tg3_disable_ints(tp);
@@ -1513,8 +1515,14 @@ static int tg3_abort_hw(struct tg3 *tp)
err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
- tw32(FTQ_RESET, 0xffffffff);
- tw32(FTQ_RESET, 0x00000000);
+ val = tr32(FTQ_RESET);
+ val |= FTQ_RESET_DMA_READ_QUEUE | FTQ_RESET_DMA_HIGH_PRI_READ |
+ FTQ_RESET_SEND_BD_COMPLETION | FTQ_RESET_DMA_WRITE |
+ FTQ_RESET_DMA_HIGH_PRI_WRITE | FTQ_RESET_SEND_DATA_COMPLETION |
+ FTQ_RESET_HOST_COALESCING | FTQ_RESET_MAC_TX |
+ FTQ_RESET_RX_BD_COMPLETE | FTQ_RESET_RX_LIST_PLCMT |
+ FTQ_RESET_RX_DATA_COMPLETION;
+ tw32(FTQ_RESET, val);
err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
@@ -1554,8 +1562,19 @@ static void tg3_chip_reset(struct tg3 *tp)
// Alf: here patched
/* do the reset */
val = GRC_MISC_CFG_CORECLK_RESET;
+ if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
+ if (tr32(0x7e2c) == 0x60) {
+ tw32(0x7e2c, 0x20);
+ }
+ if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
+ tw32(GRC_MISC_CFG, (1 << 29));
+ val |= (1 << 29);
+ }
+ }
+
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
- || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
+ || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)) {
val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
}
@@ -1644,7 +1663,8 @@ static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
udelay(10);
}
if (i >= 100000 &&
- !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
+ !(tp->tg3_flags2 & TG3_FLG2_SUN_5704) &&
+ !(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)) {
printf ( "Firmware will not restart magic=%#lx\n",
val );
return -ENODEV;
@@ -1879,7 +1899,9 @@ static int tg3_setup_hw(struct tg3 *tp)
(65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
/* Initialize MBUF/DESC pool. */
- if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
+ /* Do nothing. */
+ } else if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
(tp->pci_chip_rev_id != CHIPREV_ID_5721)) {
tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
@@ -1976,7 +1998,8 @@ static int tg3_setup_hw(struct tg3 *tp)
TG3_WRITE_SETTINGS(table_all);
tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
virt_to_bus(tp->rx_std));
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
} else {
@@ -1985,10 +2008,11 @@ static int tg3_setup_hw(struct tg3 *tp)
}
- /* There is only one send ring on 5705, no need to explicitly
+ /* There is only one send ring on 5705 and 5787, no need to explicitly
* disable the others.
*/
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) {
/* Clear out send RCB ring in SRAM. */
for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
@@ -2004,10 +2028,11 @@ static int tg3_setup_hw(struct tg3 *tp)
(TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
NIC_SRAM_TX_BUFFER_DESC);
- /* There is only one receive return ring on 5705, no need to explicitly
- * disable the others.
+ /* There is only one receive return ring on 5705 and 5787, no need to
+ * explicitly disable the others.
*/
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) {
for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS,
BDINFO_FLAGS_DISABLED);
@@ -2086,6 +2111,11 @@ static int tg3_setup_hw(struct tg3 *tp)
!(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
val |= WDMAC_MODE_RX_ACCEL;
}
+
+ /* Host coalescing bug fix */
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+ val |= (1 << 29);
+
tw32_carefully(WDMAC_MODE, val);
if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
@@ -2182,7 +2212,8 @@ static int tg3_setup_hw(struct tg3 *tp)
virt_to_bus(tp->hw_stats));
tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
virt_to_bus(tp->hw_status));
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) {
TG3_WRITE_SETTINGS(table_not_5705);
}
}
@@ -2762,15 +2793,9 @@ static int tg3_get_invariants(struct tg3 *tp)
/* determine if it is PCIE system */
// Alf : I have no idea what this is about...
// But it's definitely usefull
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
- val = tr32(TG3PCI_MSI_CAP_ID) ;
- if (((val >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) {
- val = tr32(T3_PCIE_CAPABILITY_ID_REG) ;
- if ((val & 0xff) == T3_PCIE_CAPABILITY_ID) {
- tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS ;
- }
- }
- }
+ val = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
+ if (val)
+ tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
/* Force the chip into D0. */
tg3_set_power_state_0(tp);
@@ -3010,6 +3035,7 @@ static const char * tg3_phy_string(struct tg3 *tp)
case PHY_ID_BCM5705: return "5705";
case PHY_ID_BCM5750: return "5750";
case PHY_ID_BCM5751: return "5751";
+ case PHY_ID_BCM5787: return "5787";
case PHY_ID_BCM8002: return "8002/serdes";
case PHY_ID_SERDES: return "serdes";
default: return "unknown";
@@ -3370,6 +3396,7 @@ PCI_ROM(0x14e4, 0x1659, "tg3-5721", "Broadcom Tigon 3 5721"),
PCI_ROM(0x14e4, 0x165d, "tg3-5705M", "Broadcom Tigon 3 5705M"),
PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2", "Broadcom Tigon 3 5705M_2"),
PCI_ROM(0x14e4, 0x1677, "tg3-5751", "Broadcom Tigon 3 5751"),
+PCI_ROM(0x14e4, 0x167a, "tg3-5754", "Broadcom Tigon 3 5754"),
PCI_ROM(0x14e4, 0x1696, "tg3-5782", "Broadcom Tigon 3 5782"),
PCI_ROM(0x14e4, 0x169c, "tg3-5788", "Broadcom Tigon 3 5788"),
PCI_ROM(0x14e4, 0x169d, "tg3-5789", "Broadcom Tigon 3 5789"),
diff --git a/gpxe/src/drivers/net/tg3.h b/gpxe/src/drivers/net/tg3.h
index 9077f80a..d1c09e03 100644
--- a/gpxe/src/drivers/net/tg3.h
+++ b/gpxe/src/drivers/net/tg3.h
@@ -294,6 +294,7 @@ typedef unsigned long dma_addr_t;
#define ASIC_REV_5704 0x02
#define ASIC_REV_5705 0x03
#define ASIC_REV_5750 0x04
+#define ASIC_REV_5787 0x0b
#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
#define CHIPREV_5700_AX 0x70
#define CHIPREV_5700_BX 0x71
@@ -1273,6 +1274,17 @@ typedef unsigned long dma_addr_t;
/* Flow Through queues */
#define FTQ_RESET 0x00005c00
+#define FTQ_RESET_DMA_READ_QUEUE (1 << 1)
+#define FTQ_RESET_DMA_HIGH_PRI_READ (1 << 2)
+#define FTQ_RESET_SEND_BD_COMPLETION (1 << 4)
+#define FTQ_RESET_DMA_WRITE (1 << 6)
+#define FTQ_RESET_DMA_HIGH_PRI_WRITE (1 << 7)
+#define FTQ_RESET_SEND_DATA_COMPLETION (1 << 9)
+#define FTQ_RESET_HOST_COALESCING (1 << 10)
+#define FTQ_RESET_MAC_TX (1 << 11)
+#define FTQ_RESET_RX_BD_COMPLETE (1 << 13)
+#define FTQ_RESET_RX_LIST_PLCMT (1 << 14)
+#define FTQ_RESET_RX_DATA_COMPLETION (1 << 16)
/* 0x5c04 --> 0x5c10 unused */
#define FTQ_DMA_NORM_READ_CTL 0x00005c10
#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
@@ -2130,7 +2142,8 @@ struct tg3 {
#define PHY_ID_BCM5703 0x60008160
#define PHY_ID_BCM5704 0x60008190
#define PHY_ID_BCM5705 0x600081a0
-#define PHY_ID_BCM5750 0x60008180
+#define PHY_ID_BCM5750 0x60008180
+#define PHY_ID_BCM5787 0xbc050ce0
#define PHY_ID_BCM8002 0x60010140
#define PHY_ID_BCM5751 0x00206180
#define PHY_ID_SERDES 0xfeedbee0
@@ -2157,7 +2170,8 @@ struct tg3 {
((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
(X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
(X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
- (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || (X) == PHY_ID_BCM5751 || \
+ (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
+ (X) == PHY_ID_BCM5751 || (X) == PHY_ID_BCM5787 || \
(X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
unsigned long regs;