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authorH. Peter Anvin <hpa@zytor.com>2009-09-04 17:19:09 -0700
committerH. Peter Anvin <hpa@zytor.com>2009-09-04 17:21:10 -0700
commit779a360023f47def89666923653d3ec59483a036 (patch)
treeaf43a1aa5b239558b1594655dc0a230706a31206 /core
parent96281dc8bf8189add880d8f2bedf104e6517d1f7 (diff)
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core: when enabling serial IRQs, unmask interrupts at the PIC
Some BIOSes only enable interrupts in active use by the BIOS at the PIC, which presumably don't include the serial ports. As such, enable the interrupt lines at the PIC and hope to $DEITY we don't hang due to a stuck interrupt line. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'core')
-rw-r--r--core/serirq.inc25
1 files changed, 25 insertions, 0 deletions
diff --git a/core/serirq.inc b/core/serirq.inc
index 579c42b4..6babacec 100644
--- a/core/serirq.inc
+++ b/core/serirq.inc
@@ -91,6 +91,9 @@ SerialIRQPort dw 0 ; Serial port w IRQ service
SerialHead dw 0 ; Head of serial port rx buffer
SerialTail dw 0 ; Tail of serial port rx buffer
+ section .bss
+IRQMask resw 1 ; PIC IRQ mask status
+
section .text
sirq_install:
@@ -133,6 +136,22 @@ sirq_install:
mov al,1 ; Enable receive interrupt
slow_out dx,al
+ ;
+ ; Enable all ther interupt lines at the PIC. Some BIOSes
+ ; only enable the timer interrupts and other interrupts
+ ; actively in use by the BIOS.
+ ;
+ in al,0xA1 ; Secondary PIC mask register
+ mov ah,al
+ in al,0x21 ; Primary PIC mask register
+ mov [IRQMask],ax
+
+ io_delay
+
+ xor ax,ax ; Remove all interrupt masks
+ out 0x21,al
+ out 0xA1,al
+
popad
ret
@@ -156,6 +175,12 @@ sirq_cleanup_nowipe:
xor ax,ax
slow_out dx,al ; Clear IER
+ ; Restore PIC masks
+ mov ax,[IRQMask]
+ out 0x21,al
+ mov al,ah
+ out 0xA1,al
+
; Restore the original interrupt vectors
mov si,oldirq0
mov di,4*08h