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authorErwan Velu <erwan.velu@free.fr>2009-11-27 10:10:52 +0100
committerErwan Velu <erwan.velu@free.fr>2009-12-04 10:11:14 +0100
commitfef4af4aada7001595a56d287d89f2a9e3cd328b (patch)
tree93fed294dd8074c2d1bbf278fdfe8e3443cf68da /com32
parent0709f91fab7244cef45018d51c33fbe9361a3cc0 (diff)
downloadsyslinux.git-fef4af4aada7001595a56d287d89f2a9e3cd328b.tar.gz
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cpuid: Adding more flags
Impact: sync with linux kernel cpu flags are now in sync with the linux kernel. Too many flags were missing.
Diffstat (limited to 'com32')
-rw-r--r--com32/gplinclude/cpuid.h51
-rw-r--r--com32/gpllib/cpuid.c51
-rw-r--r--com32/include/cpufeature.h56
3 files changed, 156 insertions, 2 deletions
diff --git a/com32/gplinclude/cpuid.h b/com32/gplinclude/cpuid.h
index f85e6ab3..9f463aed 100644
--- a/com32/gplinclude/cpuid.h
+++ b/com32/gplinclude/cpuid.h
@@ -49,6 +49,7 @@ typedef struct {
bool clflsh; /* Supports the CLFLUSH instruction */
bool dts; /* Debug Trace Store */
bool acpi; /* ACPI via MSR */
+ bool pbe; /* Pending Break Enable */
bool mmx; /* Multimedia Extensions */
bool fxsr; /* FXSAVE and FXRSTOR instructions (fast save and restore */
/* of FPU context), and CR4.OSFXSR available */
@@ -61,12 +62,62 @@ typedef struct {
bool mp; /* MP Capable. */
bool nx; /* Execute Disable */
bool mmxext; /* AMD MMX extensions */
+ bool fxsr_opt; /* FXSAVE/FXRSTOR optimizations */
+ bool gbpages; /* "pdpe1gb" GB pages */
+ bool rdtscp; /* RDTSCP */
bool lm; /* Long Mode (x86-64) */
bool nowext; /* AMD 3DNow! extensions */
bool now; /* 3DNow! */
bool smp; /* A smp configuration has been found */
+ bool pni; /* Streaming SIMD Extensions-3 */
+ bool pclmulqd; /* PCLMULQDQ instruction */
+ bool dtes64; /* 64-bit Debug Store */
bool vmx; /* Hardware virtualization */
+ bool smx; /* Safer Mode */
+ bool est; /* Enhanced SpeedStep */
+ bool tm2; /* Thermal Monitor 2 */
+ bool sse3; /* Supplemental SSE-3 */
+ bool cid; /* Context ID */
+ bool fma; /* Fused multiply-add */
+ bool cx16; /* CMPXCHG16B */
+ bool xtpr; /* Send Task Priority Messages */
+ bool pdcm; /* Performance Capabilities */
+ bool dca; /* Direct Cache Access */
+ bool xmm4_1; /* "sse4_1" SSE-4.1 */
+ bool xmm4_2; /* "sse4_2" SSE-4.2 */
+ bool x2apic; /* x2APIC */
+ bool movbe; /* MOVBE instruction */
+ bool popcnt; /* POPCNT instruction */
+ bool aes; /* AES Instruction */
+ bool xsave; /* XSAVE/XRSTOR/XSETBV/XGETBV */
+ bool osxsave; /* XSAVE enabled in the OS */
+ bool avx; /* Advanced Vector Extensions */
+ bool hypervisor; /* Running on a hypervisor */
+ bool ace2; /* Advanced Cryptography Engine v2 */
+ bool ace2_en; /* ACE v2 enabled */
+ bool phe; /* PadLock Hash Engine */
+ bool phe_en; /* PadLock Hash Engine Enabled */
+ bool pmm; /* PadLock Montgomery Multiplier */
+ bool pmm_en; /* PadLock Montgomery Multiplier enabled */
bool svm; /* Secure virtual machine */
+ bool extapic; /* Extended APIC space */
+ bool cr8_legacy; /* CR8 in 32-bit mode */
+ bool abm; /* Advanced bit manipulation */
+ bool sse4a; /* SSE4-A */
+ bool misalignsse; /* Misaligned SSE mode */
+ bool nowprefetch; /* 3DNow prefetch instructions */
+ bool osvw; /* OS Visible Workaround */
+ bool ibs; /* Instruction Based Sampling */
+ bool sse5; /* SSE5 */
+ bool skinit; /* SKINIT/STGI instructions */
+ bool wdt; /* Watchdog Timer */
+ bool ida; /* Intel Dynamic Acceleration */
+ bool arat; /* Always Running APIC Timer */
+ bool tpr_shadow; /* Intel TPR Shadow */
+ bool vnmi; /* Intel Virtual NMI */
+ bool flexpriority; /* Intel FlexPriority */
+ bool ept; /* Intel Extended Page Table */
+ bool vpid; /* Intel Virtual Processor ID */
} s_cpu_flags;
typedef struct {
diff --git a/com32/gpllib/cpuid.c b/com32/gpllib/cpuid.c
index fb69cef6..b24de0a7 100644
--- a/com32/gpllib/cpuid.c
+++ b/com32/gpllib/cpuid.c
@@ -280,6 +280,7 @@ void set_cpu_flags(struct cpuinfo_x86 *c, s_cpu * cpu)
cpu->flags.clflsh = cpu_has(c, X86_FEATURE_CLFLSH);
cpu->flags.dts = cpu_has(c, X86_FEATURE_DTES);
cpu->flags.acpi = cpu_has(c, X86_FEATURE_ACPI);
+ cpu->flags.pbe = cpu_has(c, X86_FEATURE_PBE);
cpu->flags.mmx = cpu_has(c, X86_FEATURE_MMX);
cpu->flags.fxsr = cpu_has(c, X86_FEATURE_FXSR);
cpu->flags.sse = cpu_has(c, X86_FEATURE_XMM);
@@ -291,11 +292,61 @@ void set_cpu_flags(struct cpuinfo_x86 *c, s_cpu * cpu)
cpu->flags.mp = cpu_has(c, X86_FEATURE_MP);
cpu->flags.nx = cpu_has(c, X86_FEATURE_NX);
cpu->flags.mmxext = cpu_has(c, X86_FEATURE_MMXEXT);
+ cpu->flags.fxsr_opt = cpu_has(c, X86_FEATURE_FXSR_OPT);
+ cpu->flags.gbpages = cpu_has(c, X86_FEATURE_GBPAGES);
+ cpu->flags.rdtscp = cpu_has(c, X86_FEATURE_RDTSCP);
cpu->flags.lm = cpu_has(c, X86_FEATURE_LM);
cpu->flags.nowext = cpu_has(c, X86_FEATURE_3DNOWEXT);
cpu->flags.now = cpu_has(c, X86_FEATURE_3DNOW);
cpu->flags.smp = find_smp_config();
+ cpu->flags.pni = cpu_has(c, X86_FEATURE_XMM3);
+ cpu->flags.pclmulqd = cpu_has(c, X86_FEATURE_PCLMULQDQ);
+ cpu->flags.dtes64 = cpu_has(c, X86_FEATURE_DTES64);
cpu->flags.vmx = cpu_has(c, X86_FEATURE_VMX);
+ cpu->flags.smx = cpu_has(c, X86_FEATURE_SMX);
+ cpu->flags.est = cpu_has(c, X86_FEATURE_EST);
+ cpu->flags.tm2 = cpu_has(c, X86_FEATURE_TM2);
+ cpu->flags.sse3 = cpu_has(c, X86_FEATURE_SSE3);
+ cpu->flags.cid = cpu_has(c, X86_FEATURE_CID);
+ cpu->flags.fma = cpu_has(c, X86_FEATURE_FMA);
+ cpu->flags.cx16 = cpu_has(c, X86_FEATURE_CX16);
+ cpu->flags.xtpr = cpu_has(c, X86_FEATURE_XTPR);
+ cpu->flags.pdcm = cpu_has(c, X86_FEATURE_PDCM);
+ cpu->flags.dca = cpu_has(c, X86_FEATURE_DCA);
+ cpu->flags.xmm4_1 = cpu_has(c, X86_FEATURE_XMM4_1);
+ cpu->flags.xmm4_2 = cpu_has(c, X86_FEATURE_XMM4_2);
+ cpu->flags.x2apic = cpu_has(c, X86_FEATURE_X2APIC);
+ cpu->flags.movbe = cpu_has(c, X86_FEATURE_MOVBE);
+ cpu->flags.popcnt = cpu_has(c, X86_FEATURE_POPCNT);
+ cpu->flags.aes = cpu_has(c, X86_FEATURE_AES);
+ cpu->flags.xsave = cpu_has(c, X86_FEATURE_XSAVE);
+ cpu->flags.osxsave = cpu_has(c, X86_FEATURE_OSXSAVE);
+ cpu->flags.avx = cpu_has(c, X86_FEATURE_AVX);
+ cpu->flags.hypervisor = cpu_has(c, X86_FEATURE_HYPERVISOR);
+ cpu->flags.ace2 = cpu_has(c, X86_FEATURE_ACE2);
+ cpu->flags.ace2_en = cpu_has(c, X86_FEATURE_ACE2_EN);
+ cpu->flags.phe = cpu_has(c, X86_FEATURE_PHE);
+ cpu->flags.phe_en = cpu_has(c, X86_FEATURE_PHE_EN);
+ cpu->flags.pmm = cpu_has(c, X86_FEATURE_PMM);
+ cpu->flags.pmm_en = cpu_has(c, X86_FEATURE_PMM_EN);
+ cpu->flags.extapic = cpu_has(c, X86_FEATURE_EXTAPIC);
+ cpu->flags.cr8_legacy = cpu_has(c, X86_FEATURE_CR8_LEGACY);
+ cpu->flags.abm = cpu_has(c, X86_FEATURE_ABM);
+ cpu->flags.sse4a = cpu_has(c, X86_FEATURE_SSE4A);
+ cpu->flags.misalignsse = cpu_has(c, X86_FEATURE_MISALIGNSSE);
+ cpu->flags.nowprefetch = cpu_has(c, X86_FEATURE_3DNOWPREFETCH);
+ cpu->flags.osvw = cpu_has(c, X86_FEATURE_OSVW);
+ cpu->flags.ibs = cpu_has(c, X86_FEATURE_IBS);
+ cpu->flags.sse5 = cpu_has(c, X86_FEATURE_SSE5);
+ cpu->flags.skinit = cpu_has(c, X86_FEATURE_SKINIT);
+ cpu->flags.wdt = cpu_has(c, X86_FEATURE_WDT);
+ cpu->flags.ida = cpu_has(c, X86_FEATURE_IDA);
+ cpu->flags.arat = cpu_has(c, X86_FEATURE_ARAT);
+ cpu->flags.tpr_shadow = cpu_has(c, X86_FEATURE_TPR_SHADOW);
+ cpu->flags.vnmi = cpu_has(c, X86_FEATURE_VNMI);
+ cpu->flags.flexpriority = cpu_has(c, X86_FEATURE_FLEXPRIORITY);
+ cpu->flags.ept = cpu_has(c, X86_FEATURE_EPT);
+ cpu->flags.vpid = cpu_has(c, X86_FEATURE_VPID);
cpu->flags.svm = cpu_has(c, X86_FEATURE_SVM);
}
diff --git a/com32/include/cpufeature.h b/com32/include/cpufeature.h
index 036631a7..df9dd3d3 100644
--- a/com32/include/cpufeature.h
+++ b/com32/include/cpufeature.h
@@ -40,6 +40,7 @@
#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
+#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
/* Don't duplicate feature flags which are redundant with Intel! */
@@ -47,6 +48,9 @@
#define X86_FEATURE_MP (1*32+19) /* MP Capable. */
#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
+#define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */
+#define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */
+#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
@@ -70,25 +74,73 @@
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
+#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
+#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
-#define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */
+#define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */
+#define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */
#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
+#define X86_FEATURE_SSE3 (4*32+ 9) /* Supplemental SSE-3 */
#define X86_FEATURE_CID (4*32+10) /* Context ID */
+#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
+#define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */
+#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
+#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
+#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
+#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
+#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */
+#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
+#define X86_FEATURE_AES (4*32+25) /* AES instructions */
+#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
+#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
+#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
+#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
+#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
+#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
+#define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */
+#define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */
+#define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */
+#define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */
/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
-#define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */
+#define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */
+#define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */
+#define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */
+#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
+#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
+#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
+#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
+#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
+#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */
+#define X86_FEATURE_SSE5 (6*32+11) /* SSE-5 */
+#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */
+#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */
+
+/*
+ * * Auxiliary flags: Linux defined - For features scattered in various
+ * * CPUID levels like 0x6, 0xA etc
+ * */
+#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */
+#define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */
+
+/* Virtualization flags: Linux defined */
+#define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
+#define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */
#endif /* __ASM_I386_CPUFEATURE_H */