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authorErwan Velu <erwan.velu@free.fr>2009-11-27 19:47:46 +0100
committerErwan Velu <erwan.velu@free.fr>2009-12-04 10:11:14 +0100
commit86f0a14f7c045776b14c5ad8f7c4974f9e0cfc01 (patch)
tree9daa2c38442b13793e0fc9c7c83a9cc2a18ee19d /com32/gplinclude/cpuid.h
parent91df71284aecce943b7d4e46220cf277b4098304 (diff)
downloadsyslinux.git-86f0a14f7c045776b14c5ad8f7c4974f9e0cfc01.tar.gz
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cpuid: Adding L1 & L2 cache detection
Impact: Adding L1 & L2 cache detection Adding L1 & L2 cache detection
Diffstat (limited to 'com32/gplinclude/cpuid.h')
-rw-r--r--com32/gplinclude/cpuid.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/com32/gplinclude/cpuid.h b/com32/gplinclude/cpuid.h
index 677f3f9f..bc9df171 100644
--- a/com32/gplinclude/cpuid.h
+++ b/com32/gplinclude/cpuid.h
@@ -128,6 +128,9 @@ typedef struct {
uint8_t model_id;
uint8_t stepping;
uint8_t num_cores;
+ uint16_t l1_data_cache_size;
+ uint16_t l1_instruction_cache_size;
+ uint16_t l2_cache_size;
s_cpu_flags flags;
} s_cpu;
@@ -196,7 +199,9 @@ struct cpuinfo_x86 {
uint32_t x86_capability[NCAPINTS];
char x86_vendor_id[16];
char x86_model_id[64];
- int x86_cache_size; /* in KB, if available */
+ uint16_t x86_l1_data_cache_size; /* in KB, if available */
+ uint16_t x86_l1_instruction_cache_size; /* in KB, if available */
+ uint16_t x86_l2_cache_size; /* in KB, if available */
int x86_cache_alignment; /* in bytes */
char fdiv_bug;
char f00f_bug;