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authorH. Peter Anvin <hpa@zytor.com>2007-10-11 14:47:23 -0700
committerH. Peter Anvin <hpa@zytor.com>2007-10-11 14:47:23 -0700
commit51f53cd1b7d82bf5dc451b2a9d12fe873507699c (patch)
tree1abd69671ef185e8b7e10908fa4c012c67ad3471 /bcopy32.inc
parent83d1b33a86685ede62933f761b8e0b61c48b269f (diff)
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Set TR and LDTR when entering protected mode
Intel's VT daftly requires TR and LDTR to have valid protected-mode values in order to kick in. Thus, give it at least a valid chunk of memory for the TR and a null selector for the LDTR.
Diffstat (limited to 'bcopy32.inc')
-rw-r--r--bcopy32.inc33
1 files changed, 26 insertions, 7 deletions
diff --git a/bcopy32.inc b/bcopy32.inc
index 4eef874d..7e3ac0f9 100644
--- a/bcopy32.inc
+++ b/bcopy32.inc
@@ -40,17 +40,22 @@ __bcopy_start:
bcopy_gdt: dw bcopy_gdt_size-1 ; Null descriptor - contains GDT
dd bcopy_gdt ; pointer for LGDT instruction
dw 0
- dd 0000ffffh ; Code segment, use16, readable,
+ dd 0000ffffh ; 08h Code segment, use16, readable,
dd 00009b00h ; present, dpl 0, cover 64K
- dd 0000ffffh ; Data segment, use16, read/write,
+ dd 0000ffffh ; 10h Data segment, use16, read/write,
dd 008f9300h ; present, dpl 0, cover all 4G
- dd 0000ffffh ; Data segment, use16, read/write,
+ dd 0000ffffh ; 18h Data segment, use16, read/write,
dd 00009300h ; present, dpl 0, cover 64K
- ; The rest are used for COM32 only
- dd 0000ffffh ; Code segment, use32, readable,
+ ; The next two segments are used for COM32 only
+ dd 0000ffffh ; 20h Code segment, use32, readable,
dd 00cf9b00h ; present, dpl 0, cover all 4G
- dd 0000ffffh ; Data segment, use32, read/write,
+ dd 0000ffffh ; 28h Data segment, use32, read/write,
dd 00cf9300h ; present, dpl 0, cover all 4G
+ ; TSS segment to keep Intel VT happy. Intel VT is
+ ; unhappy about anything that doesn't smell like a
+ ; full-blown 32-bit OS.
+ dw 104-1, DummyTSS ; 30h 32-bit task state segment
+ dd 00008900h ; present, dpl 0, 104 bytes @DummyTSS
bcopy_gdt_size: equ $-bcopy_gdt
;
@@ -100,11 +105,16 @@ bcopy: push eax
; ss is NOT zero in general, so we have to preserve
; the value.
- mov ax,18h ; Real-mode-like segment
+ mov al,18h ; Real-mode-like segment
mov fs,ax
mov gs,ax
mov ss,ax
+ mov al,30h ; Intel VT really doesn't want
+ ltr ax ; an invalid TR and LDTR, so give
+ xor ax,ax ; it something that it can use...
+ lldt ax ; (sigh)
+
cmp esi,-1
je .bzero
@@ -535,4 +545,13 @@ A20Tries resb 1 ; Times until giving up on A20
; For the PM case, it is 9*5 = 45 bytes long; for the RM case it is
; 8*6 to set the GPRs, 6*5 to set the segment registers (including a dummy
; setting of CS), 5 bytes to set CS:IP, for a total of 83 bytes.
+;
TrampolineBuf resb 83 ; Shuffle and boot trampoline
+
+;
+; Space for a dummy task state segment. It should never be actually
+; accessed, but just in case it is, point to a chunk of memory not used
+; for anything real.
+;
+ alignb 4
+DummyTSS resb 104