path: root/x86/insns.dat
Commit message (Expand)AuthorAgeFilesLines
* Fix inefficient encoding of MPX instructionsH. Peter Anvin2020-08-131-3/+3
* BR 3392705: AVX512: reinstate the SSE-like opcodes for VPCMPEQ/GTH. Peter Anvin (Intel)2020-07-301-0/+27
* insns.pl: audit for impossible Sx patterns; fix a fewH. Peter Anvin (Intel)2020-07-301-17/+17
* BR 3392704: unbreak MOVHPD instructionH. Peter Anvin (Intel)2020-07-281-4/+4
* BR 2292703: Add memory sizes to SSE and some other instructionsH. Peter Anvin (Intel)2020-07-271-145/+129
* BR 2292702: fix ENQCMDS and TILELOADT1 instructionsH. Peter Anvin (Intel)2020-07-271-5/+5
* insns.dat: fix accidentally duplicated patternsH. Peter Anvin2020-07-171-28/+0
* insns.dat: get rid of the X64 marker (= X86_64,LONG)H. Peter Anvin2020-07-171-388/+416
* x86/insns.dat: add tuple type for the latest AVX512 instructionsH. Peter Anvin2020-07-171-12/+12
* Add support for new instructions from ISE June 2020H. Peter Anvin2020-07-161-0/+45
* insns.dat: Add Intel Control-Flow Enforcement Technology (CET) instructionsHenrik Gramner2020-06-271-0/+16
* BR 3392681: handle a64 instruction patters correctlyH. Peter Anvin (Intel)2020-06-221-3/+3
* avx512: remove bogus imm8 for specific VCMP and VPCMP operationsH. Peter Anvin (Intel)2020-06-051-584/+584
* avx512: implement shorthand forms of VCMP and VPCMP opcodesH. Peter Anvin (Intel)2020-06-051-25/+585
* BR 3392676: fix cmpxchg8b/16b with explicit sizeH. Peter Anvin (Intel)2020-06-041-2/+2
* BR 3392674: fix handling of {ud1,ud2b} <reg>,<reg>H. Peter Anvin2020-06-011-6/+6
* insns.dat: Fix the opcodes for the AVX512-VBMI2 instructionsHenrik Gramner2020-04-221-18/+18
* LEA: allow immediate syntax; ignore operand size entirelyH. Peter Anvin (Intel)2019-08-141-3/+6
* obsolete handing: handle a few more subcases in a useful wayH. Peter Anvin (Intel)2019-08-091-1/+1
* Add implicitly sized versions of the K instructionsH. Peter Anvin (Intel)2019-08-091-2/+72
* insns.dat: Fix MOVDDUP instructionChang S. Bae2019-06-021-1/+1
* Merge tag 'nasm-2.14.01'H. Peter Anvin2018-12-221-0/+3
| * insns.dat: accept explicit ax/eax/rax operand to CLZEROH. Peter Anvin2018-12-221-0/+3
* | Don't convert the various RESx instructions to RESBH. Peter Anvin2018-12-181-7/+7
* insns.dat: add Intel Software Guard Extensions (SGX) instructionsH. Peter Anvin (Intel)2018-06-251-0/+5
* insns.dat: V4F(N)MADDSS are .lig not .512H. Peter Anvin (Intel)2018-06-251-2/+2
* insns.dat: fix the opcodes for the V4FNM* instructionsH. Peter Anvin2018-06-251-2/+2
* asm: support the +n syntax for register setsH. Peter Anvin2018-06-251-6/+6
* insns.dat: add support for the V4* and VP4* 4-way instructionsnasm-2.14rc8H. Peter Anvin (Intel)2018-06-251-0/+10
* insns.dat: add PTWRITE instructionH. Peter Anvin (Intel)2018-06-251-0/+4
* insns.dat: update with instructions from ISE 319433-034H. Peter Anvin2018-06-161-1/+131
* insns.dat: Update UD0 encoding to fit the specificationCyrill Gorcunov2018-02-251-1/+4
* Merge remote-tracking branch 'origin/nasm-2.13.xx'H. Peter Anvin2018-02-201-1/+19
| * insns.dat: add aliases of the RET instruction with explicit operand sizeH. Peter Anvin2018-02-141-1/+19
| * Revert "insns.dat: Add VAESENC, VAESENCLAST instructions"Cyrill Gorcunov2018-02-051-24/+0
| * insns.dat: Add VAESENC, VAESENCLAST instructionsTomasz Kantecki2018-02-051-0/+24
| * insns.dat: Add VPCLMULQDQ instruictionsTomasz Kantecki2018-01-081-0/+27
| * insns.dat: Move VAES instructions to AES groupCyrill Gorcunov2018-01-081-24/+25
| * insns.dat: Add VAESENC, VAESENCLAST instructionsTomasz Kantecki2018-01-081-0/+24
* | insns.dat: Add VPCLMULQDQ instruictionsTomasz Kantecki2017-12-291-0/+27
* | insns.dat: Move VAES instructions to AES groupCyrill Gorcunov2017-12-291-24/+25
* | insns.dat: Add VAESENC, VAESENCLAST instructionsTomasz Kantecki2017-12-291-0/+24
* | Merge remote-tracking branch 'origin/nasm-2.13.xx'H. Peter Anvin2017-11-011-4/+6
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| * BR 3392362: generate RMI versions of PEXTRW when possibleH. Peter Anvin2017-09-271-4/+6
* | insns.dat: change the title of the pseudo-ops sectionH. Peter Anvin2017-05-011-1/+1
* | Don't sort opcodes; move all pseudo-ops to the beginningH. Peter Anvin2017-05-011-1/+3
* doc: clean up the instruction list in the documentation slightlyH. Peter Anvin2017-04-071-16/+20
* BR 3392396: fix EVEX compressed displacementsH. Peter Anvin2017-04-061-6/+6
* Rename insns-iflags.pl -> insns-iflags.ph, add missing dependencyH. Peter Anvin2017-04-031-1/+1
* BR 3392370: {z} decorator allowed on MOVDQ* memory operandsH. Peter Anvin2017-03-311-36/+18