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authorH. Peter Anvin (Intel) <hpa@zytor.com>2020-08-31 12:23:36 -0700
committerH. Peter Anvin (Intel) <hpa@zytor.com>2020-08-31 12:23:36 -0700
commitcc64861a6187de89bf91acb344207c7ae5880bea (patch)
tree0e0dddb3d9b83ac5befc39a1b89216a5c76bd8ac /travis/test
parent515f4242963a0bd4322fc40ec9d8708bd470d849 (diff)
parent214f2d4c56925a280c480950bbf71389e2169e1a (diff)
downloadnasm-cc64861a6187de89bf91acb344207c7ae5880bea.tar.gz
nasm-cc64861a6187de89bf91acb344207c7ae5880bea.tar.xz
nasm-cc64861a6187de89bf91acb344207c7ae5880bea.zip
Merge tag 'nasm-2.15.05'
NASM 2.15.05 Resolved Conflicts: asm/preproc.c version Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Diffstat (limited to 'travis/test')
-rw-r--r--travis/test/a64.asm22
-rw-r--r--travis/test/a64.bin.t1
-rw-r--r--travis/test/a64.json18
-rw-r--r--travis/test/absolute.asm3
-rw-r--r--travis/test/alonesym-obj.obj.tbin1161 -> 1155 bytes
-rw-r--r--travis/test/amx.asm36
-rw-r--r--travis/test/amx.bin.t1
-rw-r--r--travis/test/amx.json12
-rw-r--r--travis/test/avx2.asm1608
-rw-r--r--travis/test/avx2.bin.tbin0 -> 7970 bytes
-rw-r--r--travis/test/avx2.json11
-rw-r--r--travis/test/br3104312.asm11
-rw-r--r--travis/test/br3104312.json11
-rw-r--r--travis/test/br3104312.stderr2
-rw-r--r--travis/test/br3392275.asm10
-rw-r--r--travis/test/br3392275.bin.t1
-rw-r--r--travis/test/br3392275.json12
-rw-r--r--travis/test/br3392363.asm5
-rw-r--r--travis/test/br3392363.bin.t1
-rw-r--r--travis/test/br3392363.json12
-rw-r--r--travis/test/br3392392.asm15
-rw-r--r--travis/test/br3392392.bin.tbin0 -> 48 bytes
-rw-r--r--travis/test/br3392392.json21
-rw-r--r--travis/test/br3392392.stderr1
-rw-r--r--travis/test/br3392396.asm5
-rw-r--r--travis/test/br3392396.bin.t1
-rw-r--r--travis/test/br3392396.json12
-rw-r--r--travis/test/br3392411.asm22
-rw-r--r--travis/test/br3392411.json12
-rw-r--r--travis/test/br3392411.out.tbin0 -> 355 bytes
-rw-r--r--travis/test/br3392643.obj.tbin349 -> 343 bytes
-rw-r--r--travis/test/elif.o.tbin230 -> 224 bytes
-rw-r--r--travis/test/ifid.asm19
-rw-r--r--travis/test/ifid.bin.t3
-rw-r--r--travis/test/ifid.json11
-rw-r--r--travis/test/lwp.asm213
-rw-r--r--travis/test/lwp.bin.tbin0 -> 1810 bytes
-rw-r--r--travis/test/lwp.json12
-rw-r--r--travis/test/obj.o.tbin480 -> 474 bytes
-rw-r--r--travis/test/ret-16.stderr1
-rw-r--r--travis/test/ret-32.stderr1
-rw-r--r--travis/test/ret-64.stderr1
-rw-r--r--travis/test/ret.asm61
-rw-r--r--travis/test/ret.bin.t1
-rw-r--r--travis/test/ret.json39
-rw-r--r--travis/test/sreg.asm65
-rw-r--r--travis/test/sreg.bin.t1
-rw-r--r--travis/test/sreg.json12
-rw-r--r--travis/test/tmap.json22
-rw-r--r--travis/test/tmap.stderr (renamed from travis/test/tmap.o.stderr)0
-rw-r--r--travis/test/v4.asm16
-rw-r--r--travis/test/v4.bin.tbin0 -> 42 bytes
-rw-r--r--travis/test/v4.json21
-rw-r--r--travis/test/v4.stderr3
-rw-r--r--travis/test/vaesenc.asm20
-rw-r--r--travis/test/vaesenc.bin.tbin0 -> 93 bytes
-rw-r--r--travis/test/vaesenc.json12
-rw-r--r--travis/test/vex.asm9
-rw-r--r--travis/test/vex.bin.t1
-rw-r--r--travis/test/vex.json21
-rw-r--r--travis/test/vex.stderr1
-rw-r--r--travis/test/vgather.asm76
-rw-r--r--travis/test/vgather.bin.tbin0 -> 440 bytes
-rw-r--r--travis/test/vgather.json12
-rw-r--r--travis/test/vpcmp.asm28
-rw-r--r--travis/test/vpcmp.bin.tbin0 -> 160 bytes
-rw-r--r--travis/test/vpcmp.json12
-rw-r--r--travis/test/warnstack.asm10
-rw-r--r--travis/test/warnstack.bin.t0
-rw-r--r--travis/test/warnstack.json13
-rw-r--r--travis/test/warnstack.stderr4
-rw-r--r--travis/test/winalign.asm45
-rw-r--r--travis/test/winalign.json13
-rw-r--r--travis/test/winalign.obj.tbin0 -> 642 bytes
-rw-r--r--travis/test/xdefine.asm15
-rw-r--r--travis/test/xdefine.bin.t1
-rw-r--r--travis/test/xdefine.json12
-rw-r--r--travis/test/xpaste.asm6
-rw-r--r--travis/test/xpaste.bin.t1
-rw-r--r--travis/test/xpaste.json11
80 files changed, 2681 insertions, 10 deletions
diff --git a/travis/test/a64.asm b/travis/test/a64.asm
new file mode 100644
index 00000000..057c29fc
--- /dev/null
+++ b/travis/test/a64.asm
@@ -0,0 +1,22 @@
+ bits 64
+start:
+ invlpga eax, ecx
+ invlpga rax, ecx
+ jecxz start
+ jrcxz start
+ loop start, ecx
+ loop start, rcx
+ loope start, ecx
+ loope start, rcx
+ loopz start, ecx
+ loopz start, rcx
+ loopne start, ecx
+ loopne start, rcx
+ loopnz start, ecx
+ loopnz start, rcx
+ clzero eax
+ clzero rax
+ movdir64b eax, [edi]
+ movdir64b rax, [rdi]
+ umonitor eax
+ umonitor rax
diff --git a/travis/test/a64.bin.t b/travis/test/a64.bin.t
new file mode 100644
index 00000000..b13b9e53
--- /dev/null
+++ b/travis/test/a64.bin.t
@@ -0,0 +1 @@
+gggggggggf8f8g \ No newline at end of file
diff --git a/travis/test/a64.json b/travis/test/a64.json
new file mode 100644
index 00000000..f734b11e
--- /dev/null
+++ b/travis/test/a64.json
@@ -0,0 +1,18 @@
+[
+ {
+ "description": "Test 64 bit address (-Ox)",
+ "id": "a64",
+ "format": "bin",
+ "source": "a64.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "a64.bin" }
+ ]
+ },
+ {
+ "description": "Test 64 bit address (-O0)",
+ "ref": "a64",
+ "option": "-O0",
+ "update": "false"
+ }
+]
diff --git a/travis/test/absolute.asm b/travis/test/absolute.asm
index 38532ec9..8a72a9b5 100644
--- a/travis/test/absolute.asm
+++ b/travis/test/absolute.asm
@@ -1,4 +1,7 @@
+%ifmacro org
org 7c00h
+%endif
+
init_foo:
jmp init_bar
nop
diff --git a/travis/test/alonesym-obj.obj.t b/travis/test/alonesym-obj.obj.t
index 99ec34c4..aa25a5c9 100644
--- a/travis/test/alonesym-obj.obj.t
+++ b/travis/test/alonesym-obj.obj.t
Binary files differ
diff --git a/travis/test/amx.asm b/travis/test/amx.asm
new file mode 100644
index 00000000..88455508
--- /dev/null
+++ b/travis/test/amx.asm
@@ -0,0 +1,36 @@
+ bits 64
+
+%macro amx 1
+ %define treg tmm %+ %1
+
+ ldtilecfg [rsi]
+ sttilecfg [rdi]
+
+ tilezero treg
+
+ tileloadd treg, [rax]
+ tileloadd treg, [rax,rdx]
+ tileloadd treg, [rax,rdx*2]
+
+ tileloaddt1 treg, [rax]
+ tileloaddt1 treg, [rax,rdx]
+ tileloaddt1 treg, [rax,rdx*2]
+
+ tdpbf16ps treg, treg, treg
+ tdpbssd treg, treg, treg
+ tdpbusd treg, treg, treg
+ tdpbsud treg, treg, treg
+ tdpbuud treg, treg, treg
+
+ tilestored [rax], treg
+ tilestored [rax,rdx], treg
+ tilestored [rax,rdx*2], treg
+
+ tilerelease
+%endmacro
+
+%assign n 0
+ %rep 8
+ amx n
+ %assign n n+1
+ %endrep
diff --git a/travis/test/amx.bin.t b/travis/test/amx.bin.t
new file mode 100644
index 00000000..ad28ba5b
--- /dev/null
+++ b/travis/test/amx.bin.t
@@ -0,0 +1 @@
+xIyI{I{K {K{KPyK yKyKPz\{^y^z^x^zK zKzKPxIxIyI{I{K {K {K PyK yK yK Pr\s^q^r^p^zK zK zK PxIxIyI{I{K {K{KPyK yKyKPj\k^i^j^h^zK zKzKPxIxIyI{I{K {K{KPyK yKyKPb\c^a^b^`^zK zKzKPxIxIyI{I{K$ {K${K$PyK$ yK$yK$PZ\[^Y^Z^X^zK$ zK$zK$PxIxIyI{I{K, {K,{K,PyK, yK,yK,PR\S^Q^R^P^zK, zK,zK,PxIxIyI{I{K4 {K4{K4PyK4 yK4yK4PJ\K^I^J^H^zK4 zK4zK4PxIxIyI{I{K< {K<{K<PyK< yK<yK<PB\C^A^B^@^zK< zK<zK<PxI \ No newline at end of file
diff --git a/travis/test/amx.json b/travis/test/amx.json
new file mode 100644
index 00000000..6697331e
--- /dev/null
+++ b/travis/test/amx.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Test AMX instructions",
+ "id": "amx",
+ "format": "bin",
+ "source": "amx.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "amx.bin" }
+ ]
+ }
+]
diff --git a/travis/test/avx2.asm b/travis/test/avx2.asm
new file mode 100644
index 00000000..b6228513
--- /dev/null
+++ b/travis/test/avx2.asm
@@ -0,0 +1,1608 @@
+; AVX testcases from gas
+;------------------------
+
+;
+; This file is taken from there
+; http://sourceware.org/ml/binutils/2011-06/msg00150.html
+; So the original author is "H.J. Lu" <hongjiu dot lu at intel dot com>
+;
+; nasm64developer adopted it for the nasm testing suite
+
+%macro testcase 2
+ %ifdef BIN
+ db %1
+ %endif
+ %ifdef SRC
+ %2
+ %endif
+%endmacro
+
+bits 32
+
+; b/gas/testsuite/gas/i386/avx-gather-intel.d
+testcase { 0xc4, 0xe2, 0xe9, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdpd xmm1,QWORD [ebp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0xe9, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqpd xmm1,QWORD [ebp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0xed, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdpd ymm1,QWORD [ebp+xmm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0xed, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqpd ymm1,QWORD [ebp+ymm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm4*1-0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x0],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x298],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm4*8-0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x0],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x298],ymm5 }
+testcase { 0xc4, 0xe2, 0x69, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdps xmm1,DWORD [ebp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x69, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqps xmm1,DWORD [ebp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x6d, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdps ymm1,DWORD [ebp+ymm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0x6d, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqps xmm1,DWORD [ebp+ymm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm4*1-0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x0],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x298],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm4*8-0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x0],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x298],xmm5 }
+testcase { 0xc4, 0xe2, 0x69, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdd xmm1,DWORD [ebp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x69, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqd xmm1,DWORD [ebp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x6d, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdd ymm1,DWORD [ebp+ymm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0x6d, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqd xmm1,DWORD [ebp+ymm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm4*1-0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x0],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x298],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm4*8-0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x0],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x298],xmm5 }
+testcase { 0xc4, 0xe2, 0xe9, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdq xmm1,QWORD [ebp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0xe9, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqq xmm1,QWORD [ebp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0xed, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdq ymm1,QWORD [ebp+xmm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0xed, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqq ymm1,QWORD [ebp+ymm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm4*1-0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x0],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x298],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm4*8-0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x0],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x298],ymm5 }
+
+; b/gas/testsuite/gas/i386/avx2-intel.d
+testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [ecx],ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [ecx],ymm6,ymm4 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0xd6, 0x07 }, { vpermpd ymm2,ymm6,0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0xd6, 0x07 }, { vpermq ymm2,ymm6,0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0xd4 }, { vpermd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0xd4 }, { vpermps ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0xd4 }, { vpsllvd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0xd4 }, { vpsllvq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0xd4 }, { vpsravd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0xd4 }, { vpsrlvd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0xd4 }, { vpsrlvq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x19, 0xf4 }, { vbroadcastsd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x18, 0xf4 }, { vbroadcastss ymm6,xmm4 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0xd4, 0x07 }, { vpblendd ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0xd4, 0x07 }, { vperm2i128 ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x07 }, { vinserti128 ymm6,ymm4,xmm4,0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [ecx],0x7 }
+testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0xd4 }, { vpsllvd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0xd4 }, { vpsllvq xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0xd4 }, { vpsravd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0xd4 }, { vpsrlvd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0xd4 }, { vpsrlvq xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [ecx] }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x07 }, { vextracti128 xmm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [ecx],ymm4,0x7 }
+testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [ecx],xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [ecx],xmm6,xmm4 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0xd4, 0x07 }, { vpblendd xmm2,xmm6,xmm4,0x7 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [ecx],0x7 }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0xf4 }, { vpbroadcastq xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0xf4 }, { vpbroadcastq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0xe4 }, { vpbroadcastd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0xf4 }, { vpbroadcastd xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0xf4 }, { vpbroadcastw xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0xf4 }, { vpbroadcastw ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0xf4 }, { vpbroadcastb xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0xf4 }, { vpbroadcastb ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x18, 0xf4 }, { vbroadcastss xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [ecx],ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [ecx],ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [ecx],ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [ecx],ymm6,ymm4 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0xd6, 0x07 }, { vpermpd ymm2,ymm6,0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0xd6, 0x07 }, { vpermq ymm2,ymm6,0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0xd4 }, { vpermd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0xd4 }, { vpermps ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0xd4 }, { vpsllvd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0xd4 }, { vpsllvq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0xd4 }, { vpsravd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0xd4 }, { vpsrlvd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0xd4 }, { vpsrlvq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x19, 0xf4 }, { vbroadcastsd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x18, 0xf4 }, { vbroadcastss ymm6,xmm4 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0xd4, 0x07 }, { vpblendd ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0xd4, 0x07 }, { vperm2i128 ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x07 }, { vinserti128 ymm6,ymm4,xmm4,0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [ecx],0x7 }
+testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0xd4 }, { vpsllvd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0xd4 }, { vpsllvq xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0xd4 }, { vpsravd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0xd4 }, { vpsrlvd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0xd4 }, { vpsrlvq xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [ecx] }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x07 }, { vextracti128 xmm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [ecx],ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [ecx],ymm4,0x7 }
+testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [ecx],xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [ecx],xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [ecx],xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [ecx],xmm6,xmm4 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0xd4, 0x07 }, { vpblendd xmm2,xmm6,xmm4,0x7 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [ecx],0x7 }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0xf4 }, { vpbroadcastq xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0xf4 }, { vpbroadcastq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0xe4 }, { vpbroadcastd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0xf4 }, { vpbroadcastd xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0xf4 }, { vpbroadcastw xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0xf4 }, { vpbroadcastw ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0xf4 }, { vpbroadcastb xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0xf4 }, { vpbroadcastb ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [ecx] }
+testcase { 0xc4, 0xe2, 0x79, 0x18, 0xf4 }, { vbroadcastss xmm6,xmm4 }
+
+; b/gas/testsuite/gas/i386/avx256int-intel.d
+testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 }
+testcase { 0xc5, 0xed, 0x72, 0xf6, 0x07 }, { vpslld ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xfe, 0x07 }, { vpslldq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xf6, 0x07 }, { vpsllq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xf6, 0x07 }, { vpsllw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x72, 0xe6, 0x07 }, { vpsrad ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xe6, 0x07 }, { vpsraw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x72, 0xd6, 0x07 }, { vpsrld ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xde, 0x07 }, { vpsrldq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xd6, 0x07 }, { vpsrlq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xd6, 0x07 }, { vpsrlw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0xd6, 0x07 }, { vpshufd ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [ecx],0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0xd6, 0x07 }, { vpshufhw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [ecx],0x7 }
+testcase { 0xc5, 0xff, 0x70, 0xd6, 0x07 }, { vpshuflw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [ecx],0x7 }
+testcase { 0xc5, 0xcd, 0x6b, 0xd4 }, { vpackssdw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x63, 0xd4 }, { vpacksswb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0xd4 }, { vpackusdw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x67, 0xd4 }, { vpackuswb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfc, 0xd4 }, { vpaddb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfd, 0xd4 }, { vpaddw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfe, 0xd4 }, { vpaddd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd4, 0xd4 }, { vpaddq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xec, 0xd4 }, { vpaddsb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xed, 0xd4 }, { vpaddsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdc, 0xd4 }, { vpaddusb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdd, 0xd4 }, { vpaddusw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdb, 0xd4 }, { vpand ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdf, 0xd4 }, { vpandn ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe0, 0xd4 }, { vpavgb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe3, 0xd4 }, { vpavgw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x74, 0xd4 }, { vpcmpeqb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x75, 0xd4 }, { vpcmpeqw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x76, 0xd4 }, { vpcmpeqd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0xd4 }, { vpcmpeqq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x64, 0xd4 }, { vpcmpgtb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x65, 0xd4 }, { vpcmpgtw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x66, 0xd4 }, { vpcmpgtd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0xd4 }, { vpcmpgtq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0xd4 }, { vphaddw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0xd4 }, { vphaddd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0xd4 }, { vphaddsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0xd4 }, { vphsubw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0xd4 }, { vphsubd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0xd4 }, { vphsubsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf5, 0xd4 }, { vpmaddwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0xd4 }, { vpmaddubsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0xd4 }, { vpmaxsb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xee, 0xd4 }, { vpmaxsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0xd4 }, { vpmaxsd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xde, 0xd4 }, { vpmaxub ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0xd4 }, { vpmaxuw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0xd4 }, { vpmaxud ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0xd4 }, { vpminsb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xea, 0xd4 }, { vpminsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0xd4 }, { vpminsd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xda, 0xd4 }, { vpminub ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0xd4 }, { vpminuw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0xd4 }, { vpminud ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe4, 0xd4 }, { vpmulhuw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0xd4 }, { vpmulhrsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe5, 0xd4 }, { vpmulhw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd5, 0xd4 }, { vpmullw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0xd4 }, { vpmulld ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf4, 0xd4 }, { vpmuludq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0xd4 }, { vpmuldq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xeb, 0xd4 }, { vpor ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf6, 0xd4 }, { vpsadbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0xd4 }, { vpshufb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0xd4 }, { vpsignb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0xd4 }, { vpsignw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0xd4 }, { vpsignd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf8, 0xd4 }, { vpsubb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf9, 0xd4 }, { vpsubw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfa, 0xd4 }, { vpsubd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfb, 0xd4 }, { vpsubq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe8, 0xd4 }, { vpsubsb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe9, 0xd4 }, { vpsubsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd8, 0xd4 }, { vpsubusb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd9, 0xd4 }, { vpsubusw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x68, 0xd4 }, { vpunpckhbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x69, 0xd4 }, { vpunpckhwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6a, 0xd4 }, { vpunpckhdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6d, 0xd4 }, { vpunpckhqdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x60, 0xd4 }, { vpunpcklbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x61, 0xd4 }, { vpunpcklwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x62, 0xd4 }, { vpunpckldq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6c, 0xd4 }, { vpunpcklqdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xef, 0xd4 }, { vpxor ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0xf4 }, { vpabsb ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0xf4 }, { vpabsw ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0xf4 }, { vpabsd ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x07 }, { vmpsadbw ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0xd4, 0x07 }, { vpalignr ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0xd4, 0x07 }, { vpblendw ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0xfe, 0x40 }, { vpblendvb ymm7,ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [ecx],ymm4 }
+testcase { 0xc5, 0xcd, 0xf1, 0xd4 }, { vpsllw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf2, 0xd4 }, { vpslld ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf3, 0xd4 }, { vpsllq ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe1, 0xd4 }, { vpsraw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe2, 0xd4 }, { vpsrad ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd1, 0xd4 }, { vpsrlw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd2, 0xd4 }, { vpsrld ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd3, 0xd4 }, { vpsrlq ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0xe4 }, { vpmovsxbw ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0xe4 }, { vpmovsxwd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0xe4 }, { vpmovsxdq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0xe4 }, { vpmovzxbw ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0xe4 }, { vpmovzxwd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0xe4 }, { vpmovzxdq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0xf4 }, { vpmovsxbd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0xf4 }, { vpmovsxwq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0xf4 }, { vpmovzxbd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0xf4 }, { vpmovzxwq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0xe4 }, { vpmovsxbq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0xe4 }, { vpmovzxbq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [ecx] }
+testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 }
+testcase { 0xc5, 0xed, 0x72, 0xf6, 0x07 }, { vpslld ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xfe, 0x07 }, { vpslldq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xf6, 0x07 }, { vpsllq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xf6, 0x07 }, { vpsllw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x72, 0xe6, 0x07 }, { vpsrad ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xe6, 0x07 }, { vpsraw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x72, 0xd6, 0x07 }, { vpsrld ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xde, 0x07 }, { vpsrldq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xd6, 0x07 }, { vpsrlq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xd6, 0x07 }, { vpsrlw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0xd6, 0x07 }, { vpshufd ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [ecx],0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [ecx],0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0xd6, 0x07 }, { vpshufhw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [ecx],0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [ecx],0x7 }
+testcase { 0xc5, 0xff, 0x70, 0xd6, 0x07 }, { vpshuflw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [ecx],0x7 }
+testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [ecx],0x7 }
+testcase { 0xc5, 0xcd, 0x6b, 0xd4 }, { vpackssdw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x63, 0xd4 }, { vpacksswb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0xd4 }, { vpackusdw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x67, 0xd4 }, { vpackuswb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfc, 0xd4 }, { vpaddb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfd, 0xd4 }, { vpaddw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfe, 0xd4 }, { vpaddd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd4, 0xd4 }, { vpaddq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xec, 0xd4 }, { vpaddsb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xed, 0xd4 }, { vpaddsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdc, 0xd4 }, { vpaddusb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdd, 0xd4 }, { vpaddusw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdb, 0xd4 }, { vpand ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdf, 0xd4 }, { vpandn ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe0, 0xd4 }, { vpavgb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe3, 0xd4 }, { vpavgw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x74, 0xd4 }, { vpcmpeqb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x75, 0xd4 }, { vpcmpeqw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x76, 0xd4 }, { vpcmpeqd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0xd4 }, { vpcmpeqq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x64, 0xd4 }, { vpcmpgtb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x65, 0xd4 }, { vpcmpgtw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x66, 0xd4 }, { vpcmpgtd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0xd4 }, { vpcmpgtq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0xd4 }, { vphaddw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0xd4 }, { vphaddd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0xd4 }, { vphaddsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0xd4 }, { vphsubw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0xd4 }, { vphsubd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0xd4 }, { vphsubsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf5, 0xd4 }, { vpmaddwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0xd4 }, { vpmaddubsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0xd4 }, { vpmaxsb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xee, 0xd4 }, { vpmaxsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0xd4 }, { vpmaxsd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xde, 0xd4 }, { vpmaxub ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0xd4 }, { vpmaxuw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0xd4 }, { vpmaxud ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0xd4 }, { vpminsb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xea, 0xd4 }, { vpminsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0xd4 }, { vpminsd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xda, 0xd4 }, { vpminub ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0xd4 }, { vpminuw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0xd4 }, { vpminud ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe4, 0xd4 }, { vpmulhuw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0xd4 }, { vpmulhrsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe5, 0xd4 }, { vpmulhw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd5, 0xd4 }, { vpmullw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0xd4 }, { vpmulld ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf4, 0xd4 }, { vpmuludq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0xd4 }, { vpmuldq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xeb, 0xd4 }, { vpor ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf6, 0xd4 }, { vpsadbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0xd4 }, { vpshufb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0xd4 }, { vpsignb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0xd4 }, { vpsignw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0xd4 }, { vpsignd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf8, 0xd4 }, { vpsubb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf9, 0xd4 }, { vpsubw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfa, 0xd4 }, { vpsubd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfb, 0xd4 }, { vpsubq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe8, 0xd4 }, { vpsubsb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe9, 0xd4 }, { vpsubsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd8, 0xd4 }, { vpsubusb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd9, 0xd4 }, { vpsubusw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x68, 0xd4 }, { vpunpckhbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x69, 0xd4 }, { vpunpckhwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6a, 0xd4 }, { vpunpckhdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6d, 0xd4 }, { vpunpckhqdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x60, 0xd4 }, { vpunpcklbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x61, 0xd4 }, { vpunpcklwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x62, 0xd4 }, { vpunpckldq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6c, 0xd4 }, { vpunpcklqdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xef, 0xd4 }, { vpxor ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0xf4 }, { vpabsb ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0xf4 }, { vpabsw ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0xf4 }, { vpabsd ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [ecx] }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x07 }, { vmpsadbw ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0xd4, 0x07 }, { vpalignr ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0xd4, 0x07 }, { vpblendw ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [ecx],0x7 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0xfe, 0x40 }, { vpblendvb ymm7,ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [ecx],ymm4 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [ecx],ymm4 }
+testcase { 0xc5, 0xcd, 0xf1, 0xd4 }, { vpsllw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf2, 0xd4 }, { vpslld ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf3, 0xd4 }, { vpsllq ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe1, 0xd4 }, { vpsraw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe2, 0xd4 }, { vpsrad ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd1, 0xd4 }, { vpsrlw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd2, 0xd4 }, { vpsrld ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd3, 0xd4 }, { vpsrlq ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0xe4 }, { vpmovsxbw ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0xe4 }, { vpmovsxwd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0xe4 }, { vpmovsxdq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0xe4 }, { vpmovzxbw ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0xe4 }, { vpmovzxwd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0xe4 }, { vpmovzxdq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0xf4 }, { vpmovsxbd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0xf4 }, { vpmovsxwq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0xf4 }, { vpmovzxbd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0xf4 }, { vpmovzxwq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0xe4 }, { vpmovsxbq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0xe4 }, { vpmovzxbq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [ecx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [ecx] }
+
+bits 64
+
+; b/gas/testsuite/gas/i386/x86-64-avx-gather-intel.d
+testcase { 0xc4, 0xe2, 0xe9, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdpd xmm1,QWORD [rbp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0xe9, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqpd xmm1,QWORD [rbp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0xed, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdpd ymm1,QWORD [rbp+xmm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0xed, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqpd ymm1,QWORD [rbp+ymm7*2+0x0],ymm2 }
+testcase { 0xc4, 0x02, 0x99, 0x92, 0x5c, 0x75, 0x00 }, { vgatherdpd xmm11,QWORD [r13+xmm14*2+0x0],xmm12 }
+testcase { 0xc4, 0x02, 0x99, 0x93, 0x5c, 0x75, 0x00 }, { vgatherqpd xmm11,QWORD [r13+xmm14*2+0x0],xmm12 }
+testcase { 0xc4, 0x02, 0x9d, 0x92, 0x5c, 0x75, 0x00 }, { vgatherdpd ymm11,QWORD [r13+xmm14*2+0x0],ymm12 }
+testcase { 0xc4, 0x02, 0x9d, 0x93, 0x5c, 0x75, 0x00 }, { vgatherqpd ymm11,QWORD [r13+ymm14*2+0x0],ymm12 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm4*1-0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x0],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*1+0x298],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm4*8-0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x0],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x92, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm4*8+0x298],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0x35, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*1+0x8],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0x35, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm14*1-0x8],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0x35, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*1+0x0],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0x35, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*1+0x298],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0xf5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*8+0x8],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0xf5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdpd ymm6,QWORD [xmm14*8-0x8],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0xf5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*8+0x0],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x92, 0x34, 0xf5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdpd ymm6,QWORD [xmm14*8+0x298],ymm5 }
+testcase { 0xc4, 0xe2, 0x69, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdps xmm1,DWORD [rbp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x69, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqps xmm1,DWORD [rbp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x6d, 0x92, 0x4c, 0x7d, 0x00 }, { vgatherdps ymm1,DWORD [rbp+ymm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0x6d, 0x93, 0x4c, 0x7d, 0x00 }, { vgatherqps xmm1,DWORD [rbp+ymm7*2+0x0],xmm2 }
+testcase { 0xc4, 0x02, 0x19, 0x92, 0x5c, 0x75, 0x00 }, { vgatherdps xmm11,DWORD [r13+xmm14*2+0x0],xmm12 }
+testcase { 0xc4, 0x02, 0x19, 0x93, 0x5c, 0x75, 0x00 }, { vgatherqps xmm11,DWORD [r13+xmm14*2+0x0],xmm12 }
+testcase { 0xc4, 0x02, 0x1d, 0x92, 0x5c, 0x75, 0x00 }, { vgatherdps ymm11,DWORD [r13+ymm14*2+0x0],ymm12 }
+testcase { 0xc4, 0x02, 0x1d, 0x93, 0x5c, 0x75, 0x00 }, { vgatherqps xmm11,DWORD [r13+ymm14*2+0x0],xmm12 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm4*1-0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x0],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*1+0x298],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm4*8-0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x0],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x92, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm4*8+0x298],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0x35, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*1+0x8],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0x35, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm14*1-0x8],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0x35, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*1+0x0],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0x35, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*1+0x298],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0xf5, 0x08, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*8+0x8],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0xf5, 0xf8, 0xff, 0xff, 0xff }, { vgatherdps xmm6,DWORD [xmm14*8-0x8],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0xf5, 0x00, 0x00, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*8+0x0],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x92, 0x34, 0xf5, 0x98, 0x02, 0x00, 0x00 }, { vgatherdps xmm6,DWORD [xmm14*8+0x298],xmm5 }
+testcase { 0xc4, 0xe2, 0x69, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdd xmm1,DWORD [rbp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x69, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqd xmm1,DWORD [rbp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0x6d, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdd ymm1,DWORD [rbp+ymm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0x6d, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqd xmm1,DWORD [rbp+ymm7*2+0x0],xmm2 }
+testcase { 0xc4, 0x02, 0x19, 0x90, 0x5c, 0x75, 0x00 }, { vpgatherdd xmm11,DWORD [r13+xmm14*2+0x0],xmm12 }
+testcase { 0xc4, 0x02, 0x19, 0x91, 0x5c, 0x75, 0x00 }, { vpgatherqd xmm11,DWORD [r13+xmm14*2+0x0],xmm12 }
+testcase { 0xc4, 0x02, 0x1d, 0x90, 0x5c, 0x75, 0x00 }, { vpgatherdd ymm11,DWORD [r13+ymm14*2+0x0],ymm12 }
+testcase { 0xc4, 0x02, 0x1d, 0x91, 0x5c, 0x75, 0x00 }, { vpgatherqd xmm11,DWORD [r13+ymm14*2+0x0],xmm12 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm4*1-0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x0],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*1+0x298],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm4*8-0x8],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x0],xmm5 }
+testcase { 0xc4, 0xe2, 0x51, 0x90, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm4*8+0x298],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0x35, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*1+0x8],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0x35, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm14*1-0x8],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0x35, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*1+0x0],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0x35, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*1+0x298],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0xf5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*8+0x8],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0xf5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdd xmm6,DWORD [xmm14*8-0x8],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0xf5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*8+0x0],xmm5 }
+testcase { 0xc4, 0xa2, 0x51, 0x90, 0x34, 0xf5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdd xmm6,DWORD [xmm14*8+0x298],xmm5 }
+testcase { 0xc4, 0xe2, 0xe9, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdq xmm1,QWORD [rbp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0xe9, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqq xmm1,QWORD [rbp+xmm7*2+0x0],xmm2 }
+testcase { 0xc4, 0xe2, 0xed, 0x90, 0x4c, 0x7d, 0x00 }, { vpgatherdq ymm1,QWORD [rbp+xmm7*2+0x0],ymm2 }
+testcase { 0xc4, 0xe2, 0xed, 0x91, 0x4c, 0x7d, 0x00 }, { vpgatherqq ymm1,QWORD [rbp+ymm7*2+0x0],ymm2 }
+testcase { 0xc4, 0x02, 0x99, 0x90, 0x5c, 0x75, 0x00 }, { vpgatherdq xmm11,QWORD [r13+xmm14*2+0x0],xmm12 }
+testcase { 0xc4, 0x02, 0x99, 0x91, 0x5c, 0x75, 0x00 }, { vpgatherqq xmm11,QWORD [r13+xmm14*2+0x0],xmm12 }
+testcase { 0xc4, 0x02, 0x9d, 0x90, 0x5c, 0x75, 0x00 }, { vpgatherdq ymm11,QWORD [r13+xmm14*2+0x0],ymm12 }
+testcase { 0xc4, 0x02, 0x9d, 0x91, 0x5c, 0x75, 0x00 }, { vpgatherqq ymm11,QWORD [r13+ymm14*2+0x0],ymm12 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm4*1-0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x0],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0x25, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*1+0x298],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm4*8-0x8],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x0],ymm5 }
+testcase { 0xc4, 0xe2, 0xd5, 0x90, 0x34, 0xe5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm4*8+0x298],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0x35, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*1+0x8],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0x35, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm14*1-0x8],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0x35, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*1+0x0],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0x35, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*1+0x298],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0xf5, 0x08, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*8+0x8],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0xf5, 0xf8, 0xff, 0xff, 0xff }, { vpgatherdq ymm6,QWORD [xmm14*8-0x8],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0xf5, 0x00, 0x00, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*8+0x0],ymm5 }
+testcase { 0xc4, 0xa2, 0xd5, 0x90, 0x34, 0xf5, 0x98, 0x02, 0x00, 0x00 }, { vpgatherdq ymm6,QWORD [xmm14*8+0x298],ymm5 }
+
+; b/gas/testsuite/gas/i386/x86-64-avx2-intel.d
+testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [rcx],ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [rcx],ymm6,ymm4 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0xd6, 0x07 }, { vpermpd ymm2,ymm6,0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0xd6, 0x07 }, { vpermq ymm2,ymm6,0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0xd4 }, { vpermd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0xd4 }, { vpermps ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0xd4 }, { vpsllvd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0xd4 }, { vpsllvq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0xd4 }, { vpsravd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0xd4 }, { vpsrlvd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0xd4 }, { vpsrlvq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x19, 0xf4 }, { vbroadcastsd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x18, 0xf4 }, { vbroadcastss ymm6,xmm4 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0xd4, 0x07 }, { vpblendd ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0xd4, 0x07 }, { vperm2i128 ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x07 }, { vinserti128 ymm6,ymm4,xmm4,0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [rcx],0x7 }
+testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0xd4 }, { vpsllvd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0xd4 }, { vpsllvq xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0xd4 }, { vpsravd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0xd4 }, { vpsrlvd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0xd4 }, { vpsrlvq xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [rcx] }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x07 }, { vextracti128 xmm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [rcx],ymm4,0x7 }
+testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [rcx],xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [rcx],xmm6,xmm4 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0xd4, 0x07 }, { vpblendd xmm2,xmm6,xmm4,0x7 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [rcx],0x7 }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0xf4 }, { vpbroadcastq xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0xf4 }, { vpbroadcastq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0xe4 }, { vpbroadcastd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0xf4 }, { vpbroadcastd xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0xf4 }, { vpbroadcastw xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0xf4 }, { vpbroadcastw ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0xf4 }, { vpbroadcastb xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0xf4 }, { vpbroadcastb ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x18, 0xf4 }, { vbroadcastss xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [rcx],ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x5d, 0x8c, 0x31 }, { vpmaskmovd ymm6,ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x8e, 0x21 }, { vpmaskmovd YWORD [rcx],ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [rcx],ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xdd, 0x8c, 0x31 }, { vpmaskmovq ymm6,ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x8e, 0x21 }, { vpmaskmovq YWORD [rcx],ymm6,ymm4 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0xd6, 0x07 }, { vpermpd ymm2,ymm6,0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x01, 0x31, 0x07 }, { vpermpd ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0xd6, 0x07 }, { vpermq ymm2,ymm6,0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0xfd, 0x00, 0x31, 0x07 }, { vpermq ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0xd4 }, { vpermd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x36, 0x11 }, { vpermd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0xd4 }, { vpermps ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x16, 0x11 }, { vpermps ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0xd4 }, { vpsllvd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x47, 0x11 }, { vpsllvd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0xd4 }, { vpsllvq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x47, 0x11 }, { vpsllvq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0xd4 }, { vpsravd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x46, 0x11 }, { vpsravd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0xd4 }, { vpsrlvd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x45, 0x11 }, { vpsrlvd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0xd4 }, { vpsrlvq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xcd, 0x45, 0x11 }, { vpsrlvq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x2a, 0x21 }, { vmovntdqa ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x19, 0xf4 }, { vbroadcastsd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x18, 0xf4 }, { vbroadcastss ymm6,xmm4 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0xd4, 0x07 }, { vpblendd ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x02, 0x11, 0x07 }, { vpblendd ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0xd4, 0x07 }, { vperm2i128 ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x46, 0x11, 0x07 }, { vperm2i128 ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x07 }, { vinserti128 ymm6,ymm4,xmm4,0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x5d, 0x38, 0x31, 0x07 }, { vinserti128 ymm6,ymm4,OWORD [rcx],0x7 }
+testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x5a, 0x21 }, { vbroadcasti128 ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0xd4 }, { vpsllvd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x49, 0x47, 0x39 }, { vpsllvd xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0xd4 }, { vpsllvq xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x47, 0x39 }, { vpsllvq xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0xd4 }, { vpsravd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x49, 0x46, 0x39 }, { vpsravd xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0xd4 }, { vpsrlvd xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x49, 0x45, 0x39 }, { vpsrlvd xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0xd4 }, { vpsrlvq xmm2,xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xc9, 0x45, 0x39 }, { vpsrlvq xmm7,xmm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x59, 0x8c, 0x31 }, { vpmaskmovd xmm6,xmm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0xd9, 0x8c, 0x31 }, { vpmaskmovq xmm6,xmm4,OWORD [rcx] }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x07 }, { vextracti128 xmm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [rcx],ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x7d, 0x39, 0x21, 0x07 }, { vextracti128 OWORD [rcx],ymm4,0x7 }
+testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [rcx],xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x49, 0x8e, 0x21 }, { vpmaskmovd OWORD [rcx],xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [rcx],xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0xc9, 0x8e, 0x21 }, { vpmaskmovq OWORD [rcx],xmm6,xmm4 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0xd4, 0x07 }, { vpblendd xmm2,xmm6,xmm4,0x7 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x49, 0x02, 0x11, 0x07 }, { vpblendd xmm2,xmm6,OWORD [rcx],0x7 }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0xf4 }, { vpbroadcastq xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x59, 0x21 }, { vpbroadcastq xmm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0xf4 }, { vpbroadcastq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x59, 0x21 }, { vpbroadcastq ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0xe4 }, { vpbroadcastd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x58, 0x21 }, { vpbroadcastd ymm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0xf4 }, { vpbroadcastd xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x58, 0x21 }, { vpbroadcastd xmm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0xf4 }, { vpbroadcastw xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x79, 0x21 }, { vpbroadcastw xmm4,WORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0xf4 }, { vpbroadcastw ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x79, 0x21 }, { vpbroadcastw ymm4,WORD [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0xf4 }, { vpbroadcastb xmm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x78, 0x21 }, { vpbroadcastb xmm4,BYTE [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0xf4 }, { vpbroadcastb ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x78, 0x21 }, { vpbroadcastb ymm4,BYTE [rcx] }
+testcase { 0xc4, 0xe2, 0x79, 0x18, 0xf4 }, { vbroadcastss xmm6,xmm4 }
+
+; b/gas/testsuite/gas/i386/x86-64-avx256int-intel.d
+testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 }
+testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 }
+testcase { 0xc5, 0xed, 0x72, 0xf6, 0x07 }, { vpslld ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xfe, 0x07 }, { vpslldq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xf6, 0x07 }, { vpsllq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xf6, 0x07 }, { vpsllw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x72, 0xe6, 0x07 }, { vpsrad ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xe6, 0x07 }, { vpsraw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x72, 0xd6, 0x07 }, { vpsrld ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xde, 0x07 }, { vpsrldq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xd6, 0x07 }, { vpsrlq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xd6, 0x07 }, { vpsrlw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0xd6, 0x07 }, { vpshufd ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [rcx],0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0xd6, 0x07 }, { vpshufhw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [rcx],0x7 }
+testcase { 0xc5, 0xff, 0x70, 0xd6, 0x07 }, { vpshuflw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [rcx],0x7 }
+testcase { 0xc5, 0xcd, 0x6b, 0xd4 }, { vpackssdw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x63, 0xd4 }, { vpacksswb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0xd4 }, { vpackusdw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x67, 0xd4 }, { vpackuswb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfc, 0xd4 }, { vpaddb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfd, 0xd4 }, { vpaddw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfe, 0xd4 }, { vpaddd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd4, 0xd4 }, { vpaddq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xec, 0xd4 }, { vpaddsb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xed, 0xd4 }, { vpaddsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdc, 0xd4 }, { vpaddusb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdd, 0xd4 }, { vpaddusw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdb, 0xd4 }, { vpand ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdf, 0xd4 }, { vpandn ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe0, 0xd4 }, { vpavgb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe3, 0xd4 }, { vpavgw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x74, 0xd4 }, { vpcmpeqb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x75, 0xd4 }, { vpcmpeqw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x76, 0xd4 }, { vpcmpeqd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0xd4 }, { vpcmpeqq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x64, 0xd4 }, { vpcmpgtb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x65, 0xd4 }, { vpcmpgtw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x66, 0xd4 }, { vpcmpgtd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0xd4 }, { vpcmpgtq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0xd4 }, { vphaddw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0xd4 }, { vphaddd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0xd4 }, { vphaddsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0xd4 }, { vphsubw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0xd4 }, { vphsubd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0xd4 }, { vphsubsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf5, 0xd4 }, { vpmaddwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0xd4 }, { vpmaddubsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0xd4 }, { vpmaxsb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xee, 0xd4 }, { vpmaxsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0xd4 }, { vpmaxsd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xde, 0xd4 }, { vpmaxub ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0xd4 }, { vpmaxuw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0xd4 }, { vpmaxud ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0xd4 }, { vpminsb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xea, 0xd4 }, { vpminsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0xd4 }, { vpminsd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xda, 0xd4 }, { vpminub ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0xd4 }, { vpminuw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0xd4 }, { vpminud ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe4, 0xd4 }, { vpmulhuw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0xd4 }, { vpmulhrsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe5, 0xd4 }, { vpmulhw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd5, 0xd4 }, { vpmullw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0xd4 }, { vpmulld ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf4, 0xd4 }, { vpmuludq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0xd4 }, { vpmuldq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xeb, 0xd4 }, { vpor ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf6, 0xd4 }, { vpsadbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0xd4 }, { vpshufb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0xd4 }, { vpsignb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0xd4 }, { vpsignw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0xd4 }, { vpsignd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf8, 0xd4 }, { vpsubb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf9, 0xd4 }, { vpsubw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfa, 0xd4 }, { vpsubd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfb, 0xd4 }, { vpsubq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe8, 0xd4 }, { vpsubsb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe9, 0xd4 }, { vpsubsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd8, 0xd4 }, { vpsubusb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd9, 0xd4 }, { vpsubusw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x68, 0xd4 }, { vpunpckhbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x69, 0xd4 }, { vpunpckhwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6a, 0xd4 }, { vpunpckhdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6d, 0xd4 }, { vpunpckhqdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x60, 0xd4 }, { vpunpcklbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x61, 0xd4 }, { vpunpcklwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x62, 0xd4 }, { vpunpckldq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6c, 0xd4 }, { vpunpcklqdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xef, 0xd4 }, { vpxor ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0xf4 }, { vpabsb ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0xf4 }, { vpabsw ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0xf4 }, { vpabsd ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x07 }, { vmpsadbw ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0xd4, 0x07 }, { vpalignr ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0xd4, 0x07 }, { vpblendw ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0xfe, 0x40 }, { vpblendvb ymm7,ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [rcx],ymm4 }
+testcase { 0xc5, 0xcd, 0xf1, 0xd4 }, { vpsllw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf2, 0xd4 }, { vpslld ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf3, 0xd4 }, { vpsllq ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe1, 0xd4 }, { vpsraw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe2, 0xd4 }, { vpsrad ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd1, 0xd4 }, { vpsrlw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd2, 0xd4 }, { vpsrld ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd3, 0xd4 }, { vpsrlq ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0xe4 }, { vpmovsxbw ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0xe4 }, { vpmovsxwd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0xe4 }, { vpmovsxdq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0xe4 }, { vpmovzxbw ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0xe4 }, { vpmovzxwd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0xe4 }, { vpmovzxdq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0xf4 }, { vpmovsxbd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0xf4 }, { vpmovsxwq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0xf4 }, { vpmovzxbd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0xf4 }, { vpmovzxwq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0xe4 }, { vpmovsxbq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0xe4 }, { vpmovzxbq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [rcx] }
+testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 }
+testcase { 0xc5, 0xfd, 0xd7, 0xcc }, { vpmovmskb ecx,ymm4 }
+testcase { 0xc5, 0xed, 0x72, 0xf6, 0x07 }, { vpslld ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xfe, 0x07 }, { vpslldq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xf6, 0x07 }, { vpsllq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xf6, 0x07 }, { vpsllw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x72, 0xe6, 0x07 }, { vpsrad ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xe6, 0x07 }, { vpsraw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x72, 0xd6, 0x07 }, { vpsrld ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xde, 0x07 }, { vpsrldq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x73, 0xd6, 0x07 }, { vpsrlq ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xed, 0x71, 0xd6, 0x07 }, { vpsrlw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0xd6, 0x07 }, { vpshufd ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [rcx],0x7 }
+testcase { 0xc5, 0xfd, 0x70, 0x31, 0x07 }, { vpshufd ymm6,YWORD [rcx],0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0xd6, 0x07 }, { vpshufhw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [rcx],0x7 }
+testcase { 0xc5, 0xfe, 0x70, 0x31, 0x07 }, { vpshufhw ymm6,YWORD [rcx],0x7 }
+testcase { 0xc5, 0xff, 0x70, 0xd6, 0x07 }, { vpshuflw ymm2,ymm6,0x7 }
+testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [rcx],0x7 }
+testcase { 0xc5, 0xff, 0x70, 0x31, 0x07 }, { vpshuflw ymm6,YWORD [rcx],0x7 }
+testcase { 0xc5, 0xcd, 0x6b, 0xd4 }, { vpackssdw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6b, 0x11 }, { vpackssdw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x63, 0xd4 }, { vpacksswb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x63, 0x11 }, { vpacksswb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0xd4 }, { vpackusdw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x2b, 0x11 }, { vpackusdw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x67, 0xd4 }, { vpackuswb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x67, 0x11 }, { vpackuswb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfc, 0xd4 }, { vpaddb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfc, 0x11 }, { vpaddb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfd, 0xd4 }, { vpaddw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfd, 0x11 }, { vpaddw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfe, 0xd4 }, { vpaddd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfe, 0x11 }, { vpaddd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd4, 0xd4 }, { vpaddq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd4, 0x11 }, { vpaddq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xec, 0xd4 }, { vpaddsb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xec, 0x11 }, { vpaddsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xed, 0xd4 }, { vpaddsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xed, 0x11 }, { vpaddsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdc, 0xd4 }, { vpaddusb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdc, 0x11 }, { vpaddusb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdd, 0xd4 }, { vpaddusw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdd, 0x11 }, { vpaddusw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdb, 0xd4 }, { vpand ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdb, 0x11 }, { vpand ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdf, 0xd4 }, { vpandn ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xdf, 0x11 }, { vpandn ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe0, 0xd4 }, { vpavgb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe0, 0x11 }, { vpavgb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe3, 0xd4 }, { vpavgw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe3, 0x11 }, { vpavgw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x74, 0xd4 }, { vpcmpeqb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x74, 0x11 }, { vpcmpeqb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x75, 0xd4 }, { vpcmpeqw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x75, 0x11 }, { vpcmpeqw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x76, 0xd4 }, { vpcmpeqd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x76, 0x11 }, { vpcmpeqd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0xd4 }, { vpcmpeqq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x29, 0x11 }, { vpcmpeqq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x64, 0xd4 }, { vpcmpgtb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x64, 0x11 }, { vpcmpgtb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x65, 0xd4 }, { vpcmpgtw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x65, 0x11 }, { vpcmpgtw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x66, 0xd4 }, { vpcmpgtd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x66, 0x11 }, { vpcmpgtd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0xd4 }, { vpcmpgtq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x37, 0x11 }, { vpcmpgtq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0xd4 }, { vphaddw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x01, 0x11 }, { vphaddw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0xd4 }, { vphaddd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x02, 0x11 }, { vphaddd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0xd4 }, { vphaddsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x03, 0x11 }, { vphaddsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0xd4 }, { vphsubw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x05, 0x11 }, { vphsubw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0xd4 }, { vphsubd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x06, 0x11 }, { vphsubd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0xd4 }, { vphsubsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x07, 0x11 }, { vphsubsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf5, 0xd4 }, { vpmaddwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf5, 0x11 }, { vpmaddwd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0xd4 }, { vpmaddubsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x04, 0x11 }, { vpmaddubsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0xd4 }, { vpmaxsb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3c, 0x11 }, { vpmaxsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xee, 0xd4 }, { vpmaxsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xee, 0x11 }, { vpmaxsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0xd4 }, { vpmaxsd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3d, 0x11 }, { vpmaxsd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xde, 0xd4 }, { vpmaxub ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xde, 0x11 }, { vpmaxub ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0xd4 }, { vpmaxuw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3e, 0x11 }, { vpmaxuw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0xd4 }, { vpmaxud ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3f, 0x11 }, { vpmaxud ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0xd4 }, { vpminsb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x38, 0x11 }, { vpminsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xea, 0xd4 }, { vpminsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xea, 0x11 }, { vpminsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0xd4 }, { vpminsd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x39, 0x11 }, { vpminsd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xda, 0xd4 }, { vpminub ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xda, 0x11 }, { vpminub ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0xd4 }, { vpminuw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3a, 0x11 }, { vpminuw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0xd4 }, { vpminud ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x3b, 0x11 }, { vpminud ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe4, 0xd4 }, { vpmulhuw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe4, 0x11 }, { vpmulhuw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0xd4 }, { vpmulhrsw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0b, 0x11 }, { vpmulhrsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe5, 0xd4 }, { vpmulhw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe5, 0x11 }, { vpmulhw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd5, 0xd4 }, { vpmullw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd5, 0x11 }, { vpmullw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0xd4 }, { vpmulld ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x40, 0x11 }, { vpmulld ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf4, 0xd4 }, { vpmuludq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf4, 0x11 }, { vpmuludq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0xd4 }, { vpmuldq ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x28, 0x11 }, { vpmuldq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xeb, 0xd4 }, { vpor ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xeb, 0x11 }, { vpor ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf6, 0xd4 }, { vpsadbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf6, 0x11 }, { vpsadbw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0xd4 }, { vpshufb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x00, 0x11 }, { vpshufb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0xd4 }, { vpsignb ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x08, 0x11 }, { vpsignb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0xd4 }, { vpsignw ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x09, 0x11 }, { vpsignw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0xd4 }, { vpsignd ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x4d, 0x0a, 0x11 }, { vpsignd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf8, 0xd4 }, { vpsubb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf8, 0x11 }, { vpsubb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf9, 0xd4 }, { vpsubw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf9, 0x11 }, { vpsubw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfa, 0xd4 }, { vpsubd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfa, 0x11 }, { vpsubd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfb, 0xd4 }, { vpsubq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xfb, 0x11 }, { vpsubq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe8, 0xd4 }, { vpsubsb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe8, 0x11 }, { vpsubsb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe9, 0xd4 }, { vpsubsw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe9, 0x11 }, { vpsubsw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd8, 0xd4 }, { vpsubusb ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd8, 0x11 }, { vpsubusb ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd9, 0xd4 }, { vpsubusw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd9, 0x11 }, { vpsubusw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x68, 0xd4 }, { vpunpckhbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x68, 0x11 }, { vpunpckhbw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x69, 0xd4 }, { vpunpckhwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x69, 0x11 }, { vpunpckhwd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6a, 0xd4 }, { vpunpckhdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6a, 0x11 }, { vpunpckhdq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6d, 0xd4 }, { vpunpckhqdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6d, 0x11 }, { vpunpckhqdq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x60, 0xd4 }, { vpunpcklbw ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x60, 0x11 }, { vpunpcklbw ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x61, 0xd4 }, { vpunpcklwd ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x61, 0x11 }, { vpunpcklwd ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x62, 0xd4 }, { vpunpckldq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x62, 0x11 }, { vpunpckldq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6c, 0xd4 }, { vpunpcklqdq ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0x6c, 0x11 }, { vpunpcklqdq ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xef, 0xd4 }, { vpxor ymm2,ymm6,ymm4 }
+testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xef, 0x11 }, { vpxor ymm2,ymm6,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0xf4 }, { vpabsb ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1c, 0x21 }, { vpabsb ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0xf4 }, { vpabsw ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1d, 0x21 }, { vpabsw ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0xf4 }, { vpabsd ymm6,ymm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x1e, 0x21 }, { vpabsd ymm4,YWORD [rcx] }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x07 }, { vmpsadbw ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x42, 0x11, 0x07 }, { vmpsadbw ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0xd4, 0x07 }, { vpalignr ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0f, 0x11, 0x07 }, { vpalignr ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0xd4, 0x07 }, { vpblendw ymm2,ymm6,ymm4,0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x4d, 0x0e, 0x11, 0x07 }, { vpblendw ymm2,ymm6,YWORD [rcx],0x7 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0xfe, 0x40 }, { vpblendvb ymm7,ymm2,ymm6,ymm4 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [rcx],ymm4 }
+testcase { 0xc4, 0xe3, 0x6d, 0x4c, 0x39, 0x40 }, { vpblendvb ymm7,ymm2,YWORD [rcx],ymm4 }
+testcase { 0xc5, 0xcd, 0xf1, 0xd4 }, { vpsllw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf1, 0x11 }, { vpsllw ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf2, 0xd4 }, { vpslld ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf2, 0x11 }, { vpslld ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf3, 0xd4 }, { vpsllq ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xf3, 0x11 }, { vpsllq ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe1, 0xd4 }, { vpsraw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe1, 0x11 }, { vpsraw ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe2, 0xd4 }, { vpsrad ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xe2, 0x11 }, { vpsrad ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd1, 0xd4 }, { vpsrlw ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd1, 0x11 }, { vpsrlw ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd2, 0xd4 }, { vpsrld ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd2, 0x11 }, { vpsrld ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd3, 0xd4 }, { vpsrlq ymm2,ymm6,xmm4 }
+testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc5, 0xcd, 0xd3, 0x11 }, { vpsrlq ymm2,ymm6,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0xe4 }, { vpmovsxbw ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x20, 0x21 }, { vpmovsxbw ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0xe4 }, { vpmovsxwd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x23, 0x21 }, { vpmovsxwd ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0xe4 }, { vpmovsxdq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x25, 0x21 }, { vpmovsxdq ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0xe4 }, { vpmovzxbw ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x30, 0x21 }, { vpmovzxbw ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0xe4 }, { vpmovzxwd ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x33, 0x21 }, { vpmovzxwd ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0xe4 }, { vpmovzxdq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x35, 0x21 }, { vpmovzxdq ymm4,OWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0xf4 }, { vpmovsxbd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x21, 0x21 }, { vpmovsxbd ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0xf4 }, { vpmovsxwq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x24, 0x21 }, { vpmovsxwq ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0xf4 }, { vpmovzxbd ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x31, 0x21 }, { vpmovzxbd ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0xf4 }, { vpmovzxwq ymm6,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x34, 0x21 }, { vpmovzxwq ymm4,QWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0xe4 }, { vpmovsxbq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x22, 0x21 }, { vpmovsxbq ymm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0xe4 }, { vpmovzxbq ymm4,xmm4 }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [rcx] }
+testcase { 0xc4, 0xe2, 0x7d, 0x32, 0x21 }, { vpmovzxbq ymm4,DWORD [rcx] }
+
+; EOF
diff --git a/travis/test/avx2.bin.t b/travis/test/avx2.bin.t
new file mode 100644
index 00000000..60977f36
--- /dev/null
+++ b/travis/test/avx2.bin.t
Binary files differ
diff --git a/travis/test/avx2.json b/travis/test/avx2.json
new file mode 100644
index 00000000..3f9cb764
--- /dev/null
+++ b/travis/test/avx2.json
@@ -0,0 +1,11 @@
+[
+ {
+ "description": "Test AVX2 instructions (from gas testsuite)",
+ "id": "avx2",
+ "source": "avx2.asm",
+ "option": "-DSRC -Ox",
+ "target": [
+ { "output": "avx2.bin" }
+ ]
+ }
+]
diff --git a/travis/test/br3104312.asm b/travis/test/br3104312.asm
new file mode 100644
index 00000000..3b9509bd
--- /dev/null
+++ b/travis/test/br3104312.asm
@@ -0,0 +1,11 @@
+%if 1 < 8000_0002h
+ %warning No bug with 8000_0002h
+%else
+ %warning Bug with 8000_0002h
+%endif
+
+%if 1 < 8000_0001h
+ %warning No bug with 8000_0001h
+%else
+ %warning Bug with 8000_0001h
+%endif
diff --git a/travis/test/br3104312.json b/travis/test/br3104312.json
new file mode 100644
index 00000000..17358171
--- /dev/null
+++ b/travis/test/br3104312.json
@@ -0,0 +1,11 @@
+[
+ {
+ "description": "Test 8000_0001h and 8000_0002h bugs",
+ "id": "br3104312",
+ "source": "br3104312.asm",
+ "option": "-E",
+ "target": [
+ { "stderr": "br3104312.stderr" }
+ ]
+ }
+]
diff --git a/travis/test/br3104312.stderr b/travis/test/br3104312.stderr
new file mode 100644
index 00000000..a7fbdb69
--- /dev/null
+++ b/travis/test/br3104312.stderr
@@ -0,0 +1,2 @@
+./travis/test/br3104312.asm:2: warning: No bug with 8000_0002h [-w+user]
+./travis/test/br3104312.asm:8: warning: No bug with 8000_0001h [-w+user] \ No newline at end of file
diff --git a/travis/test/br3392275.asm b/travis/test/br3392275.asm
new file mode 100644
index 00000000..c37343d4
--- /dev/null
+++ b/travis/test/br3392275.asm
@@ -0,0 +1,10 @@
+ bits 32
+
+ blendvpd xmm2,xmm1,xmm0
+ blendvpd xmm2,xmm1
+ blendvps xmm2,xmm1,xmm0
+ blendvps xmm2,xmm1
+ pblendvb xmm2,xmm1,xmm0
+ pblendvb xmm2,xmm1
+ sha256rnds2 xmm2,xmm1,xmm0
+ sha256rnds2 xmm2,xmm1
diff --git a/travis/test/br3392275.bin.t b/travis/test/br3392275.bin.t
new file mode 100644
index 00000000..9f704492
--- /dev/null
+++ b/travis/test/br3392275.bin.t
@@ -0,0 +1 @@
+f8f8f8f8f8f888 \ No newline at end of file
diff --git a/travis/test/br3392275.json b/travis/test/br3392275.json
new file mode 100644
index 00000000..3d48812d
--- /dev/null
+++ b/travis/test/br3392275.json
@@ -0,0 +1,12 @@
+[
+ {
+ "id": "br3392275",
+ "description": "Do not require xmm0 to be explicitly declared when implicit",
+ "format": "bin",
+ "source": "br3392275.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "br3392275.bin" }
+ ]
+ }
+]
diff --git a/travis/test/br3392363.asm b/travis/test/br3392363.asm
new file mode 100644
index 00000000..e098bdd2
--- /dev/null
+++ b/travis/test/br3392363.asm
@@ -0,0 +1,5 @@
+ bits 64
+ vaddps zmm0 {k1}, zmm0, zmm0
+ rep
+ vaddps zmm0 {k1}, zmm0, zmm0
+ rep movsd
diff --git a/travis/test/br3392363.bin.t b/travis/test/br3392363.bin.t
new file mode 100644
index 00000000..ddee9535
--- /dev/null
+++ b/travis/test/br3392363.bin.t
@@ -0,0 +1 @@
+b|IXb|IX \ No newline at end of file
diff --git a/travis/test/br3392363.json b/travis/test/br3392363.json
new file mode 100644
index 00000000..021bfbb5
--- /dev/null
+++ b/travis/test/br3392363.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Test br3392363",
+ "id": "br3392363",
+ "format": "bin",
+ "source": "br3392363.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "br3392363.bin" }
+ ]
+ }
+]
diff --git a/travis/test/br3392392.asm b/travis/test/br3392392.asm
new file mode 100644
index 00000000..8a52da67
--- /dev/null
+++ b/travis/test/br3392392.asm
@@ -0,0 +1,15 @@
+ bits 64
+ vpaddd zmm0, zmm0, [rax]{1to16}
+ vpaddd zmm2{k3}, zmm0, zmm1
+ vpaddd zmm2 {k3}, zmm0, zmm1
+ vpaddd zmm0{k1}, zmm0, [rax]{1to16}
+ vmovdqa32 [rsi]{k1}, zmm1
+ vmovdqa32 [rsi]{z}, zmm1
+ vmovdqa32 [rsi]{k1}{z}, zmm1
+ vmovdqa32 [rsi]{z}{k1}, zmm1
+%ifdef ERROR
+ vmovdqa32 [rsi]{z}{1to16}, zmm1
+ vmovdqa32 [rsi]{z}{k1}{1to16}, zmm1
+ vpaddd zmm0, zmm0, [rax]{k1}
+ vpaddd zmm0, zmm1, zmm2{1to16}
+%endif
diff --git a/travis/test/br3392392.bin.t b/travis/test/br3392392.bin.t
new file mode 100644
index 00000000..f0b476db
--- /dev/null
+++ b/travis/test/br3392392.bin.t
Binary files differ
diff --git a/travis/test/br3392392.json b/travis/test/br3392392.json
new file mode 100644
index 00000000..42fa96ec
--- /dev/null
+++ b/travis/test/br3392392.json
@@ -0,0 +1,21 @@
+[
+ {
+ "description": "Test br3392392",
+ "id": "br3392392",
+ "format": "bin",
+ "source": "br3392392.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "br3392392.bin" }
+ ]
+ },
+ {
+ "description": "Test br3392392 (error)",
+ "ref": "br3392392",
+ "option": "-DERROR -o br3392392.bin",
+ "target": [
+ { "stderr": "br3392392.stderr" }
+ ],
+ "error": "expected"
+ }
+]
diff --git a/travis/test/br3392392.stderr b/travis/test/br3392392.stderr
new file mode 100644
index 00000000..a40a0d48
--- /dev/null
+++ b/travis/test/br3392392.stderr
@@ -0,0 +1 @@
+./travis/test/br3392392.asm:14: error: broadcast not allowed with register operand \ No newline at end of file
diff --git a/travis/test/br3392396.asm b/travis/test/br3392396.asm
new file mode 100644
index 00000000..beb71cf1
--- /dev/null
+++ b/travis/test/br3392396.asm
@@ -0,0 +1,5 @@
+ bits 64
+ vmovdqa32 [rdi],zmm16
+ vmovdqa32 [rdi+64],zmm17
+ vmovdqa32 [rdi+128],zmm18
+ vmovdqa32 [rdi+192],zmm19
diff --git a/travis/test/br3392396.bin.t b/travis/test/br3392396.bin.t
new file mode 100644
index 00000000..43c24a13
--- /dev/null
+++ b/travis/test/br3392396.bin.t
@@ -0,0 +1 @@
+b}Hb}HOb}HWb}H_ \ No newline at end of file
diff --git a/travis/test/br3392396.json b/travis/test/br3392396.json
new file mode 100644
index 00000000..a06f4ca9
--- /dev/null
+++ b/travis/test/br3392396.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Test br3392396",
+ "id": "br3392396",
+ "format": "bin",
+ "source": "br3392396.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "br3392396.bin" }
+ ]
+ }
+]
diff --git a/travis/test/br3392411.asm b/travis/test/br3392411.asm
new file mode 100644
index 00000000..56b9706b
--- /dev/null
+++ b/travis/test/br3392411.asm
@@ -0,0 +1,22 @@
+bits 64
+default rel
+
+%use smartalign
+
+section .text code align=32
+
+align 32
+
+nop
+jz LDone
+
+%rep 10
+ nop
+%endrep
+
+align 16
+%rep 115
+ nop
+%endrep
+
+LDone:
diff --git a/travis/test/br3392411.json b/travis/test/br3392411.json
new file mode 100644
index 00000000..27264e6b
--- /dev/null
+++ b/travis/test/br3392411.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Description of a test",
+ "id": "br3392411",
+ "format": "win64",
+ "source": "br3392411.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "br3392411.out" }
+ ]
+ }
+]
diff --git a/travis/test/br3392411.out.t b/travis/test/br3392411.out.t
new file mode 100644
index 00000000..6fa66e82
--- /dev/null
+++ b/travis/test/br3392411.out.t
Binary files differ
diff --git a/travis/test/br3392643.obj.t b/travis/test/br3392643.obj.t
index de1dafbb..28fbb387 100644
--- a/travis/test/br3392643.obj.t
+++ b/travis/test/br3392643.obj.t
Binary files differ
diff --git a/travis/test/elif.o.t b/travis/test/elif.o.t
index 60336dcd..89787192 100644
--- a/travis/test/elif.o.t
+++ b/travis/test/elif.o.t
Binary files differ
diff --git a/travis/test/ifid.asm b/travis/test/ifid.asm
new file mode 100644
index 00000000..ffe03d27
--- /dev/null
+++ b/travis/test/ifid.asm
@@ -0,0 +1,19 @@
+; BR 3392715: Test proper operation of %ifid with $ and $$
+; This produces a human-readable file when compiled with -f bin
+
+%define LF 10
+
+%macro ifid 2
+ %ifid %1
+ %define %%is 'true'
+ %else
+ %define %%is 'false'
+ %endif
+ %defstr %%what %1
+ %defstr %%should %2
+ db '%ifid ', %%what, ' = ', %%is, ' (expect ', %%should, ')', LF
+%endmacro
+
+ ifid hello, true
+ ifid $, false
+ ifid $$, false
diff --git a/travis/test/ifid.bin.t b/travis/test/ifid.bin.t
new file mode 100644
index 00000000..ca86592d
--- /dev/null
+++ b/travis/test/ifid.bin.t
@@ -0,0 +1,3 @@
+%ifid hello = true (expect true)
+%ifid $ = false (expect false)
+%ifid $$ = false (expect false)
diff --git a/travis/test/ifid.json b/travis/test/ifid.json
new file mode 100644
index 00000000..cf1a3854
--- /dev/null
+++ b/travis/test/ifid.json
@@ -0,0 +1,11 @@
+[
+ {
+ "description": "BR 3392715: Test proper operation of %ifid with $ and $$",
+ "id": "ifid",
+ "format": "bin",
+ "source": "ifid.asm",
+ "target": [
+ { "output": "ifid.bin" }
+ ]
+ }
+]
diff --git a/travis/test/lwp.asm b/travis/test/lwp.asm
new file mode 100644
index 00000000..4b2bdc9b
--- /dev/null
+++ b/travis/test/lwp.asm
@@ -0,0 +1,213 @@
+; LWP testcases from 2010/03/22 binutils change: no more 16-bit variants
+;------------------------------------------------------------------------
+
+%define testcase3(x) x
+%define testcase3(x,y) y,x
+%define testcase3(x,y,z) z,y,x
+
+%macro testcase 3.nolist ; uncomment one of the two, and compare the -f bin and -l output between them
+%ifdef BIN
+ db %1
+%endif
+%ifdef SRC
+ %2 testcase3(%3)
+%endif
+%endmacro
+
+bits 32
+
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc0 }, { llwpcb }, { eax }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc1 }, { llwpcb }, { ecx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc2 }, { llwpcb }, { edx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc3 }, { llwpcb }, { ebx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc4 }, { llwpcb }, { esp }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc5 }, { llwpcb }, { ebp }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc6 }, { llwpcb }, { esi }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc7 }, { llwpcb }, { edi }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcf }, { slwpcb }, { edi }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xce }, { slwpcb }, { esi }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcd }, { slwpcb }, { ebp }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcc }, { slwpcb }, { esp }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcb }, { slwpcb }, { ebx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xca }, { slwpcb }, { edx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc9 }, { slwpcb }, { ecx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc8 }, { slwpcb }, { eax }
+testcase { 0x8f, 0xea, 0x78, 0x12, 0xc7, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,edi,eax }
+testcase { 0x8f, 0xea, 0x70, 0x12, 0xc6, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,esi,ecx }
+testcase { 0x8f, 0xea, 0x68, 0x12, 0xc5, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ebp,edx }
+testcase { 0x8f, 0xea, 0x60, 0x12, 0xc4, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,esp,ebx }
+testcase { 0x8f, 0xea, 0x58, 0x12, 0xc3, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ebx,esp }
+testcase { 0x8f, 0xea, 0x50, 0x12, 0xc2, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,edx,ebp }
+testcase { 0x8f, 0xea, 0x48, 0x12, 0xc1, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ecx,esi }
+testcase { 0x8f, 0xea, 0x40, 0x12, 0xc0, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,eax,edi }
+testcase { 0x8f, 0xea, 0x78, 0x12, 0xcf, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,edi,eax }
+testcase { 0x8f, 0xea, 0x70, 0x12, 0xce, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,esi,ecx }
+testcase { 0x8f, 0xea, 0x68, 0x12, 0xcd, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ebp,edx }
+testcase { 0x8f, 0xea, 0x60, 0x12, 0xcc, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,esp,ebx }
+testcase { 0x8f, 0xea, 0x58, 0x12, 0xcb, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ebx,esp }
+testcase { 0x8f, 0xea, 0x50, 0x12, 0xca, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,edx,ebp }
+testcase { 0x8f, 0xea, 0x48, 0x12, 0xc9, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ecx,esi }
+testcase { 0x8f, 0xea, 0x40, 0x12, 0xc8, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,eax,edi }
+testcase { 0x8f, 0xea, 0x78, 0x12, 0x07, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[edi],eax }
+testcase { 0x8f, 0xea, 0x70, 0x12, 0x06, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[esi],ecx }
+testcase { 0x8f, 0xea, 0x68, 0x12, 0x45, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ebp],edx }
+testcase { 0x8f, 0xea, 0x60, 0x12, 0x04, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[esp],ebx }
+testcase { 0x8f, 0xea, 0x58, 0x12, 0x03, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ebx],esp }
+testcase { 0x8f, 0xea, 0x50, 0x12, 0x02, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[edx],ebp }
+testcase { 0x8f, 0xea, 0x48, 0x12, 0x01, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ecx],esi }
+testcase { 0x8f, 0xea, 0x40, 0x12, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[eax],edi }
+testcase { 0x8f, 0xea, 0x78, 0x12, 0x0f, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[edi],eax }
+testcase { 0x8f, 0xea, 0x70, 0x12, 0x0e, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[esi],ecx }
+testcase { 0x8f, 0xea, 0x68, 0x12, 0x4d, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ebp],edx }
+testcase { 0x8f, 0xea, 0x60, 0x12, 0x0c, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[esp],ebx }
+testcase { 0x8f, 0xea, 0x58, 0x12, 0x0b, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ebx],esp }
+testcase { 0x8f, 0xea, 0x50, 0x12, 0x0a, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[edx],ebp }
+testcase { 0x8f, 0xea, 0x48, 0x12, 0x09, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ecx],esi }
+testcase { 0x8f, 0xea, 0x40, 0x12, 0x08, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[eax],edi }
+testcase { 0x8f, 0xea, 0x78, 0x12, 0x87, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+edi],eax }
+testcase { 0x8f, 0xea, 0x70, 0x12, 0x86, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+esi],ecx }
+testcase { 0x8f, 0xea, 0x68, 0x12, 0x85, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ebp],edx }
+testcase { 0x8f, 0xea, 0x60, 0x12, 0x84, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+esp],ebx }
+testcase { 0x8f, 0xea, 0x58, 0x12, 0x83, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ebx],esp }
+testcase { 0x8f, 0xea, 0x50, 0x12, 0x82, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+edx],ebp }
+testcase { 0x8f, 0xea, 0x48, 0x12, 0x81, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ecx],esi }
+testcase { 0x8f, 0xea, 0x40, 0x12, 0x80, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+eax],edi }
+testcase { 0x8f, 0xea, 0x78, 0x12, 0x8f, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+edi],eax }
+testcase { 0x8f, 0xea, 0x70, 0x12, 0x8e, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+esi],ecx }
+testcase { 0x8f, 0xea, 0x68, 0x12, 0x8d, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ebp],edx }
+testcase { 0x8f, 0xea, 0x60, 0x12, 0x8c, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+esp],ebx }
+testcase { 0x8f, 0xea, 0x58, 0x12, 0x8b, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ebx],esp }
+testcase { 0x8f, 0xea, 0x50, 0x12, 0x8a, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+edx],ebp }
+testcase { 0x8f, 0xea, 0x48, 0x12, 0x89, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ecx],esi }
+testcase { 0x8f, 0xea, 0x40, 0x12, 0x88, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+eax],edi }
+
+bits 64
+
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc0 }, { llwpcb }, { eax }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc1 }, { llwpcb }, { ecx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc2 }, { llwpcb }, { edx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc3 }, { llwpcb }, { ebx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc4 }, { llwpcb }, { esp }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc5 }, { llwpcb }, { ebp }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc6 }, { llwpcb }, { esi }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc7 }, { llwpcb }, { edi }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc0 }, { llwpcb }, { r8d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc1 }, { llwpcb }, { r9d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc2 }, { llwpcb }, { r10d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc3 }, { llwpcb }, { r11d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc4 }, { llwpcb }, { r12d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc5 }, { llwpcb }, { r13d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc6 }, { llwpcb }, { r14d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc7 }, { llwpcb }, { r15d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xcf }, { slwpcb }, { r15d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xce }, { slwpcb }, { r14d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xcd }, { slwpcb }, { r13d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xcc }, { slwpcb }, { r12d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xcb }, { slwpcb }, { r11d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xca }, { slwpcb }, { r10d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc9 }, { slwpcb }, { r9d }
+testcase { 0x8f, 0xc9, 0x78, 0x12, 0xc8 }, { slwpcb }, { r8d }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcf }, { slwpcb }, { edi }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xce }, { slwpcb }, { esi }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcd }, { slwpcb }, { ebp }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcc }, { slwpcb }, { esp }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xcb }, { slwpcb }, { ebx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xca }, { slwpcb }, { edx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc9 }, { slwpcb }, { ecx }
+testcase { 0x8f, 0xe9, 0x78, 0x12, 0xc8 }, { slwpcb }, { eax }
+testcase { 0x8f, 0xca, 0x78, 0x12, 0xc7, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r15d,eax }
+testcase { 0x8f, 0xca, 0x70, 0x12, 0xc6, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r14d,ecx }
+testcase { 0x8f, 0xca, 0x68, 0x12, 0xc5, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r13d,edx }
+testcase { 0x8f, 0xca, 0x60, 0x12, 0xc4, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r12d,ebx }
+testcase { 0x8f, 0xca, 0x58, 0x12, 0xc3, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r11d,esp }
+testcase { 0x8f, 0xca, 0x50, 0x12, 0xc2, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r10d,ebp }
+testcase { 0x8f, 0xca, 0x48, 0x12, 0xc1, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r9d,esi }
+testcase { 0x8f, 0xca, 0x40, 0x12, 0xc0, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,r8d,edi }
+testcase { 0x8f, 0xea, 0x38, 0x12, 0xc7, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,edi,r8d }
+testcase { 0x8f, 0xea, 0x30, 0x12, 0xc6, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,esi,r9d }
+testcase { 0x8f, 0xea, 0x28, 0x12, 0xc5, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ebp,r10d }
+testcase { 0x8f, 0xea, 0x20, 0x12, 0xc4, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,esp,r11d }
+testcase { 0x8f, 0xea, 0x18, 0x12, 0xc3, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ebx,r12d }
+testcase { 0x8f, 0xea, 0x10, 0x12, 0xc2, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,edx,r13d }
+testcase { 0x8f, 0xea, 0x08, 0x12, 0xc1, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,ecx,r14d }
+testcase { 0x8f, 0xea, 0x00, 0x12, 0xc0, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,eax,r15d }
+testcase { 0x8f, 0xca, 0x78, 0x12, 0xcf, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r15d,eax }
+testcase { 0x8f, 0xca, 0x70, 0x12, 0xce, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r14d,ecx }
+testcase { 0x8f, 0xca, 0x68, 0x12, 0xcd, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r13d,edx }
+testcase { 0x8f, 0xca, 0x60, 0x12, 0xcc, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r12d,ebx }
+testcase { 0x8f, 0xca, 0x58, 0x12, 0xcb, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r11d,esp }
+testcase { 0x8f, 0xca, 0x50, 0x12, 0xca, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r10d,ebp }
+testcase { 0x8f, 0xca, 0x48, 0x12, 0xc9, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r9d,esi }
+testcase { 0x8f, 0xca, 0x40, 0x12, 0xc8, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,r8d,edi }
+testcase { 0x8f, 0xea, 0x38, 0x12, 0xcf, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,edi,r8d }
+testcase { 0x8f, 0xea, 0x30, 0x12, 0xce, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,esi,r9d }
+testcase { 0x8f, 0xea, 0x28, 0x12, 0xcd, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ebp,r10d }
+testcase { 0x8f, 0xea, 0x20, 0x12, 0xcc, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,esp,r11d }
+testcase { 0x8f, 0xea, 0x18, 0x12, 0xcb, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ebx,r12d }
+testcase { 0x8f, 0xea, 0x10, 0x12, 0xca, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,edx,r13d }
+testcase { 0x8f, 0xea, 0x08, 0x12, 0xc9, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,ecx,r14d }
+testcase { 0x8f, 0xea, 0x00, 0x12, 0xc8, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,eax,r15d }
+testcase { 0x67, 0x8f, 0xca, 0x78, 0x12, 0x07, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r15d],eax }
+testcase { 0x67, 0x8f, 0xca, 0x70, 0x12, 0x06, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r14d],ecx }
+testcase { 0x67, 0x8f, 0xca, 0x68, 0x12, 0x45, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r13d],edx }
+testcase { 0x67, 0x8f, 0xca, 0x60, 0x12, 0x04, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r12d],ebx }
+testcase { 0x67, 0x8f, 0xca, 0x58, 0x12, 0x03, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r11d],esp }
+testcase { 0x67, 0x8f, 0xca, 0x50, 0x12, 0x02, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r10d],ebp }
+testcase { 0x67, 0x8f, 0xca, 0x48, 0x12, 0x01, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r9d],esi }
+testcase { 0x67, 0x8f, 0xca, 0x40, 0x12, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[r8d],edi }
+testcase { 0x67, 0x8f, 0xea, 0x38, 0x12, 0x07, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[edi],r8d }
+testcase { 0x67, 0x8f, 0xea, 0x30, 0x12, 0x06, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[esi],r9d }
+testcase { 0x67, 0x8f, 0xea, 0x28, 0x12, 0x45, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ebp],r10d }
+testcase { 0x67, 0x8f, 0xea, 0x20, 0x12, 0x04, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[esp],r11d }
+testcase { 0x67, 0x8f, 0xea, 0x18, 0x12, 0x03, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ebx],r12d }
+testcase { 0x67, 0x8f, 0xea, 0x10, 0x12, 0x02, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[edx],r13d }
+testcase { 0x67, 0x8f, 0xea, 0x08, 0x12, 0x01, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[ecx],r14d }
+testcase { 0x67, 0x8f, 0xea, 0x00, 0x12, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[eax],r15d }
+testcase { 0x67, 0x8f, 0xca, 0x78, 0x12, 0x0f, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r15d],eax }
+testcase { 0x67, 0x8f, 0xca, 0x70, 0x12, 0x0e, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r14d],ecx }
+testcase { 0x67, 0x8f, 0xca, 0x68, 0x12, 0x4d, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r13d],edx }
+testcase { 0x67, 0x8f, 0xca, 0x60, 0x12, 0x0c, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r12d],ebx }
+testcase { 0x67, 0x8f, 0xca, 0x58, 0x12, 0x0b, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r11d],esp }
+testcase { 0x67, 0x8f, 0xca, 0x50, 0x12, 0x0a, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r10d],ebp }
+testcase { 0x67, 0x8f, 0xca, 0x48, 0x12, 0x09, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r9d],esi }
+testcase { 0x67, 0x8f, 0xca, 0x40, 0x12, 0x08, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[r8d],edi }
+testcase { 0x67, 0x8f, 0xea, 0x38, 0x12, 0x0f, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[edi],r8d }
+testcase { 0x67, 0x8f, 0xea, 0x30, 0x12, 0x0e, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[esi],r9d }
+testcase { 0x67, 0x8f, 0xea, 0x28, 0x12, 0x4d, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ebp],r10d }
+testcase { 0x67, 0x8f, 0xea, 0x20, 0x12, 0x0c, 0x24, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[esp],r11d }
+testcase { 0x67, 0x8f, 0xea, 0x18, 0x12, 0x0b, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ebx],r12d }
+testcase { 0x67, 0x8f, 0xea, 0x10, 0x12, 0x0a, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[edx],r13d }
+testcase { 0x67, 0x8f, 0xea, 0x08, 0x12, 0x09, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[ecx],r14d }
+testcase { 0x67, 0x8f, 0xea, 0x00, 0x12, 0x08, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[eax],r15d }
+testcase { 0x67, 0x8f, 0xca, 0x78, 0x12, 0x87, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r15d],eax }
+testcase { 0x67, 0x8f, 0xca, 0x70, 0x12, 0x86, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r14d],ecx }
+testcase { 0x67, 0x8f, 0xca, 0x68, 0x12, 0x85, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r13d],edx }
+testcase { 0x67, 0x8f, 0xca, 0x60, 0x12, 0x84, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r12d],ebx }
+testcase { 0x67, 0x8f, 0xca, 0x58, 0x12, 0x83, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r11d],esp }
+testcase { 0x67, 0x8f, 0xca, 0x50, 0x12, 0x82, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r10d],ebp }
+testcase { 0x67, 0x8f, 0xca, 0x48, 0x12, 0x81, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r9d],esi }
+testcase { 0x67, 0x8f, 0xca, 0x40, 0x12, 0x80, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+r8d],edi }
+testcase { 0x67, 0x8f, 0xea, 0x38, 0x12, 0x87, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+edi],r8d }
+testcase { 0x67, 0x8f, 0xea, 0x30, 0x12, 0x86, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+esi],r9d }
+testcase { 0x67, 0x8f, 0xea, 0x28, 0x12, 0x85, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ebp],r10d }
+testcase { 0x67, 0x8f, 0xea, 0x20, 0x12, 0x84, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+esp],r11d }
+testcase { 0x67, 0x8f, 0xea, 0x18, 0x12, 0x83, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ebx],r12d }
+testcase { 0x67, 0x8f, 0xea, 0x10, 0x12, 0x82, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+edx],r13d }
+testcase { 0x67, 0x8f, 0xea, 0x08, 0x12, 0x81, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+ecx],r14d }
+testcase { 0x67, 0x8f, 0xea, 0x00, 0x12, 0x80, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpins }, { 0x12345678,[0xcafe+eax],r15d }
+testcase { 0x67, 0x8f, 0xca, 0x78, 0x12, 0x8f, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r15d],eax }
+testcase { 0x67, 0x8f, 0xca, 0x70, 0x12, 0x8e, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r14d],ecx }
+testcase { 0x67, 0x8f, 0xca, 0x68, 0x12, 0x8d, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r13d],edx }
+testcase { 0x67, 0x8f, 0xca, 0x60, 0x12, 0x8c, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r12d],ebx }
+testcase { 0x67, 0x8f, 0xca, 0x58, 0x12, 0x8b, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r11d],esp }
+testcase { 0x67, 0x8f, 0xca, 0x50, 0x12, 0x8a, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r10d],ebp }
+testcase { 0x67, 0x8f, 0xca, 0x48, 0x12, 0x89, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r9d],esi }
+testcase { 0x67, 0x8f, 0xca, 0x40, 0x12, 0x88, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+r8d],edi }
+testcase { 0x67, 0x8f, 0xea, 0x38, 0x12, 0x8f, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+edi],r8d }
+testcase { 0x67, 0x8f, 0xea, 0x30, 0x12, 0x8e, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+esi],r9d }
+testcase { 0x67, 0x8f, 0xea, 0x28, 0x12, 0x8d, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ebp],r10d }
+testcase { 0x67, 0x8f, 0xea, 0x20, 0x12, 0x8c, 0x24, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+esp],r11d }
+testcase { 0x67, 0x8f, 0xea, 0x18, 0x12, 0x8b, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ebx],r12d }
+testcase { 0x67, 0x8f, 0xea, 0x10, 0x12, 0x8a, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+edx],r13d }
+testcase { 0x67, 0x8f, 0xea, 0x08, 0x12, 0x89, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+ecx],r14d }
+testcase { 0x67, 0x8f, 0xea, 0x00, 0x12, 0x88, 0xfe, 0xca, 0x00, 0x00, 0x78, 0x56, 0x34, 0x12 }, { lwpval }, { 0x12345678,[0xcafe+eax],r15d }
diff --git a/travis/test/lwp.bin.t b/travis/test/lwp.bin.t
new file mode 100644
index 00000000..13110779
--- /dev/null
+++ b/travis/test/lwp.bin.t
Binary files differ
diff --git a/travis/test/lwp.json b/travis/test/lwp.json
new file mode 100644
index 00000000..8a0dd562
--- /dev/null
+++ b/travis/test/lwp.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Test LWP instructions",
+ "id": "lwp",
+ "format": "bin",
+ "source": "lwp.asm",
+ "option": "-Ox -DSRC",
+ "target": [
+ { "output": "lwp.bin" }
+ ]
+ }
+]
diff --git a/travis/test/obj.o.t b/travis/test/obj.o.t
index a91f3ad1..b3607882 100644
--- a/travis/test/obj.o.t
+++ b/travis/test/obj.o.t
Binary files differ
diff --git a/travis/test/ret-16.stderr b/travis/test/ret-16.stderr
new file mode 100644
index 00000000..1994fe9d
--- /dev/null
+++ b/travis/test/ret-16.stderr
@@ -0,0 +1 @@
+./travis/test/ret.asm:18: error: expression syntax error \ No newline at end of file
diff --git a/travis/test/ret-32.stderr b/travis/test/ret-32.stderr
new file mode 100644
index 00000000..b971af0e
--- /dev/null
+++ b/travis/test/ret-32.stderr
@@ -0,0 +1 @@
+./travis/test/ret.asm:37: error: expression syntax error \ No newline at end of file
diff --git a/travis/test/ret-64.stderr b/travis/test/ret-64.stderr
new file mode 100644
index 00000000..f06987b3
--- /dev/null
+++ b/travis/test/ret-64.stderr
@@ -0,0 +1 @@
+./travis/test/ret.asm:53: error: expression syntax error \ No newline at end of file
diff --git a/travis/test/ret.asm b/travis/test/ret.asm
new file mode 100644
index 00000000..0606257e
--- /dev/null
+++ b/travis/test/ret.asm
@@ -0,0 +1,61 @@
+;; All the flavors of RET
+%ifndef ERROR
+ %define ERROR 0
+%endif
+
+%ifdef TEST_BITS_16
+ bits 16
+
+ ret
+ retn
+ retf
+ retw
+ retnw
+ retfw
+ retd
+ retnd
+ retfd
+%if ERROR
+ retq
+ retnq
+ retfq
+%endif
+%endif
+
+%ifdef TEST_BITS_32
+ bits 32
+
+ ret
+ retn
+ retf
+ retw
+ retnw
+ retfw
+ retd
+ retnd
+ retfd
+%if ERROR
+ retq
+ retnq
+ retfq
+%endif
+%endif
+
+%ifdef TEST_BITS_64
+ bits 64
+
+ ret
+ retn
+ retf ; Probably should have been RETFQ, but: legacy...
+ retw
+ retnw
+ retfw
+%if ERROR
+ retd
+ retnd
+%endif
+%endif
+ retfd
+ retq
+ retnq
+ retfq
diff --git a/travis/test/ret.bin.t b/travis/test/ret.bin.t
new file mode 100644
index 00000000..246929c8
--- /dev/null
+++ b/travis/test/ret.bin.t
@@ -0,0 +1 @@
+fffffffffH \ No newline at end of file
diff --git a/travis/test/ret.json b/travis/test/ret.json
new file mode 100644
index 00000000..ce1d2ca5
--- /dev/null
+++ b/travis/test/ret.json
@@ -0,0 +1,39 @@
+[
+ {
+ "description": "Test all the flavors of RET",
+ "id": "ret",
+ "format": "bin",
+ "source": "ret.asm",
+ "option": "-Ox -DTEST_BITS_16 -DTEST_BITS_32 -DTEST_BITS_64",
+ "target": [
+ { "output": "ret.bin" }
+ ]
+ },
+ {
+ "description": "Test all the flavors of RET (err 16 bit)",
+ "ref": "ret",
+ "option": "-DERROR -DTEST_BITS_16 -o ret.bin",
+ "target": [
+ { "stderr": "ret-16.stderr" }
+ ],
+ "error": "expected"
+ },
+ {
+ "description": "Test all the flavors of RET (err 32 bit)",
+ "ref": "ret",
+ "option": "-DERROR -DTEST_BITS_32 -o ret.bin",
+ "target": [
+ { "stderr": "ret-32.stderr" }
+ ],
+ "error": "expected"
+ },
+ {
+ "description": "Test all the flavors of RET (err 64 bit)",
+ "ref": "ret",
+ "option": "-DERROR -DTEST_BITS_64 -o ret.bin",
+ "target": [
+ { "stderr": "ret-64.stderr" }
+ ],
+ "error": "expected"
+ }
+]
diff --git a/travis/test/sreg.asm b/travis/test/sreg.asm
new file mode 100644
index 00000000..11449a50
--- /dev/null
+++ b/travis/test/sreg.asm
@@ -0,0 +1,65 @@
+ bits 64
+ mov es,rax
+ mov ss,rax
+ mov ds,rax
+ mov fs,rax
+ mov gs,rax
+ mov es,eax
+ mov ss,eax
+ mov ds,eax
+ mov fs,eax
+ mov gs,eax
+ mov es,ax
+ mov ss,ax
+ mov ds,ax
+ mov fs,ax
+ mov gs,ax
+ mov es,[rsi]
+ mov ss,[rsi]
+ mov ds,[rsi]
+ mov fs,[rsi]
+ mov gs,[rsi]
+ mov es,word [rsi]
+ mov ss,word [rsi]
+ mov ds,word [rsi]
+ mov fs,word [rsi]
+ mov gs,word [rsi]
+ mov es,qword [rsi]
+ mov ss,qword [rsi]
+ mov ds,qword [rsi]
+ mov fs,qword [rsi]
+ mov gs,qword [rsi]
+ mov rax,es
+ mov rax,cs
+ mov rax,ss
+ mov rax,ds
+ mov rax,fs
+ mov rax,gs
+ mov eax,es
+ mov eax,ss
+ mov eax,ds
+ mov eax,fs
+ mov eax,fs
+ mov ax,es
+ mov ax,ss
+ mov ax,ds
+ mov ax,fs
+ mov ax,gs
+ mov [rdi],es
+ mov [rdi],cs
+ mov [rdi],ss
+ mov [rdi],ds
+ mov [rdi],fs
+ mov [rdi],gs
+ mov word [rdi],es
+ mov word [rdi],cs
+ mov word [rdi],ss
+ mov word [rdi],ds
+ mov word [rdi],fs
+ mov word [rdi],gs
+ mov qword [rdi],es
+ mov qword [rdi],cs
+ mov qword [rdi],ss
+ mov qword [rdi],ds
+ mov qword [rdi],fs
+ mov qword [rdi],gs
diff --git a/travis/test/sreg.bin.t b/travis/test/sreg.bin.t
new file mode 100644
index 00000000..70f8319c
--- /dev/null
+++ b/travis/test/sreg.bin.t
@@ -0,0 +1 @@
+Ў؎Ў؎Ў؎&.&.HHHH&H.ȌЌ،Ќ،fffff'/'/HHHHH'H/ \ No newline at end of file
diff --git a/travis/test/sreg.json b/travis/test/sreg.json
new file mode 100644
index 00000000..703d4826
--- /dev/null
+++ b/travis/test/sreg.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Test segment registers in 64 bit mode",
+ "id": "sreg",
+ "format": "bin",
+ "source": "sreg.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "sreg.bin" }
+ ]
+ }
+]
diff --git a/travis/test/tmap.json b/travis/test/tmap.json
index 3978d998..a3b2829d 100644
--- a/travis/test/tmap.json
+++ b/travis/test/tmap.json
@@ -1,10 +1,12 @@
-{
- "description": "Test abuse the section flags which breaks NASM 0.98.37",
- "format": "elf",
- "source": "tmap.asm",
- "option": "-DLINUX",
- "target": [
- { "output": "tmap.o" },
- { "stderr": "tmap.o.stderr" }
- ]
-}
+[
+ {
+ "description": "Test abuse the section flags which breaks NASM 0.98.37",
+ "format": "elf",
+ "source": "tmap.asm",
+ "option": "-Ox -DLINUX",
+ "target": [
+ { "output": "tmap.o" },
+ { "stderr": "tmap.stderr" }
+ ]
+ }
+]
diff --git a/travis/test/tmap.o.stderr b/travis/test/tmap.stderr
index 3cf4d563..3cf4d563 100644
--- a/travis/test/tmap.o.stderr
+++ b/travis/test/tmap.stderr
diff --git a/travis/test/v4.asm b/travis/test/v4.asm
new file mode 100644
index 00000000..bf88fd86
--- /dev/null
+++ b/travis/test/v4.asm
@@ -0,0 +1,16 @@
+ bits 64
+
+ v4fmaddps zmm0,zmm1+3,[rax]
+ v4fnmaddps zmm2,zmm3,[rax]
+ v4fmaddss zmm4,zmm5+3,[rax]
+ v4fnmaddss zmm6,zmm7+3,[rax]
+
+ v4dpwssds zmm8,zmm9,[rax]
+ v4dpwssd zmm10,zmm11+3,[rax]
+ v4dpwssd zmm10+0,zmm11+3,[rax]
+
+%ifdef ERROR
+ v4dpwssd zmm10+1,zmm11+3,[rax]
+ v4dpwssd zmm10,zmm11+4,[rax]
+ v4dpwssd zmm10,zmm11+7,[rax]
+%endif
diff --git a/travis/test/v4.bin.t b/travis/test/v4.bin.t
new file mode 100644
index 00000000..fc94d407
--- /dev/null
+++ b/travis/test/v4.bin.t
Binary files differ
diff --git a/travis/test/v4.json b/travis/test/v4.json
new file mode 100644
index 00000000..99887cab
--- /dev/null
+++ b/travis/test/v4.json
@@ -0,0 +1,21 @@
+[
+ {
+ "description": "Test v4 instructions",
+ "id": "v4",
+ "format": "bin",
+ "source": "v4.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "v4.bin" }
+ ]
+ },
+ {
+ "description": "Test v4 instructions (error)",
+ "ref": "v4",
+ "option": "-DERROR -o v4.bin",
+ "target": [
+ { "stderr": "v4.stderr" }
+ ],
+ "error": "expected"
+ }
+]
diff --git a/travis/test/v4.stderr b/travis/test/v4.stderr
new file mode 100644
index 00000000..ea92399d
--- /dev/null
+++ b/travis/test/v4.stderr
@@ -0,0 +1,3 @@
+./travis/test/v4.asm:13: error: register set not valid for operand
+./travis/test/v4.asm:14: error: invalid register set size
+./travis/test/v4.asm:15: error: invalid register set size \ No newline at end of file
diff --git a/travis/test/vaesenc.asm b/travis/test/vaesenc.asm
new file mode 100644
index 00000000..38e19364
--- /dev/null
+++ b/travis/test/vaesenc.asm
@@ -0,0 +1,20 @@
+ bits 64
+ aesenc xmm0,xmm4
+ vaesenc zmm0,zmm0,zmm4
+ vpclmullqlqdq zmm1,zmm1,zmm5
+ vpclmulqdq zmm0, zmm1, zmm2, 0
+ vaesenclast zmm0, zmm1, zmm2
+
+ bits 32
+ aesenc xmm0,xmm4
+ vaesenc zmm0,zmm0,zmm4
+ vpclmullqlqdq zmm1,zmm1,zmm5
+ vpclmulqdq zmm0, zmm1, zmm2, 0
+ vaesenclast zmm0, zmm1, zmm2
+
+ bits 16
+ aesenc xmm0,xmm4
+ vaesenc zmm0,zmm0,zmm4
+ vpclmullqlqdq zmm1,zmm1,zmm5
+ vpclmulqdq zmm0, zmm1, zmm2, 0
+ vaesenclast zmm0, zmm1, zmm2
diff --git a/travis/test/vaesenc.bin.t b/travis/test/vaesenc.bin.t
new file mode 100644
index 00000000..b312920d
--- /dev/null
+++ b/travis/test/vaesenc.bin.t
Binary files differ
diff --git a/travis/test/vaesenc.json b/travis/test/vaesenc.json
new file mode 100644
index 00000000..479c73b3
--- /dev/null
+++ b/travis/test/vaesenc.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Test AES inctructions (BR 3392454, 3392460)",
+ "id": "vaesenc",
+ "format": "bin",
+ "source": "vaesenc.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "vaesenc.bin" }
+ ]
+ }
+]
diff --git a/travis/test/vex.asm b/travis/test/vex.asm
new file mode 100644
index 00000000..6772c7ce
--- /dev/null
+++ b/travis/test/vex.asm
@@ -0,0 +1,9 @@
+ bits 64
+ vcomisd xmm0,xmm31
+ vcomisd xmm0,xmm1
+ {vex2} vcomisd xmm0,xmm1
+ {vex3} vcomisd xmm0,xmm1
+ {evex} vcomisd xmm0,xmm1
+%ifdef ERROR
+ {vex3} add eax,edx
+%endif
diff --git a/travis/test/vex.bin.t b/travis/test/vex.bin.t
new file mode 100644
index 00000000..2145d4cf
--- /dev/null
+++ b/travis/test/vex.bin.t
@@ -0,0 +1 @@
+b///y/b/ \ No newline at end of file
diff --git a/travis/test/vex.json b/travis/test/vex.json
new file mode 100644
index 00000000..e1db1923
--- /dev/null
+++ b/travis/test/vex.json
@@ -0,0 +1,21 @@
+[
+ {
+ "description": "Test VEX2/VEX3/EVEX prefix",
+ "id": "vex",
+ "format": "bin",
+ "source": "vex.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "vex.bin" }
+ ]
+ },
+ {
+ "description": "Test VEX3 prefix error",
+ "ref": "vex",
+ "option": "-Ox -DERROR -o vex.bin.err",
+ "target": [
+ { "stderr": "vex.stderr" }
+ ],
+ "error": "expected"
+ }
+]
diff --git a/travis/test/vex.stderr b/travis/test/vex.stderr
new file mode 100644
index 00000000..2d8858bc
--- /dev/null
+++ b/travis/test/vex.stderr
@@ -0,0 +1 @@
+./travis/test/vex.asm:8: error: specific encoding scheme not available \ No newline at end of file
diff --git a/travis/test/vgather.asm b/travis/test/vgather.asm
new file mode 100644
index 00000000..4012bf28
--- /dev/null
+++ b/travis/test/vgather.asm
@@ -0,0 +1,76 @@
+ bits 64
+
+ vgatherdpd xmm0,[rcx+xmm2],xmm3
+ vgatherqpd xmm0,[rcx+xmm2],xmm3
+ vgatherdpd ymm0,[rcx+xmm2],ymm3
+ vgatherqpd ymm0,[rcx+ymm2],ymm3
+
+ vgatherdpd xmm0,[rcx+xmm2*1],xmm3
+ vgatherqpd xmm0,[rcx+xmm2*1],xmm3
+ vgatherdpd ymm0,[rcx+xmm2*1],ymm3
+ vgatherqpd ymm0,[rcx+ymm2*1],ymm3
+
+ vgatherdpd xmm0,[rcx+xmm2*2],xmm3
+ vgatherqpd xmm0,[rcx+xmm2*2],xmm3
+ vgatherdpd ymm0,[rcx+xmm2*2],ymm3
+ vgatherqpd ymm0,[rcx+ymm2*2],ymm3
+
+ vgatherdpd xmm0,[rcx+xmm2*4],xmm3
+ vgatherqpd xmm0,[rcx+xmm2*4],xmm3
+ vgatherdpd ymm0,[rcx+xmm2*4],ymm3
+ vgatherqpd ymm0,[rcx+ymm2*4],ymm3
+
+ vgatherdpd xmm0,[rcx+xmm2*8],xmm3
+ vgatherqpd xmm0,[rcx+xmm2*8],xmm3
+ vgatherdpd ymm0,[rcx+xmm2*8],ymm3
+ vgatherqpd ymm0,[rcx+ymm2*8],ymm3
+
+ vgatherdpd xmm0,[xmm2],xmm3
+ vgatherqpd xmm0,[xmm2],xmm3
+ vgatherdpd ymm0,[xmm2],ymm3
+ vgatherqpd ymm0,[ymm2],ymm3
+
+ vgatherdpd xmm0,[xmm2*1],xmm3
+ vgatherqpd xmm0,[xmm2*1],xmm3
+ vgatherdpd ymm0,[xmm2*1],ymm3
+ vgatherqpd ymm0,[ymm2*1],ymm3
+
+ vgatherdpd xmm0,[xmm2*2],xmm3
+ vgatherqpd xmm0,[xmm2*2],xmm3
+ vgatherdpd ymm0,[xmm2*2],ymm3
+ vgatherqpd ymm0,[ymm2*2],ymm3
+
+ vgatherdpd xmm0,[xmm2*4],xmm3
+ vgatherqpd xmm0,[xmm2*4],xmm3
+ vgatherdpd ymm0,[xmm2*4],ymm3
+ vgatherqpd ymm0,[ymm2*4],ymm3
+
+ vgatherdpd xmm0,[xmm2*8],xmm3
+ vgatherqpd xmm0,[xmm2*8],xmm3
+ vgatherdpd ymm0,[xmm2*8],ymm3
+ vgatherqpd ymm0,[ymm2*8],ymm3
+
+ vgatherdpd xmm0,[xmm2+rcx],xmm3
+ vgatherqpd xmm0,[xmm2+rcx],xmm3
+ vgatherdpd ymm0,[xmm2+rcx],ymm3
+ vgatherqpd ymm0,[ymm2+rcx],ymm3
+
+ vgatherdpd xmm0,[xmm2*1+rcx],xmm3
+ vgatherqpd xmm0,[xmm2*1+rcx],xmm3
+ vgatherdpd ymm0,[xmm2*1+rcx],ymm3
+ vgatherqpd ymm0,[ymm2*1+rcx],ymm3
+
+ vgatherdpd xmm0,[xmm2*2+rcx],xmm3
+ vgatherqpd xmm0,[xmm2*2+rcx],xmm3
+ vgatherdpd ymm0,[xmm2*2+rcx],ymm3
+ vgatherqpd ymm0,[ymm2*2+rcx],ymm3
+
+ vgatherdpd xmm0,[xmm2*4+rcx],xmm3
+ vgatherqpd xmm0,[xmm2*4+rcx],xmm3
+ vgatherdpd ymm0,[xmm2*4+rcx],ymm3
+ vgatherqpd ymm0,[ymm2*4+rcx],ymm3
+
+ vgatherdpd xmm0,[xmm2*8+rcx],xmm3
+ vgatherqpd xmm0,[xmm2*8+rcx],xmm3
+ vgatherdpd ymm0,[xmm2*8+rcx],ymm3
+ vgatherqpd ymm0,[ymm2*8+rcx],ymm3
diff --git a/travis/test/vgather.bin.t b/travis/test/vgather.bin.t
new file mode 100644
index 00000000..4fd450d1
--- /dev/null
+++ b/travis/test/vgather.bin.t
Binary files differ
diff --git a/travis/test/vgather.json b/travis/test/vgather.json
new file mode 100644
index 00000000..838537b8
--- /dev/null
+++ b/travis/test/vgather.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Test vgather instruction",
+ "id": "vgather",
+ "format": "bin",
+ "source": "vgather.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "vgather.bin" }
+ ]
+ }
+]
diff --git a/travis/test/vpcmp.asm b/travis/test/vpcmp.asm
new file mode 100644
index 00000000..acc8ef37
--- /dev/null
+++ b/travis/test/vpcmp.asm
@@ -0,0 +1,28 @@
+ bits 64
+
+ vpcmpeqb k2{k2},zmm0,zmm1
+ vpcmpgtb k2{k2},zmm0,zmm1
+ vpcmpeqw k2{k2},zmm0,zmm1
+ vpcmpgtw k2{k2},zmm0,zmm1
+ vpcmpeqd k2{k2},zmm0,zmm1
+ vpcmpgtd k2{k2},zmm0,zmm1
+ vpcmpeqq k2{k2},zmm0,zmm1
+ vpcmpgtq k2{k2},zmm0,zmm1
+
+ vpcmpb k2{k2},zmm0,zmm1,0
+ vpcmpb k2{k2},zmm0,zmm1,6
+ vpcmpw k2{k2},zmm0,zmm1,0
+ vpcmpw k2{k2},zmm0,zmm1,6
+ vpcmpd k2{k2},zmm0,zmm1,0
+ vpcmpd k2{k2},zmm0,zmm1,6
+ vpcmpq k2{k2},zmm0,zmm1,0
+ vpcmpq k2{k2},zmm0,zmm1,6
+
+ vpcmpneqb k2{k2},zmm0,zmm1
+ vpcmpleb k2{k2},zmm0,zmm1
+ vpcmpneqw k2{k2},zmm0,zmm1
+ vpcmplew k2{k2},zmm0,zmm1
+ vpcmpneqd k2{k2},zmm0,zmm1
+ vpcmpled k2{k2},zmm0,zmm1
+ vpcmpneqq k2{k2},zmm0,zmm1
+ vpcmpleq k2{k2},zmm0,zmm1
diff --git a/travis/test/vpcmp.bin.t b/travis/test/vpcmp.bin.t
new file mode 100644
index 00000000..0ac4dfe0
--- /dev/null
+++ b/travis/test/vpcmp.bin.t
Binary files differ
diff --git a/travis/test/vpcmp.json b/travis/test/vpcmp.json
new file mode 100644
index 00000000..c98da198
--- /dev/null
+++ b/travis/test/vpcmp.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Test vpcmp instruction",
+ "id": "vpcmp",
+ "format": "bin",
+ "source": "vpcmp.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "vpcmp.bin" }
+ ]
+ }
+]
diff --git a/travis/test/warnstack.asm b/travis/test/warnstack.asm
new file mode 100644
index 00000000..6e762904
--- /dev/null
+++ b/travis/test/warnstack.asm
@@ -0,0 +1,10 @@
+%warning "Good warning"
+ [warning push]
+ [warning -user]
+%warning "Bad warning"
+ [warning pop]
+%warning "Good warning"
+ [warning -user]
+%warning "Bad warning"
+ [warning pop] ; should warn but reset all
+%warning "Good warning"
diff --git a/travis/test/warnstack.bin.t b/travis/test/warnstack.bin.t
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/travis/test/warnstack.bin.t
diff --git a/travis/test/warnstack.json b/travis/test/warnstack.json
new file mode 100644
index 00000000..c462b75b
--- /dev/null
+++ b/travis/test/warnstack.json
@@ -0,0 +1,13 @@
+[
+ {
+ "description": "Test warning stack",
+ "id": "warnstack",
+ "format": "bin",
+ "source": "warnstack.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "warnstack.bin" },
+ { "stderr": "warnstack.stderr" }
+ ]
+ }
+]
diff --git a/travis/test/warnstack.stderr b/travis/test/warnstack.stderr
new file mode 100644
index 00000000..76f81a8f
--- /dev/null
+++ b/travis/test/warnstack.stderr
@@ -0,0 +1,4 @@
+./travis/test/warnstack.asm:1: warning: Good warning [-w+user]
+./travis/test/warnstack.asm:6: warning: Good warning [-w+user]
+./travis/test/warnstack.asm:9: warning: warning stack empty [-w+warn-stack-empty]
+./travis/test/warnstack.asm:10: warning: Good warning [-w+user]
diff --git a/travis/test/winalign.asm b/travis/test/winalign.asm
new file mode 100644
index 00000000..cad0a376
--- /dev/null
+++ b/travis/test/winalign.asm
@@ -0,0 +1,45 @@
+ section .pdata rdata align=2
+ dd 1
+ dd 2
+ dd 3
+
+ section .rdata align=16
+ dd 4
+ dd 5
+ dd 6
+
+ section ultra
+ dd 10
+ dd 11
+ dd 12
+
+ section infra rdata
+ dd 20
+ dd 21
+ dd 22
+
+ section omega rdata align=1
+ dd 90
+ dd 91
+ dd 92
+
+ section .xdata
+ dd 7
+ dd 8
+ dd 9
+
+ section ultra align=8
+ dd 13
+ dd 14
+ dd 15
+
+ section infra rdata align=1
+ dd 23
+ dd 24
+ dd 25
+
+ section omega rdata
+ sectalign 2
+ dd 93
+ dd 94
+ dd 95
diff --git a/travis/test/winalign.json b/travis/test/winalign.json
new file mode 100644
index 00000000..6ada1c89
--- /dev/null
+++ b/travis/test/winalign.json
@@ -0,0 +1,13 @@
+[
+ {
+ "description": "COFF alignment based on BR3392692",
+ "id": "winalign",
+ "format": "win64",
+ "source": "winalign.asm",
+ "error": "over",
+ "option": "-Ox",
+ "target": [
+ { "output": "winalign.obj" }
+ ]
+ }
+]
diff --git a/travis/test/winalign.obj.t b/travis/test/winalign.obj.t
new file mode 100644
index 00000000..f32ec00a
--- /dev/null
+++ b/travis/test/winalign.obj.t
Binary files differ
diff --git a/travis/test/xdefine.asm b/travis/test/xdefine.asm
new file mode 100644
index 00000000..5c510cd6
--- /dev/null
+++ b/travis/test/xdefine.asm
@@ -0,0 +1,15 @@
+%idefine d dword
+%define _1digits_nocheck(d) (((d)% 10)+'0')
+%xdefine _1digits(d) (!!(d/10)*(1<<32)+ _1digits_nocheck(d))
+
+ db _1digits(8) ; Should be 0x38
+
+%define n 0x21
+%xdefine ctr n
+%define n 0x22
+
+ db ctr, n ; Should be 0x21, 0x22
+
+%define MNSUFFIX
+%define MNCURRENT TEST%[MNSUFFIX]
+%xdefine var MNCURRENT
diff --git a/travis/test/xdefine.bin.t b/travis/test/xdefine.bin.t
new file mode 100644
index 00000000..6ad8beef
--- /dev/null
+++ b/travis/test/xdefine.bin.t
@@ -0,0 +1 @@
+8!" \ No newline at end of file
diff --git a/travis/test/xdefine.json b/travis/test/xdefine.json
new file mode 100644
index 00000000..39479ec0
--- /dev/null
+++ b/travis/test/xdefine.json
@@ -0,0 +1,12 @@
+[
+ {
+ "description": "Test weird defines",
+ "id": "xdefine",
+ "format": "bin",
+ "source": "xdefine.asm",
+ "option": "-Ox",
+ "target": [
+ { "output": "xdefine.bin" }
+ ]
+ }
+]
diff --git a/travis/test/xpaste.asm b/travis/test/xpaste.asm
new file mode 100644
index 00000000..cb994588
--- /dev/null
+++ b/travis/test/xpaste.asm
@@ -0,0 +1,6 @@
+%iassign OWORD_size 16 ; octo-word
+%idefine sizeof(_x_) _x_%+_size
+
+%define ptr eax+sizeof(oword)
+
+movdqa [ptr], xmm1
diff --git a/travis/test/xpaste.bin.t b/travis/test/xpaste.bin.t
new file mode 100644
index 00000000..59bb2f04
--- /dev/null
+++ b/travis/test/xpaste.bin.t
@@ -0,0 +1 @@
+gfH \ No newline at end of file
diff --git a/travis/test/xpaste.json b/travis/test/xpaste.json
new file mode 100644
index 00000000..31721c15
--- /dev/null
+++ b/travis/test/xpaste.json
@@ -0,0 +1,11 @@
+[
+ {
+ "description": "Test preproc xdefine",
+ "id": "xpaste",
+ "source": "xpaste.asm",
+ "option": "-f bin -Ox",
+ "target": [
+ { "output": "xpaste.bin" }
+ ]
+ }
+]