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path: root/drivers/net/cxgb3/ael1002.c
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* cxgb3: fix linkup issueHiroshi Shimamoto2010-04-211-1/+1
| | | | | | | | | | | | I encountered an issue that not to link up on cxgb3 fabric. I bisected and found that this regression was introduced by 0f07c4ee8c800923ae7918c231532a9256233eed. Correct to pass phy_addr to cphy_init() at t3_xaui_direct_phy_prep(). Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Acked-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: use request_firmware() for the EDC registers setupDivy Le Ray2009-07-081-1050/+31
| | | | | | | use request_firmware() to load the phy's EDC programmation Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: AEL2020 phy support updateDivy Le Ray2009-07-081-27/+75
| | | | | | | | | | We don't always see the link status update interrupt when we come out of reset and the peer is up. Check and report the link status right before enabling interrupts. Also fix LED settings, to get a consistent link status. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: fix phy power downDivy Le Ray2009-07-081-8/+2
| | | | | | | | | 2 phys are were not getting the Global Tx disable bit set when powered down, leading to an inconsistent link state on peer. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: Add Aeluros 2020 phy supportDivy Le Ray2009-05-291-65/+758
| | | | | | | | Add support for the AEL2020 phy. Add PCI IDs of the boards using this phy. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: Use generic XENPAK LASI register definitionsBen Hutchings2009-05-201-1/+2
| | | | | | Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Acked-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: Use generic MDIO definitions and mdio_mii_ioctl()Ben Hutchings2009-04-291-70/+76
| | | | | | | Compile-tested only. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* drivers/net/cxgb3: fix sparse warnings: fix signednessHannes Eder2009-02-171-1/+2
| | | | | | | | | Fix this sparse warning: drivers/net/cxgb3/ael1002.c:1010:60: warning: incorrect type in argument 4 (different signedness) Signed-off-by: Hannes Eder <hannes@hanneseder.net> Acked-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: extend copyrights to 2008Divy Le Ray2008-10-131-1/+1
| | | | | | | Update copyright banner to 2008. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: Support for Aeluros 2005 PHYDivy Le Ray2008-10-081-16/+994
| | | | | | | | Add support for SR PHY. Auto-detect phy module type, and report type changes. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: commnonize LASI phy codeDivy Le Ray2008-10-081-38/+8
| | | | | | | | | | | Add generic code to manage interrupt driven PHYs. Do not reset the phy after link parameters update, the new values might get lost. Return early from link change notification when the link parameters remain unchanged. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: simplify port type struct and usageDivy Le Ray2008-10-081-4/+12
| | | | | | | | | | Second step in overall phy layer reorganization. Clean up the port_type_info structure. Support coextistence of clause 22 and clause 45 MDIO devices. Select the type of MDIO transaction on a per transaction basis. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3: allow for PHY reset statusDivy Le Ray2008-10-081-8/+12
| | | | | | | | First step towards overall PHY layering re-organization. Allow a status return when a PHY is reset. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* cxgb3 - Fix direct XAUI supportDivy Le Ray2007-06-201-2/+8
| | | | | | | | Check all lanes for link status on direct XAUI cards. Don't assume that direct XAUI always uses XGMAC 1. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
* cxgb3 - Add dual licensingDivy Le Ray2007-02-051-7/+27
| | | | | | | Dual licensing, needed for OFED 1.2 Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
* Add support for the latest 1G/10G Chelsio adapter, T3.Divy Le Ray2007-02-051-0/+231
This driver is required by the Chelsio T3 RDMA driver posted by Steve Wise. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>