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* s0i3: allow break events, but do not STI the processorH. Peter Anvin2010-12-141-3/+18
| | | | | | We want interrupts to be break events, but we do not want them to wake us up just yet; remove sti/cli but enable them to be interrupt break events via ECX=1.
* s0i3: do a cli before looping the second threadH. Peter Anvin2010-12-141-0/+2
| | | | | | No need for interrupts on an offlined processor... Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* s0i3: remove simulation codeH. Peter Anvin2010-12-141-25/+0
| | | | | | We got entry working properly, no need to simulate further. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* s0i3: add support for putting the secondary thread back into C6H. Peter Anvin2010-12-141-0/+29
| | | | | | | | | | We need to SIPI the secondary thread just in order to put it back into C6, in order for S0i3 to be possible again. Sigh. Note: this really should be done on top of the unified trampoline patchset; that will cut the number of lines roughly in half. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* s0i3: delay the PM_CMD write until immediately before MWAITH. Peter Anvin2010-12-141-2/+5
| | | | PM_CMD has a timeout, make sure it doesn't get triggered by WBINVD.
* s0i3: don't simulate by defaultH. Peter Anvin2010-12-141-1/+1
| | | | Stub out the simulated return hack.
* s0i3: Make assembly code save and restore actually matchH. Peter Anvin2010-12-141-26/+71
| | | | | | | | Make sure we save and restore the same things ;) and that we actually restore what we thing we should be restoring. Remove the stack image definition in a header file; C code doesn't need to know about this stuff.
* Initial S0i3 code testH. Peter Anvin2010-12-141-0/+162