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* ARM: S5PV310: Fix on Secondary CPU startupChanghwan Youn2010-08-274-2/+10
| | | | | | | | | | | | | | | Following occurs on boot message without this patch. CPU1: processor failed to boot Brought up 1 CPUs SMP: Total of 1 processors activated... This patch adds SYSRAM mapping for fixing Secondary CPU startup. CPU1: Booted secondary processor Brought up 2 CPUs SMP: Total of 2 processors activated... Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S5PV310: Bug fix on uclk1 and sclk_pwmJongpill Lee2010-08-272-8/+15
| | | | | | | This patch fixes on enable and ctrlbit of uclk1 and sclk_pwm. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S5PV310: Fix missed uart clocksJongpill Lee2010-08-271-7/+37
| | | | | | | This patch adds missed uart clocks for S5PV310/S5PC210. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S5PV310: Should be clk_sclk_apll not clk_mout_apllJongpill Lee2010-08-271-3/+12
| | | | | | | This patch adds clk_sclk_apll so that fixes on clk_mout_apll. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S5PV310: Fix on PLL setting for S5PV310Jongpill Lee2010-08-271-2/+2
| | | | | | | This patch fixes on PLL setting for S5PV310/S5PC210. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S5PV310: Add CMU block for S5PV310 ClockKukjin Kim2010-08-274-31/+38
| | | | | | | | This patch adds CMU block for S5PV310/S5PC210 clock. (CMU: Clock Management Unit) Of course, changed current clock addresses for it together. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S5PV310: Fix on typo irqs.h of S5PV310Kukjin Kim2010-08-271-4/+7
| | | | | | | This patch fixes typo 'IRQ_WTD' in the irqs.h of S5PV310. And minor update comments. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S5PV310: Fix on default ZRELADDR of ARCH_S5PV310Kukjin Kim2010-08-271-1/+2
| | | | | | This patch adds default zreladdr of ARCH_S5PV310. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S5PV310: Fix on GPIO base addressesKyungmin Park2010-08-271-2/+10
| | | | | | | | | | | | The S5PV310/S5PC210 has following three GPIO base addresses. Part1 Base Address=0x11400000 Part2 Base Address=0x11000000 Part3 Base Address=0x03860000 Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor edit of title] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: SAMSUNG: Fix on build warning regarding VMALLOC_END typeKukjin Kim2010-08-274-4/+4
| | | | | | | | | | | | | | Fix this warning: arch/arm/mm/init.c: In function 'mem_init': arch/arm/mm/init.c:644: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int' And removes the useless parens and white space. Reported-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Cc: Ben Dooks <ben-linux@fluff.org>
* ARM: S5P: VMALLOC_END should be unsigned longKyungmin Park2010-08-232-2/+2
| | | | | | | | | | | Silences following build warning: arch/arm/mm/init.c: In function 'mem_init': arch/arm/mm/init.c:644: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int' Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* Linux 2.6.36-rc2v2.6.36-rc2Linus Torvalds2010-08-221-1/+1
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* Merge branch 'kvm-updates/2.6.36' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2010-08-223-3/+5
|\ | | | | | | | | | | | | * 'kvm-updates/2.6.36' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: PIT: free irq source id in handling error path KVM: destroy workqueue on kvm_create_pit() failures KVM: fix poison overwritten caused by using wrong xstate size
| * KVM: PIT: free irq source id in handling error pathXiao Guangrong2010-08-171-0/+1
| | | | | | | | | | | | | | Free irq source id if create pit workqueue fail Signed-off-by: Xiao Guangrong <xiaoguangrong@cn.fujitsu.com> Signed-off-by: Avi Kivity <avi@redhat.com>
| * KVM: destroy workqueue on kvm_create_pit() failuresXiaotian Feng2010-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kernel needs to destroy workqueue if kvm_create_pit() fails, otherwise after pit is freed, the workqueue is leaked. Signed-off-by: Xiaotian Feng <dfeng@redhat.com> Cc: Avi Kivity <avi@redhat.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Gleb Natapov <gleb@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Gregory Haskins <ghaskins@novell.com> Signed-off-by: Avi Kivity <avi@redhat.com>
| * KVM: fix poison overwritten caused by using wrong xstate sizeXiaotian Feng2010-08-152-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fpu.state is allocated from task_xstate_cachep, the size of task_xstate_cachep is xstate_size. xstate_size is set from cpuid instruction, which is often smaller than sizeof(struct xsave_struct). kvm is using sizeof(struct xsave_struct) to fill in/out fpu.state.xsave, as what we allocated for fpu.state is xstate_size, kernel will write out of memory and caused poison/redzone/padding overwritten warnings. Signed-off-by: Xiaotian Feng <dfeng@redhat.com> Reviewed-by: Sheng Yang <sheng@linux.intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Brian Gerst <brgerst@gmail.com> Cc: Avi Kivity <avi@redhat.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Sheng Yang <sheng@linux.intel.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Cc: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* | Merge branch 'for-linus' of ↵Linus Torvalds2010-08-2228-2417/+2663
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (58 commits) drm/i915,intel_agp: Add support for Sandybridge D0 drm/i915: fix render pipe control notify on sandybridge agp/intel: set 40-bit dma mask on Sandybridge drm/i915: Remove the conflicting BUG_ON() drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/ drm/i915/suspend: Flush register writes before busy-waiting. i915: disable DAC on Ironlake also when doing CRT load detection. drm/i915: wait for actual vblank, not just 20ms drm/i915: make sure eDP PLL is enabled at the right time drm/i915: fix VGA plane disable for Ironlake+ drm/i915: eDP mode set sequence corrections drm/i915: add panel reset workaround drm/i915: Enable RC6 on Ironlake. drm/i915/sdvo: Only set is_lvds if we have a valid fixed mode. drm/i915: Set up a render context on Ironlake drm/i915 invalidate indirect state pointers at end of ring exec drm/i915: Wake-up wait_request() from elapsed hang-check (v2) drm/i915: Apply i830 errata for cursor alignment drm/i915: Only update i845/i865 CURBASE when disabled (v2) drm/i915: FBC is updated within set_base() so remove second call in mode_set() ...
| * | drm/i915,intel_agp: Add support for Sandybridge D0Zhenyu Wang2010-08-213-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: fix render pipe control notify on sandybridgeZhenyu Wang2010-08-211-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | This one is missed in last pipe control fix for sandybridge, that really unmask interrupt bit for notify in render engine IMR. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | agp/intel: set 40-bit dma mask on SandybridgeZhenyu Wang2010-08-211-9/+15
| | | | | | | | | | | | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Remove the conflicting BUG_ON()Chris Wilson2010-08-211-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now attempt to free "active" objects following a GPU hang as either the GPU will be reset or the hang is permenant. In either case, the GPU writes will not be flushed to main memory and it should be safe to return that memory back to the system. The BUG_ON(active) is thus overkill and can erroneously fire after a EIO. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/Chris Wilson2010-08-211-37/+37
| | | | | | | | | | | | | | | | | | | | | For the shared paths on the next generation chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915/suspend: Flush register writes before busy-waiting.Chris Wilson2010-08-211-9/+18
| | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | i915: disable DAC on Ironlake also when doing CRT load detection.Dave Airlie2010-08-211-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like on Sandybridge, disabling the DAC here when doing CRT load detect avoids forever hangs waiting on the hardware. test procedure on HP 2740p: boot with no VGA plugged in, start X, plug in VGA monitor (1280x1024) chvt 3 machine hangs waiting forever. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: wait for actual vblank, not just 20msJesse Barnes2010-08-217-30/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Waiting for a hard coded 20ms isn't always enough to make sure a vblank period has actually occurred, so add code to make sure we really have passed through a vblank period (or that the pipe is off when disabling). This prevents problems with mode setting and link training, and seems to fix a bug like https://bugs.freedesktop.org/show_bug.cgi?id=29278, but on an HP 8440p instead. Hopefully also fixes https://bugs.freedesktop.org/show_bug.cgi?id=29141. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: make sure eDP PLL is enabled at the right timeJesse Barnes2010-08-182-39/+60
| | | | | | | | | | | | | | | | | | | | | We need to make sure the eDP PLL is enabled before the pipes or planes, so do it as part of the DP prepare mode set function. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: fix VGA plane disable for Ironlake+Jesse Barnes2010-08-181-28/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to use I/O port instructions to access VGA registers on Ironlake+, and it doesn't hurt on other platforms, so switch the VGA plane disable function over to using them. Move it to init time as well while we're at it, no need to repeatedly disable the VGA plane with every mode set and DPMS event. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: eDP mode set sequence correctionsJesse Barnes2010-08-181-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | We should disable the panel first when shutting down an eDP link. And when turning one on, the panel needs to be enabled before link training or eDP I/O won't be enabled. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: add panel reset workaroundJesse Barnes2010-08-181-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | Ironlake requires that we clear the reset panel bit during power sequences and restore it afterwards. Uncondtionally add code to do that since it should be harmless on SNB+. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: Enable RC6 on Ironlake.Zou Nan hai2010-08-091-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | RC6 allows the GPU to enter a lower power state when the GPU is idle. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [anholt: Fixed the !renderctx error path to actually not enable RC6.] Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915/sdvo: Only set is_lvds if we have a valid fixed mode.Chris Wilson2010-08-091-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we have failed to ascertain the fixed mode for the LVDS panel, then trust the pixel clock ranges reported for the connection when determing valid modes. This makes intel_sdvo_mode_valid() consistent with intel_lvds_mode_valid() which is also a no-op is there is no fixed mode defined. (Since the mode is both validated by SDVO and LVDS, why are checking against an LVDS fixed mode in SDVO...) By only defining is_lvds to be true when we actually have an LVDS output with a fixed mode, we avoid various potential NULL deferences where the assumption is made that all LVDS outputs have a fixed mode. References: Bug 29449 - [Q35] failure to read EDID/vbios for LVDS, no mode => no output https://bugs.freedesktop.org/show_bug.cgi?id=29449 The primary failure in this bug is not finding the EDID and determining the correct fixed panel mode. However, this patch should fix the secondary issue of not enabling any of the standard modes for the panel either. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Set up a render context on IronlakeZou Nan hai2010-08-093-10/+55
| | | | | | | | | | | | | | | | | | | | | | | | RC6 power state requires a logical render context in place for saving render context. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915 invalidate indirect state pointers at end of ring execZou Nan hai2010-08-093-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | This is required by the spec, and without this some 3D programs will hang after resume from RC6 we enable that. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Wake-up wait_request() from elapsed hang-check (v2)Chris Wilson2010-08-091-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If our watchdog fires and we see that the GPU is idle, but that we are still waiting on an interrupt, forcibly wake-up the waiter. i915_do_wait_request() should not be racy, yet there are persistent reports that 945GM hangs whilst the GPU is idle. This implies that the hardware is not quite as coherent as the documentation claims - a write followed by a flush is supposed to be coherent in main memory before the flush is retired and the irq is emitted. This seems to be a sensible and elegant guard to force the wait to timeout. v2: Daniel Vetter pointed out that a warning would be useful to explain why the machine appeared to stall. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Apply i830 errata for cursor alignmentChris Wilson2010-08-094-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | i830 requires 32bpp cursors to be aligned to 16KB, so we have to expose the alignment parameter to i915_gem_attach_phys_object(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Only update i845/i865 CURBASE when disabled (v2)Chris Wilson2010-08-092-30/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i845 and i865 have a peculiarlity in that CURBASE is not the trigger for the vsync update of the cursor registers but instead the modification of that register is prohibited whilst the cursor is enabled. Reorder the write sequence for CURPOS, CURCNTR and CURBASE on i845 to i865 to match. v2: Remove the checks for i845/i865 from within i9xx_cursor_update() Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: FBC is updated within set_base() so remove second call in mode_set()Chris Wilson2010-08-091-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The FBC is dependent upon a few details of the framebuffer so it is required to be updated within set_base(), so remove the redundant call from mode_set(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915/edp: Flush the write before waiting for PLLsChris Wilson2010-08-091-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Ensure that while(INREG()) are bounded (v2)Chris Wilson2010-08-095-78/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new macro, wait_for, to simplify the act of waiting on a register to change state. wait_for() takes three arguments, the condition to inspect on every loop, the maximum amount of time to wait and whether to yield the cpu for a length of time after each check. v2: Upgrade failure messages to DRM_ERROR on the suggestion of Eric Anholt. We do not expect to hit these conditions as they reflect programming errors, so if we do we want to be notified. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915/ringbuffer: Set ring->gem_buffer = NULL on init unwindChris Wilson2010-08-091-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | The cleanup path for early abort failed to nullify the gem_buffer. The likely consequence of this is zero, since a failure here should mean aborting the module load. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Update watermarks for Ironlake after dpms changesChris Wilson2010-08-091-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we only remembered to update the watermarks for i9xx, and incorrectly assumed that the crtc->enabled flag was valid at that point in the dpms cycle. Note that on my x201s this makes a SR bug on pipe 1 much easier to hit. (Since before this patch when disabling pipe 0, we either didn't update the watermarks at all, or when we did we still thought we had two pipes enabled and so disabled SR.) References: Bug 28969 - [Arrandale] Screen flickers, suspect Self-Refresh https://bugs.freedesktop.org/show_bug.cgi?id=28969 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915/opregion: Use ASLE response codes defined in 0.1Chris Wilson2010-08-091-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Within i915_opregion.c there are two blocks of semantically identical ASLE response codes defined. Only one of those matches the ACPI IGD OpRegion Specification 0.1, use those. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Matthew Garrett <mjg59@srcf.ucam.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915/display: Add pipe/plane information to dpms debuggingChris Wilson2010-08-091-3/+3
| | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Truncate the shmem backing pages on purgeChris Wilson2010-08-091-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | shmfs doesn't actually implement i_ops->truncate() so we were not immedatiately releasing the backing pages when shrinking the gfx cache under OOM. Instead use a combination of truncate_inode_pages() and i_ops->truncate_range() as is used by shmem_delete_inode(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Write to display base last.Chris Wilson2010-08-091-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Writing to the DSPBASE register triggers the double-buffered update to all the control registers, so always write it last in the update sequence. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Enable aspect/centering panel fitting for Ironlake.Chris Wilson2010-08-097-46/+143
| | | | | | | | | | | | | | | | | | | | | | | | v2: Hook in DP paths to keep FULLSCREEN panel fitting on eDP. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915/sdvo: Markup a few constant strings.Chris Wilson2010-08-091-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Record error batch buffers using iomemChris Wilson2010-08-091-7/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Directly read the GTT mapping for the contents of the batch buffers rather than relying on possibly stale CPU caches. Also for completeness scan the flushing/inactive lists for the current buffers - we are collecting error state after all. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Maintain LRU order of inactive objects upon access by CPU (v2)Chris Wilson2010-08-091-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to reduce the penalty of fallbacks under memory pressure and to avoid a potential immediate ping-pong of evicting a mmaped buffer, we move the object to the tail of the inactive list when a page is freshly faulted or the object is moved into the CPU domain. We choose not to protect the CPU objects from casual eviction, preferring to keep the GPU active for as long as possible. v2: Daniel Vetter found a bug where I forgot that pinned objects are kept off the inactive list. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: Implement fair lru eviction across both rings. (v2)Chris Wilson2010-08-092-133/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based in a large part upon Daniel Vetter's implementation and adapted for handling multiple rings in a single pass. This should lead to better gtt usage and fixes the page-fault-of-doom triggered. The fairness is provided by scanning through the GTT space amalgamating space in rendering order. As soon as we have a contiguous space in the GTT large enough for the new object (and its alignment), evict any object which lies within that space. This should keep more objects resident in the GTT. Doing throughput testing on a PineView machine with cairo-perf-trace indicates that there is very little difference with the new LRU scan, perhaps a small improvement... Except oddly for the poppler trace. Reference: Bug 15911 - Intermittent X crash (freeze) https://bugzilla.kernel.org/show_bug.cgi?id=15911 Bug 20152 - cannot view JPG in firefox when running UXA https://bugs.freedesktop.org/show_bug.cgi?id=20152 Bug 24369 - Hang when scrolling firefox page with window in front https://bugs.freedesktop.org/show_bug.cgi?id=24369 Bug 28478 - Intermittent graphics lockups due to overflow/loop https://bugs.freedesktop.org/show_bug.cgi?id=28478 v2: Attempt to clarify the logic and order of eviction through the use of comments and macros. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>