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authorStefan Richter <stefanr@s5r6.in-berlin.de>2010-07-22 11:56:38 +0200
committerStefan Richter <stefanr@s5r6.in-berlin.de>2010-07-27 11:04:11 +0200
commitfd8c8d46ca9402c15383d2cf0bc3ee7740de3b62 (patch)
tree66a33db3ea837f2fb6c66e077a9b5fae7009c3ba /tools
parentc89db7b8bc88d8288dcfbe7a885b950d2560d564 (diff)
firewire: nosy: endianess fixes and annotations
1.) The DMA programs (struct pcl) are PCI-endian = little endian data (except for the 3rd quadlet in a PCL which the controller does not touch). Annotate them as such. Fix all accesses of the PCL to work with big endian CPUs also. Not actually tested, I only have a little endian PC to test with. This includes replacement of a bitfield struct pcl_status by open-coded shift and mask operations. 2.) The two __attribute__ ((packed)) at struct pcl are not really required since it consists of u32/__le32 only, i.e. there will be no padding with or without the attribute. 3.) The received IEEE 1394 data are byteswapped by the controller from IEEE 1394 endian = big endian to PCI endian = little endian because the PCL_BIGENDIAN control bit is set. Therefore annotate the DMA buffer as a __le32 array. Fix the one access of the DMA buffer (the check of the transaction code of link packets) to work with big endian CPUs. Also fix the two accesses of the client bounce buffer (the reading of packet length). 4.) Add a comment to the userspace ABI header that all of the data gets out as little endian data, except for the timestamp which is CPU endian. (We could make it little endian too, but why? Vice versa, an ioctl could be added to dump packet data in big endian byte order...) Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Diffstat (limited to 'tools')
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