path: root/kernel/panic.c
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authorTom Lyon <pugs@cisco.com>2010-05-17 08:20:45 +0100
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-05-17 08:34:18 +0100
commita99c47a228c194aa75bffdcb82806c5f33c7c63b (patch)
tree90f8651c7374356bb29811ca6401858fb545610b /kernel/panic.c
parent4f506e07e0a3dff34427cece255a8f390a78d5a0 (diff)
intel-iommu: errors with smaller iommu widths
When using iommu_domain_alloc with the Intel iommu, the domain address width is always initialized to 48 bits (agaw 2). This domain->agaw value is then used by pfn_to_dma_pte to (always) build a 4 level page table. However, not all systems support iommu width of 48 or 4 level page tables. In particular, the Core i5-660 and i5-670 support an address width of 36 bits (not 39!), an agaw of only 1, and only 3 level page tables. This version of the patch simply lops off extra levels of the page tables if the agaw value of the iommu is less than what is currently allocated for the domain (in intel_iommu_attach_device). If there were already allocated addresses above what the new iommu can handle, EFAULT is returned. Signed-off-by: Tom Lyon <pugs@cisco.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'kernel/panic.c')
0 files changed, 0 insertions, 0 deletions