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| author | Jacob Pan <jacob.jun.pan@intel.com> | 2010-12-09 10:37:42 +0000 |
|---|---|---|
| committer | Alan Cox <alan@linux.intel.com> | 2010-12-09 10:37:42 +0000 |
| commit | f26ab70974967a94eaac9390dc65bb5836a98ee6 (patch) | |
| tree | 8d80ad1a6cec03e58c36ee4b1f4709ff7715fe0a /include | |
| parent | 6be72e9b54479e7a2c473bc6cc778319e5f925e3 (diff) | |
| download | mrst-s0i3-test-f26ab70974967a94eaac9390dc65bb5836a98ee6.tar.gz mrst-s0i3-test-f26ab70974967a94eaac9390dc65bb5836a98ee6.tar.xz mrst-s0i3-test-f26ab70974967a94eaac9390dc65bb5836a98ee6.zip | |
ehci: Support Intel Moorestown EHCI controller SRAM QH/QTD/ITD/SITD pool caching
The Intel Moorestown platform has MPH and OTG EHCI controllers that have
internal SRAM that could be used as descriptors DMA pool caching. The SRAM is
exposed via PCI BAR1. The limitation here is the SRAM access should be 32bit
aligned. A separate patch "EHCI: Make ehci_qh structure items all 32bit aligned"
has been submitted to linux-usb mailling list.
Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
Signed-off-by: Alek Du <alek.du@intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/usb/hcd.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h index 57098cd8476..08a8fedfc7e 100644 --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h @@ -119,6 +119,8 @@ struct usb_hcd { unsigned wireless:1; /* Wireless USB HCD */ unsigned authorized_default:1; unsigned has_tt:1; /* Integrated TT in root hub */ + unsigned has_sram:1; /* Local SRAM for caching */ + unsigned sram_no_payload:1; /* sram not for payload */ int irq; /* irq allocated */ void __iomem *regs; /* device memory/io */ |