path: root/include
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authorYu Zhao <yu.zhao@intel.com>2009-04-09 14:57:39 +0800
committerJesse Barnes <jbarnes@virtuousgeek.org>2009-04-22 15:59:41 -0700
commit1b6b8ce2ac372ea1f2065b89228ede105eb68dc5 (patch)
tree12a67c35d30ee626ca46d497c35f3a7d952034c5 /include
parentb10ceb5530df7ee6e81f92910589a34dd3e5690b (diff)
PCI: only save/restore existent registers in the PCIe capability
PCIe 1.1 base neither requires the endpoint to implement the entire PCIe capability structure nor specifies default values of registers that are not implemented by the device. So we only save and restore registers that must be implemented by different device types if the device PCIe capability version is 1. PCIe 1.1 Capability Structure Expansion ECN and PCIe 2.0 requires all registers in the PCIe capability to be either implemented or hardwired to 0. Their PCIe capability version is 2. Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'include')
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index e4d08c1b2e0..616bf8b3c8b 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -376,6 +376,7 @@
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
+#define PCI_EXP_TYPE_RC_EC 0x10 /* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */