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authorLinus Walleij <linus.walleij@stericsson.com>2010-08-21 11:07:36 +0200
committerGrant Likely <grant.likely@secretlab.ca>2010-09-08 12:24:30 -0600
commit545074fb953e1753f6b8409db533ad7998789efb (patch)
treefbe97a2d3cc26c425edbe21e33fc72d03c0e8a33 /include/rdma
parentbe7852a839b6dcd86db1a2d25b9a1a99f38db2db (diff)
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spi/pl022: fix APB pclk power regression on U300
With the introduction of an AMBA PrimeCell per-cell block clock, the pclk was left on after probe() unless explicitly disabled. This clock is wired to the same clock on PL022 causing it to stay always on since. Fix this up properly by clocking the pclk whenever we want to write into any PL022 registers and clocking the external clock whenever we want to transmit messages on the bus. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Tested-by : Kevin Wells <wellsk40@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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