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authorAlex Deucher <alexdeucher@gmail.com>2009-02-24 14:02:13 -0500
committerDave Airlie <airlied@redhat.com>2009-03-13 14:24:10 +1000
commitbefb73c2322923766df7e36b51f407dbdc047eab (patch)
treede14b3d98afba01aab45b4cfa531b14c34905f82 /include/drm/radeon_drm.h
parent995e37cafb90f104395e015a9836cc459df1fc39 (diff)
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drm/radeon: prep for r6xx/r7xx support
- add r6xx/r7xx regs and macros - add r6xx/r7xx chip families - fix register access for regs with offsets >= 0x10000 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'include/drm/radeon_drm.h')
-rw-r--r--include/drm/radeon_drm.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 73ff51f1231..937a275cbb9 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -304,6 +304,8 @@ typedef union {
#define RADEON_SCRATCH_REG_OFFSET 32
+#define R600_SCRATCH_REG_OFFSET 256
+
#define RADEON_NR_SAREA_CLIPRECTS 12
/* There are 2 heaps (local/GART). Each region within a heap is a
@@ -526,7 +528,8 @@ typedef struct drm_radeon_init {
RADEON_INIT_CP = 0x01,
RADEON_CLEANUP_CP = 0x02,
RADEON_INIT_R200_CP = 0x03,
- RADEON_INIT_R300_CP = 0x04
+ RADEON_INIT_R300_CP = 0x04,
+ RADEON_INIT_R600_CP = 0x05
} func;
unsigned long sarea_priv_offset;
int is_pci;