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authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>2008-07-07 21:11:54 +0900
committerPaul Mundt <lethal@linux-sh.org>2008-07-28 18:10:34 +0900
commitcafd63b0076b78bc8f114abbeb724c7e5f5bfe5d (patch)
treee12be13bbac6d45260f9aa0c507a2712ac272c79 /include/asm-sh/se7343.h
parenta4e1d08491b06b17eb77c92caacd40b330ca8146 (diff)
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sh: update Solution Engine 7343
updated the following codes for Solution Endine 7343: - fix compile error in arch/sh/boards/se/7343/irq.c - add nor flash physmaps - update defconfig Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/se7343.h')
-rw-r--r--include/asm-sh/se7343.h97
1 files changed, 84 insertions, 13 deletions
diff --git a/include/asm-sh/se7343.h b/include/asm-sh/se7343.h
index e7914a54aa9..8d2af779fbc 100644
--- a/include/asm-sh/se7343.h
+++ b/include/asm-sh/se7343.h
@@ -59,24 +59,95 @@
#define PA_LCD1 0xb8000000
#define PA_LCD2 0xb8800000
+#define PORT_PACR 0xA4050100
+#define PORT_PBCR 0xA4050102
+#define PORT_PCCR 0xA4050104
+#define PORT_PDCR 0xA4050106
+#define PORT_PECR 0xA4050108
+#define PORT_PFCR 0xA405010A
+#define PORT_PGCR 0xA405010C
+#define PORT_PHCR 0xA405010E
+#define PORT_PJCR 0xA4050110
+#define PORT_PKCR 0xA4050112
+#define PORT_PLCR 0xA4050114
+#define PORT_PMCR 0xA4050116
+#define PORT_PNCR 0xA4050118
+#define PORT_PQCR 0xA405011A
+#define PORT_PRCR 0xA405011C
+#define PORT_PSCR 0xA405011E
+#define PORT_PTCR 0xA4050140
+#define PORT_PUCR 0xA4050142
+#define PORT_PVCR 0xA4050144
+#define PORT_PWCR 0xA4050146
+#define PORT_PYCR 0xA4050148
+#define PORT_PZCR 0xA405014A
+
+#define PORT_PSELA 0xA405014C
+#define PORT_PSELB 0xA405014E
+#define PORT_PSELC 0xA4050150
+#define PORT_PSELD 0xA4050152
+#define PORT_PSELE 0xA4050154
+
+#define PORT_HIZCRA 0xA4050156
+#define PORT_HIZCRB 0xA4050158
+#define PORT_HIZCRC 0xA405015C
+
+#define PORT_DRVCR 0xA4050180
+
+#define PORT_PADR 0xA4050120
+#define PORT_PBDR 0xA4050122
+#define PORT_PCDR 0xA4050124
+#define PORT_PDDR 0xA4050126
+#define PORT_PEDR 0xA4050128
+#define PORT_PFDR 0xA405012A
+#define PORT_PGDR 0xA405012C
+#define PORT_PHDR 0xA405012E
+#define PORT_PJDR 0xA4050130
+#define PORT_PKDR 0xA4050132
+#define PORT_PLDR 0xA4050134
+#define PORT_PMDR 0xA4050136
+#define PORT_PNDR 0xA4050138
+#define PORT_PQDR 0xA405013A
+#define PORT_PRDR 0xA405013C
+#define PORT_PTDR 0xA4050160
+#define PORT_PUDR 0xA4050162
+#define PORT_PVDR 0xA4050164
+#define PORT_PWDR 0xA4050166
+#define PORT_PYDR 0xA4050168
+
+#define MSTPCR0 0xA4150030
+#define MSTPCR1 0xA4150034
+#define MSTPCR2 0xA4150038
+
+#define FPGA_IN 0xb1400000
+#define FPGA_OUT 0xb1400002
+
#define __IO_PREFIX sh7343se
#include <asm/io_generic.h>
-/* External Multiplexed interrupts */
-#define PC_IRQ0 OFFCHIP_IRQ_BASE
-#define PC_IRQ1 (PC_IRQ0 + 1)
-#define PC_IRQ2 (PC_IRQ1 + 1)
-#define PC_IRQ3 (PC_IRQ2 + 1)
+#define IRQ0_IRQ 32
+#define IRQ1_IRQ 33
+#define IRQ4_IRQ 36
+#define IRQ5_IRQ 37
+
+#define SE7343_FPGA_IRQ_MRSHPC0 0
+#define SE7343_FPGA_IRQ_MRSHPC1 1
+#define SE7343_FPGA_IRQ_MRSHPC2 2
+#define SE7343_FPGA_IRQ_MRSHPC3 3
+#define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */
+#define SE7343_FPGA_IRQ_USB 8
-#define EXT_IRQ0 (PC_IRQ3 + 1)
-#define EXT_IRQ1 (EXT_IRQ0 + 1)
-#define EXT_IRQ2 (EXT_IRQ1 + 1)
-#define EXT_IRQ3 (EXT_IRQ2 + 1)
+#define SE7343_FPGA_IRQ_NR 11
+#define SE7343_FPGA_IRQ_BASE 120
-#define USB_IRQ0 (EXT_IRQ3 + 1)
-#define USB_IRQ1 (USB_IRQ0 + 1)
+#define MRSHPC_IRQ3 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3)
+#define MRSHPC_IRQ2 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2)
+#define MRSHPC_IRQ1 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1)
+#define MRSHPC_IRQ0 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0)
+#define SMC_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC)
+#define USB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB)
-#define UART_IRQ0 (USB_IRQ1 + 1)
-#define UART_IRQ1 (UART_IRQ0 + 1)
+/* arch/sh/boards/se/7343/irq.c */
+void init_7343se_IRQ(void);
#endif /* __ASM_SH_HITACHI_SE7343_H */