intel_mid: Medfield battery driver tidy up

- Fix kfifo build problem
- Clean up printing to debug level for the most part
- Remove an impossible NULL check
- Clean up all the ipc writing loops using a single helper

Signed-off-by: Alan Cox <alan@linux.intel.com>

3 files changed, 218 insertions, 258 deletions

diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index b6e41e6cb87..6d90108e12a 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -165,12 +165,19 @@ config BATTERY_JZ4740
 	  This driver can be build as a module. If so, the module will be
 	  called jz4740-battery.
 
-config BATTERY_INTEL_MID
-	tristate "Battery driver for Intel MID platforms"
-	depends on INTEL_SCU_IPC && SPI
+config BATTERY_INTEL_MID_MRST
+	tristate "Battery driver for Intel Moorestown MID platforms"
+	depends on INTEL_SCU_IPC && SPI && USB_GADGET_LANGWELL
 	help
-	  Say Y here to enable the battery driver on Intel MID
-	  platforms.
+	  Say Y here to enable the battery driver on Intel Moorestown
+	  based MID platforms.
+
+config BATTERY_INTEL_MID_MFLD
+	tristate "Battery driver for Intel Medfield MID platforms"
+	depends on INTEL_SCU_IPC && USB_PENWELL_OTG
+	help
+	  Say Y here to enable the battery driver on Intel Medfield
+	  based MID platforms.
 
 config CHARGER_ISP1704
 	tristate "ISP1704 USB Charger Detection"
@@ -185,11 +192,4 @@ config CHARGER_TWL4030
 	help
 	  Say Y here to enable support for TWL4030 Battery Charge Interface.
 
-config BATTERY_INTEL_MDF
-	tristate "Battery driver for Intel MDFLD platforms"
-	depends on INTEL_SCU_IPC && USB_PENWELL_OTG
-	help
-	  Say Y here to enable the battery driver on Intel MFLD
-	  platforms.
-
 endif # POWER_SUPPLY
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index ddeed547e56..41428ec8c10 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -29,7 +29,8 @@ obj-$(CONFIG_BATTERY_Z2)	+= z2_battery.o
 obj-$(CONFIG_BATTERY_S3C_ADC)	+= s3c_adc_battery.o
 obj-$(CONFIG_CHARGER_PCF50633)	+= pcf50633-charger.o
 obj-$(CONFIG_BATTERY_JZ4740)	+= jz4740-battery.o
-obj-$(CONFIG_BATTERY_INTEL_MID)	+= intel_mid_battery.o
+obj-$(CONFIG_BATTERY_INTEL_MID_MRST)	+= intel_mid_battery.o
+obj-$(CONFIG_BATTERY_INTEL_MID_MFLD)	+= intel_mdf_battery.o
 obj-$(CONFIG_CHARGER_ISP1704)	+= isp1704_charger.o
 obj-$(CONFIG_CHARGER_TWL4030)	+= twl4030_charger.o
 obj-$(CONFIG_BATTERY_INTEL_MDF)	+= intel_mdf_battery.o
diff --git a/drivers/power/intel_mdf_battery.c b/drivers/power/intel_mdf_battery.c
index 175a0699e68..f085065b2ae 100644
--- a/drivers/power/intel_mdf_battery.c
+++ b/drivers/power/intel_mdf_battery.c
@@ -1,5 +1,5 @@
 /*
- * msic_battery.c - Intel Medfield MSIC Internal charger and Battery Driver
+ * intel_mdf_battery.c - Intel Medfield MSIC Internal charger and Battery Driver
  *
  * Copyright (C) 2010 Intel Corporation
  *
@@ -43,16 +43,16 @@
 #include <asm/intel_scu_ipc.h>
 #include <linux/usb/penwell_otg.h>
 
-#define DRIVER_NAME "msic_battery"
+#define DRIVER_NAME "intel_mdf_battery"
 
 /*********************************************************************
  *		Generic defines
  *********************************************************************/
 
-#define MSIC_BATT_PRESENT			1
-#define MSIC_BATT_NOT_PRESENT			0
-#define MSIC_USB_CHARGER_PRESENT		MSIC_BATT_PRESENT
-#define MSIC_USB_CHARGER_NOT_PRESENT		MSIC_BATT_NOT_PRESENT
+#define MSIC_BATT_PRESENT		1
+#define MSIC_BATT_NOT_PRESENT		0
+#define MSIC_USB_CHARGER_PRESENT	1
+#define MSIC_USB_CHARGER_NOT_PRESENT	0
 
 /* Interrupt registers*/
 #define MSIC_BATT_CHR_PWRSRCINT_ADDR	0x005
@@ -112,18 +112,18 @@
 #define MSIC_BATT_CHR_EXTCHRDIS_MASK	(1 << 5)
 
 /* Safe limit registers */
-#define MSIC_BATT_CHR_PWRSRCLMT_ADDR	0x18E  /*Temperature limits*/
+#define MSIC_BATT_CHR_PWRSRCLMT_ADDR	0x18E  /* Temperature limits */
 #define CHR_PWRSRCLMT_SET_RANGE		0xC0
 
-#define MSIC_BATT_CHR_CHRSTWDT_ADDR	0x18F  /*Watch dog timer*/
+#define MSIC_BATT_CHR_CHRSTWDT_ADDR	0x18F  /* Watchdog timer */
 #define CHR_WDT_DISABLE			0x0
 #define CHR_WDT_SET_60SEC		0x10
 
 #define MSIC_BATT_CHR_WDTWRITE_ADDR	0x190
 #define WDTWRITE_UNLOCK_VALUE		0x01
 
-#define MSIC_BATT_CHR_CHRSAFELMT_ADDR	0x191  /*Maximum safe charging
-						 voltage and current*/
+#define MSIC_BATT_CHR_CHRSAFELMT_ADDR	0x191  /* Maximum safe charging
+						  voltage and current */
 
 /* Status registers */
 #define MSIC_BATT_CHR_SPWRSRCINT_ADDR	0x192
@@ -146,7 +146,7 @@
 
 #define  MSIC_STOPBIT_MASK	0x10
 #define  MSIC_ADCTHERM_MASK	4
-#define  ADC_CHANLS_MAX		15	/*no of adc channels*/
+#define  ADC_CHANLS_MAX		15	/* num of adc channels */
 #define MSIC_BATT_SENSORS	4	/* 3 for battery pack and one USB */
 #define  ADC_LOOP_MAX		(ADC_CHANLS_MAX - MSIC_BATT_SENSORS)
 
@@ -165,8 +165,8 @@
 #define MSIC_VAUDA_VAL		0xFF
 
 /*MSIC battery temperature  attributes*/
-#define MSIC_BTP_ADC_MIN		107
-#define MSIC_BTP_ADC_MAX		977
+#define MSIC_BTP_ADC_MIN	107
+#define MSIC_BTP_ADC_MAX	977
 
 
 /*convert adc_val to voltage mV */
@@ -197,9 +197,6 @@
 /* internal return values */
 #define BIT_SET		0
 #define BIT_RESET	1
-#define BATTSUCCESS	0
-#define EBATTFAIL	1
-#define EBATTERR	2
 #define NR_ARR_ELM_MAX	5
 
 /* IPC defines */
@@ -241,13 +238,13 @@ static struct device *msic_dev;
  */
 static int const therm_curve_data[THERM_CURVE_MAX_SAMPLES]
 						[THERM_CURVE_MAX_VALUES] = {
-				/* {temp_max, temp_min, adc_max, adc_min} */
-						{-10, -20, 977, 941},
-						{0, -10, 941, 887},
-						{10, 0, 887, 769},
-						{50, 10, 769, 357},
-						{75, 50, 357, 186},
-						{100, 75, 186, 107},
+	/* {temp_max, temp_min, adc_max, adc_min} */
+	{-10, -20, 977, 941},
+	{0, -10, 941, 887},
+	{10, 0, 887, 769},
+	{50, 10, 769, 357},
+	{75, 50, 357, 186},
+	{100, 75, 186, 107},
 };
 
 
@@ -324,8 +321,8 @@ struct msic_batt_props {
 	unsigned int charge_full;	/* in mAS */
 	unsigned int charge_now;	/* in mAS */
 	unsigned int charge_avg;	/* in units per second */
-	unsigned int capacity;	/* in units persentage */
-	unsigned int temperature; /* in milli Centigrade*/
+	unsigned int capacity;		/* in units persentage */
+	unsigned int temperature;	/* in milli Centigrade*/
 	char model[BATT_STRING_MAX];
 	char vender[BATT_STRING_MAX];
 };
@@ -339,10 +336,11 @@ struct msic_charg_props {
 	char charger_vender[BATT_STRING_MAX];
 };
 
-/* All Interrupt request are queued from Interrupt
- * handler and processed in the bottem half
+/*
+ * All interrupt request are queued from interrupt
+ * handler and processed in the bottom half
  */
-static DEFINE_KFIFO(irq_fifo, IRQ_FIFO_MAX);
+static DEFINE_KFIFO(irq_fifo, u32, IRQ_FIFO_MAX);
 
 /*
  * msic battery info
@@ -525,7 +523,7 @@ static void free_adc_channels(u16 ch_index, struct msic_power_module_info *mbi)
 	u16 base_addr;
 
 	base_addr = ADC_CHNL_START_ADDR + ch_index;
-	for (i = 0; (i < 4) && (base_addr < ADC_CHANLS_MAX); i++) {
+	for (i = 0; i < 4 && base_addr < ADC_CHANLS_MAX; i++) {
 		ret = intel_scu_ipc_iowrite8(base_addr, 0x0);
 		if (ret) {
 			dev_warn(&mbi->pdev->dev, "%s:ipc write failed\n",
@@ -546,7 +544,7 @@ static int reset_stopbit(uint16_t addr)
 	ret = intel_scu_ipc_ioread8(addr, &data);
 	if (ret)
 		return ret;
-	data &= ~MSIC_STOPBIT_MASK;	/*setting the stop bit to zero*/
+	data &= ~MSIC_STOPBIT_MASK;	/* setting the stop bit to zero */
 	ret = intel_scu_ipc_iowrite8(addr, data);
 	return ret;
 }
@@ -581,7 +579,7 @@ static int find_free_channel(struct msic_power_module_info *mbi)
 	}
 
 	if (i >= ADC_CHANLS_MAX-1) {
-		/* No STOP bit found, Retrun channel number as zero */
+		/* No STOP bit found, Return channel number as zero */
 		return 0;
 	}
 
@@ -601,7 +599,7 @@ static int find_free_channel(struct msic_power_module_info *mbi)
 		ret = reset_stopbit(ADC_CHNL_START_ADDR + i);
 		if (ret) {
 			dev_err(&mbi->pdev->dev,
-			"%s:intel_mdf_battery:ipc r/w failed", __func__);
+					"%s:ipc r/w failed", __func__);
 			return ret;
 		}
 	}
@@ -618,7 +616,7 @@ static int find_free_channel(struct msic_power_module_info *mbi)
  * @therm: struct thermal module info
  * Context: can sleep
  *
- * To initialize the adc for reading thermistor
+ * Unitialize the adc for reading thermistor
  * and converting the same into actual temp value
  * on the platform
  */
@@ -628,8 +626,8 @@ static int mdf_initialize_adc(struct msic_power_module_info *mbi)
 	int channel_index = -1;
 
 	channel_index = find_free_channel(mbi);
-	if (channel_index == -EINVAL)
-		return ret;
+	if (channel_index < 0)
+		return channel_index;
 
 	/* Program the free ADC channel */
 	ret = set_up_batt_pack_chnl(channel_index, mbi);
@@ -677,7 +675,6 @@ static int adc_to_temp(uint16_t adc_val)
 		return -ERANGE;
 
 	for (i = 0; i < THERM_CURVE_MAX_SAMPLES; i++) {
-
 		/* linear approximation for battery pack temperature*/
 		if (is_valid_temp_adc_range(adc_val, therm_curve_data[i][3],
 						therm_curve_data[i][2])) {
@@ -749,10 +746,8 @@ static int mdf_read_adc_regs(int sensor,
 	adc_val = (data << 2);
 	addr++;
 	ret = intel_scu_ipc_ioread8(addr, &data);/* reading lower bits */
-	if (ret) {
+	if (ret)
 		dev_warn(&mbi->pdev->dev, "%s:ipc read failed", __func__);
-		goto ipc_failed;;
-	}
 
 ipc_failed:
 	mutex_unlock(&mbi->ipc_rw_lock);
@@ -764,26 +759,24 @@ ipc_failed:
 
 	switch (sensor) {
 	case MSIC_ADC_VOL_IDX:
-				ret = MSIC_ADC_TO_VOL(adc_val);
-				break;
+		ret = MSIC_ADC_TO_VOL(adc_val);
+		break;
 	case MSIC_ADC_CUR_IDX:
-				ret = MSIC_ADC_TO_CUR(adc_val & 0x1FF);
-				/* if D9 bit is set battery is discharging */
-				if (adc_val & 0x200)
-					ret = -(MSIC_ADC_MAX_CUR - ret);
-				break;
+		ret = MSIC_ADC_TO_CUR(adc_val & 0x1FF);
+		/* if D9 bit is set battery is discharging */
+		if (adc_val & 0x200)
+			ret = -(MSIC_ADC_MAX_CUR - ret);
+		break;
 	case MSIC_ADC_TEMP_IDX:
-				ret = adc_to_temp(adc_val);
-				break;
+		ret = adc_to_temp(adc_val);
+		break;
 	case MSIC_ADC_USB_VOL_IDX:
-				ret = MSIC_ADC_TO_VBUS_VOL(adc_val);
-				break;
+		ret = MSIC_ADC_TO_VBUS_VOL(adc_val);
+		break;
 	default:
-		dev_err(&mbi->pdev->dev,
-			"intel_mdf_battery:invalid adc_code:%d", adc_val);
+		dev_err(&mbi->pdev->dev, "invalid adc_code:%d", adc_val);
 		ret = -EINVAL;
 	}
-
 	return ret;
 }
 
@@ -796,7 +789,6 @@ static unsigned int msic_read_coloumb_ctr(void)
 	err = intel_scu_ipc_command(IPCMSG_BATTERY, 0x01, NULL, 0, &cvalue, 1);
 	if (err)
 		dev_warn(msic_dev, "IPC Command Failed %s\n", __func__);
-
 	return cvalue;
 }
 
@@ -961,32 +953,30 @@ static void msic_log_exception_event(enum msic_event event)
 {
 	switch (event) {
 	case MSIC_EVENT_BATTOCP_EXCPT:
-		dev_warn(msic_dev, "msic-battery: over battery charge "
-					"current condition detected\n");
+		dev_warn(msic_dev,
+			"over battery charge current condition detected\n");
 		break;
 	case MSIC_EVENT_BATTOTP_EXCPT:
-		dev_warn(msic_dev, "msic-battery: high battery temperature "
-						"condition detected\n");
+		dev_warn(msic_dev,
+			"high battery temperature condition detected\n");
 		break;
 	case MSIC_EVENT_LOWBATT_EXCPT:
-		dev_warn(msic_dev, "msic-battery: Low battery voltage "
-						"condition detected\n");
+		dev_warn(msic_dev,
+			"Low battery voltage condition detected\n");
 		break;
 	case MSIC_EVENT_BATTOVP_EXCPT:
-		dev_warn(msic_dev, "msic-battery: battery overvoltage "
-						"condition detected\n");
+		dev_warn(msic_dev,
+			"battery overvoltage condition detected\n");
 		break;
 	case MSIC_EVENT_CHROTP_EXCPT:
-		dev_warn(msic_dev, "msic-charger: charger high temperature "
-							"condition detected\n");
+		dev_warn(msic_dev,
+			"charger high temperature condition detected\n");
 		break;
 	case MSIC_EVENT_USBOVP_EXCPT:
-		dev_warn(msic_dev, "USB over voltage "
-						"condition detected\n");
+		dev_warn(msic_dev, "USB over voltage condition detected\n");
 		break;
 	default:
-		dev_warn(msic_dev, "unknown error %u detected\n",
-								-EBATTERR);
+		dev_warn(msic_dev, "unknown error %u detected\n", event);
 		break;
 	}
 }
@@ -1067,43 +1057,58 @@ static void msic_handle_exception(struct msic_power_module_info *mbi,
 
 }
 
-
-static int msic_batt_stop_charging(struct msic_power_module_info *mbi)
+/**
+ *	msic_write_multi	-	multi-write helper
+ *	@mbi: msic power module
+ *	@address: addresses of IPC writes
+ *	@data: data for IPC writes
+ *	@n: size of write table
+ *
+ *	Write a series of values to the SCU while respecting the ipc_rw_lock
+ *	across the entire sequence. Handle any error reporting and pass back
+ *	error codes on failure
+ */
+static int msic_write_multi(struct msic_power_module_info *mbi,
+				const u16 *address, const u8 *data, int n)
 {
-	int retval, i;
-	static const uint16_t address[] = {
-				MSIC_BATT_CHR_WDTWRITE_ADDR,
-				MSIC_BATT_CHR_CHRCTRL_ADDR,
-				MSIC_BATT_CHR_WDTWRITE_ADDR,
-				MSIC_BATT_CHR_CHRSTWDT_ADDR,
-		};
-	static const unsigned char data[] = {
-				WDTWRITE_UNLOCK_VALUE, /* Unlock chrg params */
-				CHRCNTL_CHRG_DISABLE, /*  Disable Charging */
-				WDTWRITE_UNLOCK_VALUE, /* Unlock chrg params */
-				CHR_WDT_DISABLE, /*  Disable WDT Timer */
-		};
-
-	/*
-	 * Charger connect handler delayed work also modifies the
-	 * MSIC charger parameter registers.To avoid concurrent
-	 * read writes to same set of registers  locking applied
-	 */
+	int retval = 0, i;
 	mutex_lock(&mbi->ipc_rw_lock);
-	for (i = 0; i < 4; i++) {
-		retval = intel_scu_ipc_iowrite8(address[i], data[i]);
+	for (i = 0; i < n; i++) {
+		retval = intel_scu_ipc_iowrite8(*address++, *data++);
 		if (retval) {
 			dev_warn(&mbi->pdev->dev, "%s:ipc msic write failed\n",
 								__func__);
-			goto ipc_write_failed;
+			break;
 		}
 	}
-
-ipc_write_failed:
 	mutex_unlock(&mbi->ipc_rw_lock);
 	return retval;
 }
 
+static int msic_batt_stop_charging(struct msic_power_module_info *mbi)
+{
+	static const u16 address[] = {
+		MSIC_BATT_CHR_WDTWRITE_ADDR,
+		MSIC_BATT_CHR_CHRCTRL_ADDR,
+		MSIC_BATT_CHR_WDTWRITE_ADDR,
+		MSIC_BATT_CHR_CHRSTWDT_ADDR,
+	};
+	static const u8 data[] = {
+		WDTWRITE_UNLOCK_VALUE, /* Unlock chrg params */
+		CHRCNTL_CHRG_DISABLE, /*  Disable Charging */
+		WDTWRITE_UNLOCK_VALUE, /* Unlock chrg params */
+		CHR_WDT_DISABLE, /*  Disable WDT Timer */
+	};
+
+	/*
+	 * Charger connect handler delayed work also modifies the
+	 * MSIC charger parameter registers.To avoid concurrent
+	 * read writes to same set of registers  locking applied by
+	 * msic_write_multi
+	 */
+	return msic_write_multi(mbi, address, data, 4);
+}
+
 /**
  * msic_batt_do_charging - set battery charger
  * @mbi: device info structure
@@ -1116,54 +1121,34 @@ ipc_write_failed:
 static int msic_batt_do_charging(struct msic_power_module_info *mbi,
 						struct charge_params *params)
 {
-	int retval, i;
-	uint16_t wdtwrite_addr;
-	uint8_t wdtwrite = WDTWRITE_UNLOCK_VALUE;
-	unsigned char data[4];
-	static const uint16_t address[] = {
-				MSIC_BATT_CHR_CHRCCURRENT_ADDR,
-				MSIC_BATT_CHR_CHRCVOLTAGE_ADDR,
-				MSIC_BATT_CHR_CHRCTRL_ADDR,
-				MSIC_BATT_CHR_CHRSTWDT_ADDR,
-		};
-
-	if (!params) {
-		dev_warn(msic_dev, "%s:ipc msic write failed\n", __func__);
-		return -EBATTFAIL;
-	}
-
-	data[0] = params->ccur;
-	data[1] = params->cvol; /* charge voltage 4.14V */
-	data[2] = params->vinilmt;
-	data[3] = CHR_WDT_SET_60SEC;  /* WTD Timer set to 60 Sec */
-
-	/* to unlock charger control regs */
-	wdtwrite_addr = MSIC_BATT_CHR_WDTWRITE_ADDR;
+	int retval;
+	static u8 data[8] = {
+		WDTWRITE_UNLOCK_VALUE, 0,
+		WDTWRITE_UNLOCK_VALUE, 0,
+		WDTWRITE_UNLOCK_VALUE, 0,
+		WDTWRITE_UNLOCK_VALUE, CHR_WDT_SET_60SEC
+	};
+	static const u16 address[] = {
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRCCURRENT_ADDR,
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRCVOLTAGE_ADDR,
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRCTRL_ADDR,
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRSTWDT_ADDR
+	};
+
+	data[1] = params->ccur;
+	data[3] = params->cvol; /* charge voltage 4.14V */
+	data[5] = params->vinilmt;
 
 	/*
 	 * Charger disconnect handler also modifies the
 	 * MSIC charger parameter registers.To avoid concurrent
 	 * read writes to same set of registers  locking applied
 	 */
-	mutex_lock(&mbi->ipc_rw_lock);
-	for (i = 0; i < 4; i++) {
-		retval = intel_scu_ipc_iowrite8(wdtwrite_addr, wdtwrite);
-		if (retval) {
-			dev_warn(msic_dev, "%s:ipc msic write failed\n",
-								__func__);
-			mutex_unlock(&mbi->ipc_rw_lock);
-			return retval;
-		}
-		retval = intel_scu_ipc_iowrite8(address[i], data[i]);
-		if (retval) {
-			dev_warn(msic_dev, "%s:ipc msic write failed\n",
-								__func__);
-			mutex_unlock(&mbi->ipc_rw_lock);
-			return retval;
-		}
-	}
-	mutex_unlock(&mbi->ipc_rw_lock);
-	dev_info(msic_dev, "Charger Enabled\n");
+	retval = msic_write_multi(mbi, address, data, 8);
+	if (retval < 0)
+		return retval;
+
+	dev_dbg(msic_dev, "Charger Enabled\n");
 
 	mutex_lock(&mbi->batt_lock);
 	mbi->batt_props.status = POWER_SUPPLY_STATUS_CHARGING;
@@ -1176,41 +1161,32 @@ static int msic_batt_do_charging(struct msic_power_module_info *mbi,
 	memcpy(mbi->usb_chrg_props.charger_model, "msic", sizeof("msic"));
 	memcpy(mbi->usb_chrg_props.charger_vender, "Intel", sizeof("Intel"));
 
-	if (mbi->ch_params.vinilmt == CHRG_CURR_SDP_LOW) {
+	if (mbi->ch_params.vinilmt == CHRG_CURR_SDP_LOW)
 		mbi->usb_chrg_props.charger_type =
 					POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
-	} else {
+	else
 		mbi->usb_chrg_props.charger_type =
 					POWER_SUPPLY_CHARGE_TYPE_FAST;
-	}
-	mutex_unlock(&mbi->usb_chrg_lock);
 
-	return BATTSUCCESS;
+	mutex_unlock(&mbi->usb_chrg_lock);
+	return 0;
 }
 
 static void reset_wdt_timer(struct msic_power_module_info *mbi)
 {
-	int retval;
+	static const u16 address[2] = {
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRSTWDT_ADDR
+	};
+	static const u8 data[2] = {
+		WDTWRITE_UNLOCK_VALUE, CHR_WDT_SET_60SEC
+	};
 
 	/*
 	 * Charger disconnect handler also modifies the
 	 * MSIC charger parameter registers.To avoid concurrent
 	 * read writes to same set of registers  locking applied
 	 */
-	mutex_lock(&mbi->ipc_rw_lock);
-	retval = intel_scu_ipc_iowrite8(MSIC_BATT_CHR_WDTWRITE_ADDR,
-						WDTWRITE_UNLOCK_VALUE);
-	if (retval) {
-		dev_warn(msic_dev, "%s:ipc msic write failed\n", __func__);
-		goto ipc_failed;
-	}
-	/* WDT timer set to 60 Sec */
-	retval = intel_scu_ipc_iowrite8(MSIC_BATT_CHR_CHRSTWDT_ADDR,
-							CHR_WDT_SET_60SEC);
-	if (retval)
-		dev_warn(msic_dev, "%s:ipc msic write failed\n", __func__);
-ipc_failed:
-	mutex_unlock(&mbi->ipc_rw_lock);
+	msic_write_multi(mbi, address, data, 2);
 }
 
 static void msic_update_disconn_status(struct msic_power_module_info *mbi)
@@ -1358,7 +1334,7 @@ static void msic_batt_temp_charging(struct work_struct *work)
 			 * range so just write the WDT timer and
 			 * schedule the wirk again.
 			 */
-			dev_info(msic_dev, "NoChange in Temp Range\n");
+			dev_dbg(msic_dev, "NoChange in Temp Range\n");
 			/* Reset WDT Timer Register for 60 Sec */
 			reset_wdt_timer(mbi);
 			goto lbl_sched_work;
@@ -1381,7 +1357,7 @@ static void msic_batt_temp_charging(struct work_struct *work)
 	vinlimit |= 0x08;
 	charge_param.vinilmt = vinlimit;
 
-	dev_info(msic_dev, "params  vol: %x  cur:%x vinilmt:%x\n",
+	dev_dbg(msic_dev, "params  vol: %x  cur:%x vinilmt:%x\n",
 		charge_param.cvol, charge_param.ccur, charge_param.vinilmt);
 
 	/* enable charging here */
@@ -1406,8 +1382,8 @@ static void msic_batt_disconn(struct work_struct *work)
 
 	ret = msic_batt_stop_charging(mbi);
 	if (ret) {
-		dev_info(msic_dev, "%s: failed\n", __func__);
-		return ;
+		dev_dbg(msic_dev, "%s: failed\n", __func__);
+		return;
 	}
 	msic_update_disconn_status(mbi);
 	power_supply_changed(&mbi->batt);
@@ -1446,45 +1422,44 @@ static int msic_charger_callback(void *arg, int event, struct otg_bc_cap *cap)
 	case USBCHRG_EVENT_CONNECT:
 	case USBCHRG_EVENT_RESUME:
 	case USBCHRG_EVENT_UPDATE:
-			/*
-			 * If previous event CONNECT and current is event is
-			 * UPDATE, we have already queued the work.
-			 * Its better to dequeue the previous work
-			 * and add the new work to the queue.
-			 */
-			cancel_delayed_work(&mbi->connect_handler);
+		/*
+		 * If previous event CONNECT and current is event is
+		 * UPDATE, we have already queued the work.
+		 * Its better to dequeue the previous work
+		 * and add the new work to the queue.
+		 */
+		cancel_delayed_work(&mbi->connect_handler);
 
-			if (pm_runtime_suspended(&mbi->pdev->dev))
-				pm_runtime_get_sync(&mbi->pdev->dev);
-			/* minimum charge current is 550 mA */
-			mbi->ch_params.vinilmt = cap->mA;
-			mbi->ch_params.chrg_type = cap->chrg_type;
-			dev_info(msic_dev, "CHRG TYPE:%d %d\n",
-						cap->chrg_type, cap->mA);
+		if (pm_runtime_suspended(&mbi->pdev->dev))
+			pm_runtime_get_sync(&mbi->pdev->dev);
+		/* minimum charge current is 550 mA */
+		mbi->ch_params.vinilmt = cap->mA;
+		mbi->ch_params.chrg_type = cap->chrg_type;
+		dev_dbg(msic_dev, "CHRG TYPE:%d %d\n",
+					cap->chrg_type, cap->mA);
 
-			schedule_delayed_work(&mbi->connect_handler, 0);
+		schedule_delayed_work(&mbi->connect_handler, 0);
 
-			spin_lock(&mbi->event_lock);
-			mbi->charging_mode = BATT_CHARGING_MODE_NORMAL;
-			spin_unlock(&mbi->event_lock);
+		spin_lock(&mbi->event_lock);
+		mbi->charging_mode = BATT_CHARGING_MODE_NORMAL;
+		spin_unlock(&mbi->event_lock);
 
-			break;
+		break;
 	case USBCHRG_EVENT_DISCONN:
 	case USBCHRG_EVENT_SUSPEND:
-			dev_info(msic_dev, "USB DISCONN or SUSPEND\n");
-			cancel_delayed_work(&mbi->connect_handler);
-			schedule_delayed_work(&mbi->disconn_handler, 0);
+		dev_dbg(msic_dev, "USB DISCONN or SUSPEND\n");
+		cancel_delayed_work(&mbi->connect_handler);
+		schedule_delayed_work(&mbi->disconn_handler, 0);
 
-			spin_lock(&mbi->event_lock);
-			mbi->charging_mode = BATT_CHARGING_MODE_NONE;
-			spin_unlock(&mbi->event_lock);
-			if (!pm_runtime_suspended(&mbi->pdev->dev))
-				pm_runtime_put_sync(&mbi->pdev->dev);
-			break;
+		spin_lock(&mbi->event_lock);
+		mbi->charging_mode = BATT_CHARGING_MODE_NONE;
+		spin_unlock(&mbi->event_lock);
+		if (!pm_runtime_suspended(&mbi->pdev->dev))
+			pm_runtime_put_sync(&mbi->pdev->dev);
+		break;
 	default:
 		dev_warn(msic_dev, "Invalid OTG Event:%s\n", __func__);
 	}
-
 	return 0;
 }
 
@@ -1498,8 +1473,7 @@ static int msic_charger_callback(void *arg, int event, struct otg_bc_cap *cap)
  */
 static irqreturn_t msic_battery_interrupt_handler(int id, void *dev)
 {
-	struct msic_power_module_info *mbi =
-				(struct msic_power_module_info *)dev;
+	struct msic_power_module_info *mbi = dev;
 	u32 reg_int_val;
 
 	/* We have only one concurrent fifo reader
@@ -1532,8 +1506,7 @@ static irqreturn_t msic_battery_thread_handler(int id, void *dev)
 	int err, ret;
 	uint32_t batt_charge_val;
 	unsigned char data[2];
-	struct msic_power_module_info *mbi =
-					(struct msic_power_module_info *)dev;
+	struct msic_power_module_info *mbi = dev;
 	u32 tmp;
 
 	/* We have only one concurrent fifo reader
@@ -1555,13 +1528,13 @@ static irqreturn_t msic_battery_thread_handler(int id, void *dev)
 	/* CHRINT1 Register */
 	data[1] = (tmp & 0xff000000) >> 24;
 
-	dev_info(msic_dev, "PWRSRC Int %x %x\n", tmp & 0xff,
+	dev_dbg(msic_dev, "PWRSRC Int %x %x\n", tmp & 0xff,
 						(tmp & 0xff00) >> 8);
-	dev_info(msic_dev, "CHR Int %x %x\n", data[0], data[1]);
+	dev_dbg(msic_dev, "CHR Int %x %x\n", data[0], data[1]);
 
 	/* Check if charge complete */
 	if (data[1] & MSIC_BATT_CHR_CHRCMPLT_MASK) {
-		dev_info(msic_dev, "CHRG COMPLT\n");
+		dev_dbg(msic_dev, "CHRG COMPLT\n");
 		/* Disable Charging */
 		msic_batt_stop_charging(mbi);
 
@@ -1583,7 +1556,7 @@ static irqreturn_t msic_battery_thread_handler(int id, void *dev)
 	if ((data[1] & MSIC_BATT_CHR_WKVINDET_MASK) ||
 		(data[1] & MSIC_BATT_CHR_VINREGMINT_MASK)) {
 
-		dev_info(msic_dev, "WEAK VIN or VINREGMINT DETCTED\n");
+		dev_dbg(msic_dev, "WEAK VIN or VINREGMINT DETCTED\n");
 
 		spin_lock(&mbi->event_lock);
 		/* Sometimes we may get weakVIN because of VBUS voltage
@@ -1602,13 +1575,13 @@ static irqreturn_t msic_battery_thread_handler(int id, void *dev)
 			msic_charger_callback(mbi, USBCHRG_EVENT_SUSPEND, NULL);
 		} else {
 			spin_unlock(&mbi->event_lock);
-			dev_info(msic_dev, "WeakVIN when No charger preset\n");
+			dev_dbg(msic_dev, "WeakVIN when No charger preset\n");
 		}
 	}
 
 	/* Check if total charge time expired */
 	if (data[0] & MSIC_BATT_CHR_TIMEEXP_MASK) {
-		dev_info(msic_dev, "CHR TIMER EXP\n");
+		dev_dbg(msic_dev, "CHR TIMER EXP\n");
 		mutex_lock(&mbi->batt_lock);
 		mbi->batt_props.status = POWER_SUPPLY_STATUS_NOT_CHARGING;
 		mutex_unlock(&mbi->batt_lock);
@@ -1798,43 +1771,26 @@ static void init_charger_props(struct msic_power_module_info *mbi)
  * init_msic_regs function initializes the
  * MSIC registers like CV,Power Source LMT,etc..
  */
-static void init_msic_regs(struct msic_power_module_info *mbi)
+static int init_msic_regs(struct msic_power_module_info *mbi)
 {
-	uint16_t wdtwrite_addr;
-	int retval, i;
-	uint16_t address[] = {
-			MSIC_BATT_CHR_PWRSRCLMT_ADDR,
-			MSIC_BATT_CHR_CHRCVOLTAGE_ADDR,
-			MSIC_BATT_CHR_CHRTTIME_ADDR,
-			MSIC_BATT_CHR_SPCHARGER_ADDR,
-			MSIC_BATT_CHR_CHRSTWDT_ADDR,
-		};
-	unsigned char data[NR_ARR_ELM_MAX];
-
-	wdtwrite_addr = MSIC_BATT_CHR_WDTWRITE_ADDR;
-	/* Safe Temp window set from 0 to 60 Degree Centigrades */
-	data[0] = CHR_PWRSRCLMT_SET_RANGE;
-	/* Setting CV to 4.14V */
-	data[1] = CONV_VOL_DEC_MSICREG(CHR_CHRVOLTAGE_SET_DEF);
-	data[2] = CHR_CHRTIME_SET_12HRS; /* set charge timer to 12 hrs */
-	/* Disable LOWCHR and Set WeakVin to 4.52V */
-	data[3] = (~CHR_SPCHRGER_LOWCHR_ENABLE &
-			CHR_SPCHRGER_WEAKVIN);
-	data[4] = CHR_WDT_DISABLE;  /* disable WDT timer */
-
-	for (i = 0; i < NR_ARR_ELM_MAX; i++) {
-		retval = intel_scu_ipc_iowrite8(wdtwrite_addr,
-						WDTWRITE_UNLOCK_VALUE);
-		if (retval) {
-			dev_warn(msic_dev, "%s:ipc msic write failed\n",
-								__func__);
-		}
-		retval = intel_scu_ipc_iowrite8(address[i], data[i]);
-		if (retval) {
-			dev_warn(msic_dev, "%s:ipc msic write failed\n",
-								__func__);
-		}
-	}
+	static const u16 address[] = {
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_PWRSRCLMT_ADDR,
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRCVOLTAGE_ADDR,
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRTTIME_ADDR,
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_SPCHARGER_ADDR,
+		MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRSTWDT_ADDR,
+	};
+	static u8 data[] = {
+		WDTWRITE_UNLOCK_VALUE, CHR_PWRSRCLMT_SET_RANGE,
+		WDTWRITE_UNLOCK_VALUE,
+			CONV_VOL_DEC_MSICREG(CHR_CHRVOLTAGE_SET_DEF),
+		WDTWRITE_UNLOCK_VALUE, CHR_CHRTIME_SET_12HRS,
+		WDTWRITE_UNLOCK_VALUE,
+			(~CHR_SPCHRGER_LOWCHR_ENABLE & CHR_SPCHRGER_WEAKVIN),
+		WDTWRITE_UNLOCK_VALUE, CHR_WDT_DISABLE
+	};
+
+	return msic_write_multi(mbi, address, data, 10);
 }
 
 
@@ -1904,7 +1860,9 @@ static int msic_battery_probe(struct platform_device *pdev)
 	}
 
 	/* Init MSIC Registers */
-	init_msic_regs(mbi);
+	retval = init_msic_regs(mbi);
+	if (retval < 0)
+		goto init_failed;
 
 	/* Initialize ADC Channels */
 	mbi->adc_index = mdf_initialize_adc(mbi);
@@ -1976,6 +1934,7 @@ otg_failed:
 power_reg_failed_usb:
 	power_supply_unregister(&mbi->batt);
 power_reg_failed_batt:
+init_failed:
 	iounmap(mbi->msic_regs_iomap);
 ioremap_failed:
 	kfree(sfi_table);
@@ -2031,10 +1990,10 @@ static int msic_battery_suspend(struct platform_device *pdev,
 
 		msic_charger_callback(mbi, USBCHRG_EVENT_SUSPEND, NULL);
 
-		dev_info(&mbi->pdev->dev, "Forced  suspend\n");
+		dev_dbg(&mbi->pdev->dev, "Forced suspend\n");
 	}
 
-	return BATTSUCCESS;
+	return 0;
 }
 
 static int msic_battery_resume(struct platform_device *pdev)
@@ -2067,15 +2026,15 @@ static int msic_runtime_suspend(struct device *dev)
 {
 
 	/* ToDo: Check for MSIC Power rails */
-	dev_info(dev, "%s called\n", __func__);
-	return BATTSUCCESS;
+	dev_dbg(dev, "%s called\n", __func__);
+	return 0;
 }
 
 static int msic_runtime_resume(struct device *dev)
 {
 	/* ToDo: Check for MSIC Power rails */
-	dev_info(dev, "%s called\n", __func__);
-	return BATTSUCCESS;
+	dev_dbg(dev, "%s called\n", __func__);
+	return 0;
 }
 
 static int msic_runtime_idle(struct device *dev)
@@ -2085,7 +2044,7 @@ static int msic_runtime_idle(struct device *dev)
 	struct msic_power_module_info *mbi = platform_get_drvdata(pdev);
 	int event;
 
-	dev_info(dev, "%s called\n", __func__);
+	dev_dbg(dev, "%s called\n", __func__);
 
 	spin_lock(&mbi->event_lock);
 	event = mbi->batt_event;
@@ -2095,12 +2054,12 @@ static int msic_runtime_idle(struct device *dev)
 		event == USBCHRG_EVENT_UPDATE ||
 		event == USBCHRG_EVENT_RESUME) {
 
-		dev_warn(&mbi->pdev->dev, "%s(): devise busy\n", __func__);
+		dev_warn(&mbi->pdev->dev, "%s: device busy\n", __func__);
 
 		return -EBUSY;
 	}
 
-	return BATTSUCCESS;
+	return 0;
 }
 #else
 #define msic_runtime_suspend	NULL