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authorHao Wu <hao.wu@intel.com>2010-12-09 10:37:42 +0000
committerAlan Cox <alan@linux.intel.com>2010-12-09 10:37:42 +0000
commit9a8304cfe883edf5ef669205d089326eeb6ed241 (patch)
treef7be4e5cb6f3e3522e8f3a984e11b3aac3bc16e8 /drivers
parentd36d824c696bcc02eb81e80af5f2865ccb48b2b1 (diff)
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usb: langwell_otg: use simple IPC command to control VBus power
Direct access to PMIC register is not safe and will impact battery charging. New IPC command supported in SCU FW for VBus power control. USB OTG driver will switch to such commands instead of direct access to PMIC register for safety and SCU FW will handle the actual work after got the request(IPC command). Due to this change, usb driver should wait more time for sync OTGSC with USBCFG by SCU. Update wait time from 2ms to 5ms. Signed-off-by: Hao Wu <hao.wu@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/usb/otg/langwell_otg.c48
1 files changed, 11 insertions, 37 deletions
diff --git a/drivers/usb/otg/langwell_otg.c b/drivers/usb/otg/langwell_otg.c
index 9fea48264fa..7f9b8cd4514 100644
--- a/drivers/usb/otg/langwell_otg.c
+++ b/drivers/usb/otg/langwell_otg.c
@@ -174,50 +174,24 @@ static int langwell_otg_set_power(struct otg_transceiver *otg,
return 0;
}
-/* A-device drives vbus, controlled through PMIC CHRGCNTL register*/
+/* A-device drives vbus, controlled through IPC commands */
static int langwell_otg_set_vbus(struct otg_transceiver *otg, bool enabled)
{
struct langwell_otg *lnw = the_transceiver;
- u8 r;
+ u8 sub_id;
dev_dbg(lnw->dev, "%s <--- %s\n", __func__, enabled ? "on" : "off");
- /* FIXME: surely we should cache this on the first read. If not use
- readv to avoid two transactions */
- if (intel_scu_ipc_ioread8(0x00, &r) < 0) {
- dev_dbg(lnw->dev, "Failed to read PMIC register 0xD2");
- return -EBUSY;
- }
- if ((r & 0x03) != 0x02) {
- dev_dbg(lnw->dev, "not NEC PMIC attached\n");
- return -EBUSY;
- }
-
- if (intel_scu_ipc_ioread8(0x20, &r) < 0) {
- dev_dbg(lnw->dev, "Failed to read PMIC register 0xD2");
- return -EBUSY;
- }
-
- if ((r & 0x20) == 0) {
- dev_dbg(lnw->dev, "no battery attached\n");
- return -EBUSY;
- }
+ if (enabled)
+ sub_id = 0x8; /* Turn on the VBus */
+ else
+ sub_id = 0x9; /* Turn off the VBus */
- /* Workaround for battery attachment issue */
- if (r == 0x34) {
- dev_dbg(lnw->dev, "no battery attached on SH\n");
+ if (intel_scu_ipc_simple_command(0xef, sub_id)) {
+ dev_dbg(lnw->dev, "Failed to set Vbus via IPC commands\n");
return -EBUSY;
}
- dev_dbg(lnw->dev, "battery attached. 2 reg = %x\n", r);
-
- /* workaround: FW detect writing 0x20/0xc0 to d4 event.
- * this is only for NEC PMIC.
- */
-
- if (intel_scu_ipc_iowrite8(0xD4, enabled ? 0x20 : 0xC0))
- dev_dbg(lnw->dev, "Failed to write PMIC.\n");
-
dev_dbg(lnw->dev, "%s --->\n", __func__);
return 0;
@@ -394,14 +368,14 @@ static void langwell_otg_phy_low_power(int on)
dev_dbg(lnw->dev, "%s <--- done\n", __func__);
}
-/* After drv vbus, add 2 ms delay to set PHCD */
+/* After drv vbus, add 5 ms delay to set PHCD */
static void langwell_otg_phy_low_power_wait(int on)
{
struct langwell_otg *lnw = the_transceiver;
- dev_dbg(lnw->dev, "add 2ms delay before programing PHCD\n");
+ dev_dbg(lnw->dev, "add 5ms delay before programing PHCD\n");
- mdelay(2);
+ mdelay(5);
langwell_otg_phy_low_power(on);
}