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authorJacob Pan <jacob.jun.pan@intel.com>2010-12-09 10:37:42 +0000
committerAlan Cox <alan@linux.intel.com>2010-12-09 10:37:42 +0000
commitf26ab70974967a94eaac9390dc65bb5836a98ee6 (patch)
tree8d80ad1a6cec03e58c36ee4b1f4709ff7715fe0a /drivers/usb/host/ehci.h
parent6be72e9b54479e7a2c473bc6cc778319e5f925e3 (diff)
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ehci: Support Intel Moorestown EHCI controller SRAM QH/QTD/ITD/SITD pool caching
The Intel Moorestown platform has MPH and OTG EHCI controllers that have internal SRAM that could be used as descriptors DMA pool caching. The SRAM is exposed via PCI BAR1. The limitation here is the SRAM access should be 32bit aligned. A separate patch "EHCI: Make ehci_qh structure items all 32bit aligned" has been submitted to linux-usb mailling list. Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com> Signed-off-by: Alek Du <alek.du@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com>
Diffstat (limited to 'drivers/usb/host/ehci.h')
-rw-r--r--drivers/usb/host/ehci.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index d78a781a49b..7a6de9c6e51 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -148,6 +148,8 @@ struct ehci_hcd { /* one per controller */
unsigned has_otg:1; /* if it is otg host*/
u8 sbrn; /* packed release number */
+ unsigned int sram_addr;
+ unsigned int sram_size;
/* irq statistics */
#ifdef EHCI_STATS
@@ -733,5 +735,9 @@ static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
#endif /* DEBUG */
/*-------------------------------------------------------------------------*/
-
+#ifdef CONFIG_PCI
+static void sram_deinit(struct usb_hcd *hcd);
+#else
+static void sram_deinit(struct usb_hcd *hcd) { return; };
+#endif
#endif /* __LINUX_EHCI_HCD_H */