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authorAlek Du <alek.du@intel.com>2010-12-09 10:37:41 +0000
committerAlan Cox <alan@linux.intel.com>2010-12-09 10:37:41 +0000
commit6be72e9b54479e7a2c473bc6cc778319e5f925e3 (patch)
tree00735e849a556a9b840059df654de80af040db97 /drivers/usb/host/ehci-pci.c
parent313db3b6702f31eed174bff7104c6126c518f51e (diff)
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ehci: Support for Intel Moorestown MPH and OTG host
The Intel Moorestown platform has EHCI MPH and EHCI OTG host. This patch adds PCI probe part for them. The HNP part and SRAM part will be added in another patch. This patch depends on the OTG transceive and OTG client patch from Hang Yuan that should be accepted already. Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com> Signed-off-by: Alek Du <alek.du@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Hao Wu <hao.wu@intel.com>
Diffstat (limited to 'drivers/usb/host/ehci-pci.c')
-rw-r--r--drivers/usb/host/ehci-pci.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 655f3c9f88b..c3637bb299c 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -50,6 +50,7 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
u8 rev;
u32 temp;
int retval;
+ int force_otg_hc_mode = 0;
switch (pdev->vendor) {
case PCI_VENDOR_ID_TOSHIBA_2:
@@ -63,6 +64,18 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
#endif
}
break;
+ case PCI_VENDOR_ID_INTEL:
+ if (pdev->device == 0x0811) {
+ ehci_info(ehci, "Detected Langwell OTG HC\n");
+ hcd->has_tt = 1;
+ ehci->has_hostpc = 1;
+ ehci->has_otg = 1;
+ force_otg_hc_mode = 1;
+ } else if (pdev->device == 0x0806) {
+ ehci_info(ehci, "Detected Langwell MPH\n");
+ hcd->has_tt = 1;
+ ehci->has_hostpc = 1;
+ }
}
ehci->caps = hcd->regs;
@@ -98,6 +111,8 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
/* cache this readonly data; minimize chip reads */
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+ if (force_otg_hc_mode)
+ ehci_reset(ehci);
retval = ehci_halt(ehci);
if (retval)