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authorAjit Khaparde <ajitk@serverengines.com>2010-07-29 06:16:33 +0000
committerDavid S. Miller <davem@davemloft.net>2010-07-30 23:59:05 -0700
commit7c185276e8d820fa50a678c61abd611ee599920e (patch)
tree5c8b5ac0e55eb2bafca470da939177ecc52a9755 /drivers/net/benet/be_hw.h
parent6dedec818ac2a3783581a761b0680e713f78afde (diff)
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be2net: add code to dump registers for debug
when the BE device becomes unresponsive, dump the registers to help debugging Signed-off-by: Somnath K <somnathk@serverengines.com> Signed-off-by: Ajit Khaparde <ajitk@serverengines.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/benet/be_hw.h')
-rw-r--r--drivers/net/benet/be_hw.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/benet/be_hw.h b/drivers/net/benet/be_hw.h
index 06839676e3c..6c8f9bb8bfe 100644
--- a/drivers/net/benet/be_hw.h
+++ b/drivers/net/benet/be_hw.h
@@ -56,6 +56,16 @@
#define PCICFG_PM_CONTROL_OFFSET 0x44
#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
+/********* Online Control Registers *******/
+#define PCICFG_ONLINE0 0xB0
+#define PCICFG_ONLINE1 0xB4
+
+/********* UE Status and Mask Registers ***/
+#define PCICFG_UE_STATUS_LOW 0xA0
+#define PCICFG_UE_STATUS_HIGH 0xA4
+#define PCICFG_UE_STATUS_LOW_MASK 0xA8
+#define PCICFG_UE_STATUS_HI_MASK 0xAC
+
/********* ISR0 Register offset **********/
#define CEV_ISR0_OFFSET 0xC18
#define CEV_ISR_SIZE 4