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authorAndreas Herrmann <andreas.herrmann3@amd.com>2010-09-17 18:02:54 +0200
committerH. Peter Anvin <hpa@linux.intel.com>2010-09-17 13:26:21 -0700
commit900f9ac9f12dc3dd6fc8e33e16df172eafcaead6 (patch)
tree7fb7bf3a150f8a3cc513e1bf6bd842e4ad213473 /drivers/edac/amd64_edac.c
parent3518dd14ca888085797ca8d3a9e11c8ef9e7ae68 (diff)
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x86, k8-gart: Decouple handling of garts and northbridges
So far we only provide num_k8_northbridges. This is required in different areas (e.g. L3 cache index disable, GART). But not all AMD CPUs provide a GART. Thus it is useful to split off the GART handling from the generic caching of AMD northbridge misc devices. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100917160254.GC4958@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'drivers/edac/amd64_edac.c')
-rw-r--r--drivers/edac/amd64_edac.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index e7d5d6b5dcf..5babf6f4805 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2927,7 +2927,7 @@ static int __init amd64_edac_init(void)
* to finish initialization of the MC instances.
*/
err = -ENODEV;
- for (nb = 0; nb < num_k8_northbridges; nb++) {
+ for (nb = 0; nb < k8_northbridges.num; nb++) {
if (!pvt_lookup[nb])
continue;