aboutsummaryrefslogtreecommitdiffstats
path: root/block
diff options
context:
space:
mode:
authorAndi Kleen <ak@suse.de>2006-03-08 17:57:25 -0800
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-08 18:10:31 -0800
commitf9262c12c0084ddba445a9a42e98994018e51400 (patch)
treeb54948e654e68c1e5263d955c76bf3a41dfa14da /block
parent979ce809bab37cf438f0db22bfa732d01a84a8c2 (diff)
downloadmrst-s0i3-test-f9262c12c0084ddba445a9a42e98994018e51400.tar.gz
mrst-s0i3-test-f9262c12c0084ddba445a9a42e98994018e51400.tar.xz
mrst-s0i3-test-f9262c12c0084ddba445a9a42e98994018e51400.zip
[PATCH] i386: port ATI timer fix from x86_64 to i386 II
ATI chipsets tend to generate double timer interrupts for the local APIC timer when both the 8254 and the IO-APIC timer pins are enabled. This is because they route it to both and the result is anded together and the CPU ends up processing it twice. This patch changes check_timer to disable the 8254 routing for interrupt 0. I think it would be safe on all chipsets actually (i tested it on a couple and it worked everywhere) and Windows seems to do it in a similar way, but to be conservative this patch only enables this mode on ATI (and adds options to enable/disable too) Ported over from a similar x86-64 change. I reused the ACPI earlyquirk infrastructure for the ATI bridge check, but tweaked it a bit to work even without ACPI. Inspired by a patch from Chuck Ebbert, but redone. Cc: Chuck Ebbert <76306.1226@compuserve.com> Cc: "Brown, Len" <len.brown@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'block')
0 files changed, 0 insertions, 0 deletions