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authorH. Peter Anvin <hpa@linux.intel.com>2010-12-14 15:00:27 -0800
committerH. Peter Anvin <hpa@linux.intel.com>2010-12-14 15:00:27 -0800
commita816ab366b55f39c08ebaba59d0e84a403e8b36a (patch)
tree206c994c0b75e6a4fc05dd390cfa5a14fdded56a /arch
parente203358312b4762936de133caf00b126c115952c (diff)
downloadmrst-s0i3-test-s0i3-pm-test.tar.gz
mrst-s0i3-test-s0i3-pm-test.tar.xz
mrst-s0i3-test-s0i3-pm-test.zip
s0i3: add hooks into the PCI PM layer - not functional yets0i3-pm-test
Try to add hooks into the PCI power management layer. They do not work yet. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/mrst.h5
-rw-r--r--arch/x86/pci/mrst.c2
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index 719f00b28ff..81ade903546 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -61,5 +61,10 @@ extern void intel_scu_devices_destroy(void);
/*#define MRST_VRTC_PGOFFSET (0xc00) */
extern void mrst_rtc_init(void);
+#ifdef CONFIG_MRST_S0I3
+extern void s0i3_pci_init(void);
+#else
+static inline void s0i3_pci_init(void) { }
+#endif
#endif /* _ASM_X86_MRST_H */
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index cb29191cee5..cf708773610 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -31,6 +31,7 @@
#include <asm/pci_x86.h>
#include <asm/hw_irq.h>
#include <asm/io_apic.h>
+#include <asm/mrst.h>
#define PCIE_CAP_OFFSET 0x100
@@ -235,6 +236,7 @@ int __init pci_mrst_init(void)
pci_mmcfg_late_init();
pcibios_enable_irq = mrst_pci_irq_enable;
pci_root_ops = pci_mrst_ops;
+ s0i3_pci_init();
/* Continue with standard init */
return 1;
}