path: root/arch/x86/include/asm/k8.h
diff options
authorAndreas Herrmann <andreas.herrmann3@amd.com>2010-09-17 18:02:54 +0200
committerH. Peter Anvin <hpa@linux.intel.com>2010-09-17 13:26:21 -0700
commit900f9ac9f12dc3dd6fc8e33e16df172eafcaead6 (patch)
tree7fb7bf3a150f8a3cc513e1bf6bd842e4ad213473 /arch/x86/include/asm/k8.h
parent3518dd14ca888085797ca8d3a9e11c8ef9e7ae68 (diff)
x86, k8-gart: Decouple handling of garts and northbridges
So far we only provide num_k8_northbridges. This is required in different areas (e.g. L3 cache index disable, GART). But not all AMD CPUs provide a GART. Thus it is useful to split off the GART handling from the generic caching of AMD northbridge misc devices. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100917160254.GC4958@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/include/asm/k8.h')
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/x86/include/asm/k8.h b/arch/x86/include/asm/k8.h
index af00bd1d208..9cee145dcac 100644
--- a/arch/x86/include/asm/k8.h
+++ b/arch/x86/include/asm/k8.h
@@ -7,24 +7,27 @@ extern struct pci_device_id k8_nb_ids[];
struct bootnode;
extern int early_is_k8_nb(u32 value);
-extern struct pci_dev **k8_northbridges;
-extern int num_k8_northbridges;
extern int cache_k8_northbridges(void);
extern void k8_flush_garts(void);
extern int k8_get_nodes(struct bootnode *nodes);
extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
extern int k8_scan_nodes(void);
+struct k8_northbridge_info {
+ u16 num;
+ u8 gart_supported;
+ struct pci_dev **nb_misc;
+extern struct k8_northbridge_info k8_northbridges;
#ifdef CONFIG_K8_NB
-extern int num_k8_northbridges;
static inline struct pci_dev *node_to_k8_nb_misc(int node)
- return (node < num_k8_northbridges) ? k8_northbridges[node] : NULL;
+ return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
-#define num_k8_northbridges 0
static inline struct pci_dev *node_to_k8_nb_misc(int node)