path: root/arch/x86/include/asm/gart.h
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authorBorislav Petkov <borislav.petkov@amd.com>2010-09-03 18:39:40 +0200
committerIngo Molnar <mingo@elte.hu>2010-09-05 14:28:34 +0200
commit260133ab658bd2b80e07832a878e00405e19ff43 (patch)
treec48b062b77416348c268f80df7c294f35f35588f /arch/x86/include/asm/gart.h
parent57ab43e33122ffdc2eebca5d6de035699f0a8c06 (diff)
x86, GART: Disable GART table walk probes
Current code tramples over bit F3x90[6] which can be used to disable GART table walk probes. However, this bit should be set for performance reasons (speed up GART table walks). We are allowed to do that since we put GART tables in UC memory later anyway. Make it so. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Cc: Dave Airlie <airlied@redhat.com> Cc: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> LKML-Reference: <1283531981-7495-3-git-send-email-bp@amd64.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/gart.h')
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/x86/include/asm/gart.h b/arch/x86/include/asm/gart.h
index fba0a72c4cc..bf357f9b25f 100644
--- a/arch/x86/include/asm/gart.h
+++ b/arch/x86/include/asm/gart.h
@@ -17,6 +17,7 @@ extern int fix_aperture;
#define GARTEN (1<<0)
#define DISGARTCPU (1<<4)
#define DISGARTIO (1<<5)
+#define DISTLBWALKPRB (1<<6)
/* GART cache control register bits. */
#define INVGART (1<<0)
@@ -56,6 +57,19 @@ static inline void gart_iommu_hole_init(void)
extern int agp_amd64_init(void);
+static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
+ u32 ctl;
+ /*
+ * Don't enable translation but enable GART IO and CPU accesses.
+ * Also, set DISTLBWALKPRB since GART tables memory is UC.
+ */
+ ctl = DISTLBWALKPRB | order << 1;
+ pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
u32 tmp, ctl;