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authorMike Frysinger <vapier@gentoo.org>2010-10-22 05:11:08 +0000
committerMike Frysinger <vapier@gentoo.org>2010-10-22 16:30:03 -0400
commitb9ac41e314f0b43641bc01bd553fd2e0458ed832 (patch)
treef150d78ab68d4daaace99ab80f4e6d8705919dc8 /arch/blackfin
parentfec84d21c52bca67949a17aaf7d410b497f8e1b0 (diff)
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Blackfin: bfin_spi.h: add MMR peripheral layout
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/include/asm/bfin5xx_spi.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
index 4223cf08ce8..0b5136e334b 100644
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ b/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -41,6 +41,25 @@
#define BIT_STU_SENDOVER 0x0001
#define BIT_STU_RECVFULL 0x0020
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits. So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+
+/*
+ * bfin spi registers layout
+ */
+struct bfin_spi_regs {
+ __BFP(ctl);
+ __BFP(flg);
+ __BFP(stat);
+ __BFP(tdbr);
+ __BFP(rdbr);
+ __BFP(baud);
+ __BFP(shadow);
+};
+
#define MAX_CTRL_CS 8 /* cs in spi controller */
/* device.platform_data for SSP controller devices */