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authorHaiying Wang <Haiying.Wang@freescale.com>2009-05-01 15:40:48 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-05-19 00:50:24 -0500
commit98ca77af23da6682bb3e34961a3f32e2c064a4ce (patch)
tree7c022d718c8933d25cf59c71ace2683731f905e9 /Documentation/powerpc/dts-bindings
parent345f84227b50e90329dd303499024603596566f4 (diff)
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powerpc/qe: update QE Serial Number
The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will get the number of SNUMs from device tree by reading the new property "fsl,qe-num-snums", and set 28 as the default number of SNUMs so that it is compatible with the old QE chips' device trees which don't have this new property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum table which is 256. Also we update the snum_init[] array with 18 more new SNUMs which are confirmed to be useful on new chip. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/powerpc/dts-bindings')
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
index 39b5d1f0bbe..6e37be1eeb2 100644
--- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -18,6 +18,8 @@ Required properties:
- reg : offset and length of the device registers.
- bus-frequency : the clock frequency for QUICC Engine.
- fsl,qe-num-riscs: define how many RISC engines the QE has.
+- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the
+ threads.
Recommended properties
- brg-frequency : the internal clock source frequency for baud-rate