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authorZou Nan hai <nanhai.zou@intel.com>2010-06-25 13:40:22 +0800
committerEric Anholt <eric@anholt.net>2010-08-09 14:13:39 -0700
commitce17178094f368d9e3f39b2cb4303da5ed633dd4 (patch)
tree81b0745ea43d217cea9527ed4f67f12de2ac1b52
parent8545423a912cf500009cbadfae57f706cf2b28e8 (diff)
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drm/i915: Enable RC6 on Ironlake.
RC6 allows the GPU to enter a lower power state when the GPU is idle. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [anholt: Fixed the !renderctx error path to actually not enable RC6.] Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4668e9bf67d..149c18b7c37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5753,7 +5753,8 @@ void intel_init_clock_gating(struct drm_device *dev)
ILK_DPFC_DIS2 |
ILK_CLK_FBC);
}
- return;
+ if (IS_GEN6(dev))
+ return;
} else if (IS_G4X(dev)) {
uint32_t dspclk_gate;
I915_WRITE(RENCLK_GATE_D1, 0);
@@ -5814,9 +5815,11 @@ void intel_init_clock_gating(struct drm_device *dev)
OUT_RING(MI_FLUSH);
ADVANCE_LP_RING();
}
- } else
+ } else {
DRM_DEBUG_KMS("Failed to allocate render context."
- "Disable RC6\n");
+ "Disable RC6\n");
+ return;
+ }
}
if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {