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authorRamakrishna Pallala <ramakrishna.pallala@intel.com>2010-12-09 10:37:47 +0000
committerAlan Cox <alan@linux.intel.com>2010-12-09 10:37:47 +0000
commitebe1c137340dc5f47d2b871e7eb81971d6ef7ec6 (patch)
treec72281a3e2b6288d0e4ddafffe23df7cf5245053
parente169506369d8d0015aa8ee65bfe869cdee7b4468 (diff)
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Register Initialization and conversion of coulombs to amphrs
cc_to_coloumbs/ msic_get_charge_now functions are added to return charge in mAhrs. Init_msic_regs function modified to add two more registers initialization. Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com>
-rw-r--r--drivers/power/intel_mdf_battery.c86
1 files changed, 66 insertions, 20 deletions
diff --git a/drivers/power/intel_mdf_battery.c b/drivers/power/intel_mdf_battery.c
index f085065b2ae..5a58b0c527f 100644
--- a/drivers/power/intel_mdf_battery.c
+++ b/drivers/power/intel_mdf_battery.c
@@ -106,10 +106,12 @@
#define CHR_SPCHRGER_WEAKVIN 0x04
#define MSIC_BATT_CHR_CHRTTIME_ADDR 0x18C
-#define CHR_CHRTIME_SET_12HRS 0x0E
+#define CHR_CHRTIME_SET_13HRS 0x0F
#define MSIC_BATT_CHR_CHRCTRL1_ADDR 0x18D
-#define MSIC_BATT_CHR_EXTCHRDIS_MASK (1 << 5)
+#define MSIC_EMRG_CHRG_ENBL (1 << 3)
+/* Lower Temp thresold set to -10C */
+#define MSIC_EMRG_CHRG_TEMP (1 << 4)
/* Safe limit registers */
#define MSIC_BATT_CHR_PWRSRCLMT_ADDR 0x18E /* Temperature limits */
@@ -194,20 +196,31 @@
*/
#define CONV_VOL_DEC_MSICREG(a) (((a - 3500) / 20) << 2)
+#define BATT_LOWBATT_CUTOFF_VOLT 3800 /* 3800 mV */
+#define BATT_DEAD_CUTOFF_VOLT 3400 /* 3400 mV */
+#define BATT_ADC_VOLT_ERROR 25 /* 25 mV */
+#define CHARGE_FULL_IN_MAH 1500 /* 1500 mAh */
+#define MSIC_CHRG_RBATT_VAL 180 /* 180 mOhms */
+#define COLMB_TO_MAHRS_CONV_FCTR 3600
+
+#define MSIC_BATT_TEMP_MAX 60000 /* 60000 milli degrees */
+#define MSIC_BATT_TEMP_MIN 0
+#define MSIC_TEMP_HYST_ERR 4000 /* 4000 milli degrees */
+
/* internal return values */
-#define BIT_SET 0
-#define BIT_RESET 1
-#define NR_ARR_ELM_MAX 5
+#define BIT_SET 1
+#define BIT_RESET 0
/* IPC defines */
#define IPCMSG_BATTERY 0xEF
#define TEMP_CHARGE_DELAY_JIFFIES (HZ * 30) /*30 sec */
-#define IRQ_FIFO_MAX 16
+#define IRQ_FIFO_MAX 16
#define THERM_CURVE_MAX_SAMPLES 7
-#define THERM_CURVE_MAX_VALUES 4
-#define BATT_STRING_MAX 8
+#define THERM_CURVE_MAX_VALUES 4
+#define BATT_STRING_MAX 8
+#define HYSTR_SAMPLE_MAX 4
/* Valid msic exceptional events */
@@ -791,6 +804,32 @@ static unsigned int msic_read_coloumb_ctr(void)
dev_warn(msic_dev, "IPC Command Failed %s\n", __func__);
return cvalue;
}
+static unsigned int cc_to_coloumbs(unsigned int cc_val)
+{
+ unsigned int coloumbs = 0;
+
+ /* Every LSB of cc adc bit equal to 95.37uC
+ * Approxmating it to 95uC
+ */
+ coloumbs = (cc_val & MSIC_BATT_ADC_ACCCHRGVAL_MASK) * 95;
+
+ /* return in milli coloumbs */
+ return coloumbs / 1000;
+}
+
+static unsigned int msic_get_charge_now(void)
+{
+ unsigned int temp_val, coloumbs;
+
+ temp_val = msic_read_coloumb_ctr();
+ coloumbs = cc_to_coloumbs(temp_val);
+
+ /*
+ * Convert the milli Coloumbs into mAh
+ * 1 mAh = 3600 mC
+ */
+ return coloumbs / COLMB_TO_MAHRS_CONV_FCTR;
+}
/**
* msic_usb_get_property - usb power source get property
@@ -846,7 +885,9 @@ static unsigned int mdf_cal_avg(unsigned int avg)
unsigned int charge_now;
charge_now = msic_read_coloumb_ctr();
- avg += charge_now;
+
+ /* Conver charge now to mAh */
+ avg += cc_to_coloumbs(charge_now) / COLMB_TO_MAHRS_CONV_FCTR;
return avg / 2;
}
@@ -904,16 +945,16 @@ static int msic_battery_get_property(struct power_supply *psy,
val->intval = mbi->batt_props.cur_now * 1000;
break;
case POWER_SUPPLY_PROP_CHARGE_NOW:
- mbi->batt_props.charge_now = msic_read_coloumb_ctr();
- val->intval = mbi->batt_props.charge_now;
+ mbi->batt_props.charge_now = msic_get_charge_now();
+ val->intval = mbi->batt_props.charge_now * 1000;
break;
case POWER_SUPPLY_PROP_CHARGE_FULL:
- val->intval = mbi->batt_props.charge_full;
+ val->intval = mbi->batt_props.charge_full * 1000;
break;
case POWER_SUPPLY_PROP_CHARGE_AVG:
mbi->batt_props.charge_avg =
mdf_cal_avg(mbi->batt_props.charge_avg);
- val->intval = mbi->batt_props.charge_avg;
+ val->intval = mbi->batt_props.charge_avg * 1000;
break;
case POWER_SUPPLY_PROP_CAPACITY:
val->intval = mbi->batt_props.capacity;
@@ -1689,11 +1730,11 @@ void sfi_table_populate(struct msic_batt_sfi_prop *sfi_table)
sfi_table->temp_mon_range[3].range_number = 3;
sfi_table->temp_mon_range[3].temp_low_lim = -10;
sfi_table->temp_mon_range[3].temp_up_lim = 0;
- sfi_table->temp_mon_range[3].full_chrg_cur = 350;
+ sfi_table->temp_mon_range[3].full_chrg_cur = 950;
sfi_table->temp_mon_range[3].full_chrg_vol = 3900;
- sfi_table->temp_mon_range[3].maint_chrg_cur = 350;
+ sfi_table->temp_mon_range[3].maint_chrg_cur = 950;
sfi_table->temp_mon_range[3].maint_chrg_vol_ll = 3950;
- sfi_table->temp_mon_range[3].maint_chrg_vol_ul = 3950;;
+ sfi_table->temp_mon_range[3].maint_chrg_vol_ul = 3950;
sfi_table->sram_addr = 0xFFFF7FC3;
}
@@ -1721,7 +1762,7 @@ static void init_batt_props(struct msic_power_module_info *mbi)
mbi->batt_props.vol_max_des = sfi_table->voltage_max;
mbi->batt_props.vol_now = 0x0;
mbi->batt_props.cur_now = 0x0;
- mbi->batt_props.charge_full = 5400000; /* 5400 milii coulombs */
+ mbi->batt_props.charge_full = CHARGE_FULL_IN_MAH;
mbi->batt_props.charge_now = 0x0;
mbi->batt_props.charge_avg = 0x0;
mbi->batt_props.capacity = 0;
@@ -1779,18 +1820,23 @@ static int init_msic_regs(struct msic_power_module_info *mbi)
MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRTTIME_ADDR,
MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_SPCHARGER_ADDR,
MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRSTWDT_ADDR,
+ MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRCTRL_ADDR,
+ MSIC_BATT_CHR_WDTWRITE_ADDR, MSIC_BATT_CHR_CHRCTRL1_ADDR
};
static u8 data[] = {
WDTWRITE_UNLOCK_VALUE, CHR_PWRSRCLMT_SET_RANGE,
WDTWRITE_UNLOCK_VALUE,
CONV_VOL_DEC_MSICREG(CHR_CHRVOLTAGE_SET_DEF),
- WDTWRITE_UNLOCK_VALUE, CHR_CHRTIME_SET_12HRS,
+ WDTWRITE_UNLOCK_VALUE, CHR_CHRTIME_SET_13HRS,
WDTWRITE_UNLOCK_VALUE,
(~CHR_SPCHRGER_LOWCHR_ENABLE & CHR_SPCHRGER_WEAKVIN),
- WDTWRITE_UNLOCK_VALUE, CHR_WDT_DISABLE
+ WDTWRITE_UNLOCK_VALUE, CHR_WDT_DISABLE,
+ WDTWRITE_UNLOCK_VALUE, CHRCNTL_CHRG_DISABLE,
+ WDTWRITE_UNLOCK_VALUE, MSIC_EMRG_CHRG_ENBL | MSIC_EMRG_CHRG_TEMP
+
};
- return msic_write_multi(mbi, address, data, 10);
+ return msic_write_multi(mbi, address, data, 14);
}