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// -----------------------------------------------------------------------
//
//   Copyright 2003-2019 H. Peter Anvin - All Rights Reserved
//
//   Permission is hereby granted, free of charge, to any person
//   obtaining a copy of this software and associated documentation
//   files (the "Software"), to deal in the Software without
//   restriction, including without limitation the rights to use,
//   copy, modify, merge, publish, distribute, sublicense, and/or
//   sell copies of the Software, and to permit persons to whom
//   the Software is furnished to do so, subject to the following
//   conditions:
//
//   The above copyright notice and this permission notice shall
//   be included in all copies or substantial portions of the Software.
//
//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
//   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
//   OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
//   NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
//   HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
//   WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
//   FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
//   OTHER DEALINGS IN THE SOFTWARE.
//
// -----------------------------------------------------------------------

//
// abc806addon.v
//
// Top-level module for ABC806 helper board
// using the QMTech Cyclone IV Starter Kit board.
//

//
// Use a DDR buffer to output a clock
//
module outclk (
	       input rst_n,
	       input clk,
	       output pin
	       );

   ddrio_out clkbuf (
		    .aclr ( ~rst_n ),
		    .datain_h ( 1'b1 ),
		    .datain_l ( 1'b0 ),
		    .outclock ( clk ),
		    .dataout ( pin )
		    );
endmodule // outclk

module abc806addon (
		 // Clock
		 input	       clock_50,	// 50 MHz

		 // SPI flash
		 output        fl_ce_n,
		 output        fl_mosi,
		 output        fl_sck,
		 input         fl_miso,

		 // LED and pushbutton
		 output        led_n,
		 input         key_n,

		 // 40-pin GPIO header
		 output  [36:3] gpio,

		 // "Camera interface" (18-pin GPIO socket)
		 // Note that [4:3] have 4.7k pullups
		 inout  [18:3] camio,

		 // Each row (upper and lower) of the two PMODs;
		 // the lower side is the one numbered 7-12 in the
		 // 12-pin Pmod spec.
		 // pmod0 is J10, pmod1 is J11.
		 inout  [4:1]  pmod0u,
		 input  [4:1]  pmod0l,
		 inout  [4:1]  pmod1u,
		 inout  [4:1]  pmod1l,

		 // 7-segment LEDs, multiplexed
		 output  [2:0] s7_en,    // Digit enable, active high
		 output  [7:0] s7_n,	// Segment enable, active low

		 // VGA port
		 output reg [4:0] vga_r,	// VGA red
		 output reg [5:0] vga_g,	// VGA green
		 output reg [4:0] vga_b,	// VGA blue
		 output reg       vga_hs,	// VGA horz sync
		 output reg       vga_vs,	// VGA vert sync

		 // SDRAM, 32 MiB, 166 MHz
		 output        dram_ras_n, // SDRAM RAS#
		 output        dram_cas_n, // SDRAM CAS#
		 output        dram_cke,   // SDRAM clock enable
		 output        dram_clk,   // SDRAM clock
		 output        dram_cs_n,  // SDRAM CS#
		 output        dram_we_n,  // SDRAM WE#
		 output  [1:0] dram_dqm,   // SDRAM DQM (byte enables)
		 output [12:0] dram_a,     // SDRAM address bus
		 output  [1:0] dram_ba,    // SDRAM bank selects
		 inout  [15:0] dram_dq,    // SDRAM data bus

		 // Serial port (via CP2102 bridge)
		 output        uart_txd,   // RS232 port TxD
		 input         uart_rxd,   // RS232 port RxD

		 // Ethernet GMII (RealTek RTL8211EG PHY)
		 // 4.7k pullups on:   mdio, rxer, rxd[7:4], crs
		 // 4.7k pulldowns on: txer, rxdv, col
		 //
		 // Pin naming from the RTL8211EG datasheet (GMII mode)
		 // except GTX_CLK -> GTXC, TXCLK -> TXC and PHYRSTB -> RST_n
		 // for consistency.
		 //
		 // The following pins or latched inputs are hard-wired
		 // or aliased to MAC input pins. To override defaults
		 // change the pins to INOUT and override during reset.
		 //
		 // Values in parens are pullup/pulldowns.
		 //   PHY_AD[1:0] = 01     : PHY address 1 or 5
		 //   PHY_AD[2]   = RXDV   : (0) address 1
		 //   AN[1]       = RXER   : (1) all modes supported
		 //   AN[0]       = RXD[7] : (1)
		 //   Mode        = COL    : (0) GMII mode
		 //   SELRGV      = RXD[4] : (1) 3.3 V (important!!!)
		 //   TXDLY       = RXD[5] : (1) delay in RGMII mode
		 //   RXDLY       = RXD[6] : (1) delay in RGMII mode
		 //
		 //   LED0        = yellow : blink on active
		 //   LED1        = green  : steady on link
		 //
		 // Pins unavailable: LED2, PMEB, INTB, CLK125
		 //

		 // Reset timing: 10 ms asserted, 30 ms before register access
		 output        e_rst_n,    // PHY reset (PHYRSTB)

		 output        e_mdc,      // Management clock
		 inout         e_mdio,	   // Management I/O

		 input         e_rxc,      // Receive data clock
		 input         e_rxdv,	   // Receive data valid
		 input         e_rxer,	   // Receive data error
		 input   [7:0] e_rxd,	   // Receive data bus

		 input         e_txc,      // Transmit data clock 10/100 Mbps
		 output        e_gtxc,     // Transmit data clock 1000 Mbps
		 output        e_txen,	   // Transmit enable
		 output        e_txer,	   // Transmit error
		 output  [7:0] e_txd,	   // Transmit data bus

		 input         e_col,      // Collision sense
		 input         e_crs	   // Carrier detect
	      );

   // ------------------------------------------------------------------
   //  PLL and reset
   // ------------------------------------------------------------------

   wire rst_n;
   wire clk;
   wire vid_master_clk;		// 360 MHz to swpll
   wire vid_clk;
   wire vid_clk_stb;

   wire [1:1] pll_locked;

   pll1 pll1 (
	      .areset ( 1'b0 ),
	      .inclk0 ( clock_50 ),
	      .c0 ( clk ),
	      .c1 ( vid_master_clk ),
	      .locked ( pll_locked[1] )
	      );

   wire       ready = &pll_locked;

   assign rst_n = ready;

   wire       fast_sync;
   swpll swpll (
		.rst_n ( rst_n ),
		.clk ( vid_master_clk ),
		.sync ( fast_sync ),
		.out_clk ( vid_clk ),
		.out_clk_stb ( vid_clk_stb )
		);

   // ------------------------------------------------------------------
   //  Monitor scan converter
   // ------------------------------------------------------------------

   wire conv_r, conv_g, conv_b, conv_s;
   wire [3:0] vid_sync_q;

   // First synchronize to vid_master_clk, then latch in vid_clk domain.
   // The synchronizer runs on the negative vid_master_clk, because the
   // hold relationship between vid_master_clk and vid_sync_q is
   // ill-defined.
   synchronizer #(.width(4), .stages(3)) rgb_synchro
     (
      .rst_n ( rst_n ),
      .clk   ( vid_master_clk ),
      .d     ( { pmod0l[4:2], ~pmod0l[1] } ),
      .q     ( vid_sync_q )
      );
   assign fast_sync = vid_sync_q[0];

   // This guarantees at least one vid_master_clk of both
   // setup and hold
   reg [3:0] abc_rgbs_mc;
   reg	     prev_vid_clk;
   always @(posedge vid_master_clk or negedge rst_n)
     if (~rst_n)
       begin
	  abc_rgbs_mc  <= 4'b0000;
	  prev_vid_clk <= 1'b0;
       end
     else
       begin
	  prev_vid_clk <= vid_clk;
	  if (vid_clk & prev_vid_clk)
	    abc_rgbs_mc <= vid_sync_q;
       end

   reg [3:0] abc_rgbs;
   always @(posedge vid_clk or negedge rst_n)
     if (~rst_n)
       abc_rgbs <= 4'b0000;
     else
       abc_rgbs <= abc_rgbs_mc;

   scanconv scanconv (
		      .rst_n ( rst_n ),
		      .clk ( vid_clk ),

		      .abc_b ( abc_rgbs[1] ),
		      .abc_g ( abc_rgbs[2] ),
		      .abc_r ( abc_rgbs[3] ),
		      .abc_s ( abc_rgbs[0] ),

		      .vga_b ( conv_b ),
		      .vga_g ( conv_g ),
		      .vga_r ( conv_r ),
		      .vga_s ( conv_s )
		      );

   always @(posedge vid_clk or negedge rst_n)
     if (~rst_n)
       begin
	  vga_r <= 5'b0;
	  vga_g <= 6'b0;
	  vga_b <= 6'b0;
	  vga_hs <= 1'b1;
	  vga_vs <= 1'b1;
       end
     else
       begin
	  vga_r  <= {5{conv_r}};
	  vga_g  <= {6{conv_g}};
	  vga_b  <= {5{conv_b}};
	  vga_hs <= ~conv_s;	// Composite sync
	  vga_vs <= ~conv_s;	// Or could just be set to 1(?)
       end

   // ------------------------------------------------------------------
   //  7-segment display
   // ------------------------------------------------------------------

   reg [2:0]  s7_mux;
   reg [2:0]  s7_mux_out;
   reg [9:0]  s7_switch_ctr;	// ~140 kHz switch frequency
   reg [7:0]  s7_dig [2:0];
   wire [7:0] s7_in [2:0];
   reg [7:0]  s7_out;

   always @(posedge clk or negedge rst_n)
     if (~rst_n)
       begin
	  s7_mux <= 3'b001;
	  s7_switch_ctr <= 10'b0;
       end
     else
       begin
	  s7_switch_ctr <= s7_switch_ctr + 1'b1;
	  if (&s7_switch_ctr)
	    s7_mux <= { s7_mux[1:0], s7_mux[2] };
       end // else: !if(~rst_n)

   always @(posedge clk or negedge rst_n)
     s7_mux_out <= s7_mux;	// Delayed by one cycle to match s7_out

   generate
      genvar i;

      for (i = 0; i < 3; i = i + 1)
	begin : s7_latch_in
	   always @(posedge clk or negedge rst_n)
	     s7_dig[i] <= s7_in[i];
	end
   endgenerate

   generate
      genvar j;

      for (j = 0; j < 8; j = j + 1)
	begin : s7_latch_out
	   always @(posedge clk or negedge rst_n)
	     s7_out[j] <= ~((s7_dig[0][j] & s7_mux[0]) |
			    (s7_dig[1][j] & s7_mux[1]) |
			    (s7_dig[2][j] & s7_mux[2]));
	end
   endgenerate

   wire s7_turn = 1'b0;		// Upside down output?

   assign s7_en = s7_turn ? { s7_mux_out[0], s7_mux_out[1], s7_mux_out[2] } : s7_mux_out;
   assign s7_n  = s7_turn ? { s7_out[7:6], s7_out[2:0], s7_out[5:3] } : s7_out;

   assign s7_in[0] = 8'b0111_1101; // 6
   assign s7_in[1] = 8'b0011_1111; // 0
   assign s7_in[2] = 8'b0111_1111; // 8

   // ------------------------------------------------------------------
   //  Unused hardware ports, default assignments.
   // ------------------------------------------------------------------

   // SPI flash
   assign                   fl_ce_n     = 1'b1;
   assign                   fl_mosi     = 1'b0;
   assign                   fl_sck      = 1'b0;

   // LED
   assign                   led_n       = 1'b1;

   // GPIOs
   //assign                   gpio        = 32'hzzzz_zzzz;

   // Debugging output
   assign gpio[3] = ~pmod0l[1];	// Sync in
   assign gpio[4] =  pmod0l[2];	// Blue in
   assign gpio[5] =  pmod0l[3];	// Green in
   assign gpio[6] =  pmod0l[4];	// Red in

   assign gpio[7]  = vga_hs;	// Sync out
   assign gpio[8]  = vga_b[4];
   assign gpio[9]  = vga_g[5];
   assign gpio[10] = vga_r[4];

   // Scaled versions (divided by 16) of the clocks for debugging
   reg [3:0] debug_vid_clk;

   always @(posedge vid_clk or negedge rst_n)
     if (~rst_n)
       debug_vid_clk <= 4'b0;
     else
       debug_vid_clk <= debug_vid_clk + 1'b1;

   // Note: leading edge at start of count
   assign gpio[11] = ~debug_vid_clk[3];

   assign gpio[36:12] = 25'b0;

   assign                   camio       = 16'hzzzz;
   //assign                   pmod0l      = 4'bzzzz;
   assign                   pmod0u      = 4'bzzzz;
   assign                   pmod1l      = 4'bzzzz;
   assign                   pmod1u      = 4'bzzzz;

   // SDRAM
   assign		    dram_ba     = 2'b11;
   assign		    dram_ras_n  = 1'b1;
   assign		    dram_cas_n  = 1'b1;
   assign		    dram_cke    = 1'b1;
   assign		    dram_clk    = 1'b1;
   assign		    dram_cs_n   = 1'b1;
   assign		    dram_we_n   = 1'b1;
   assign		    dram_dqm    = 2'b11;
   assign		    dram_a      = ~13'b0;
   assign		    dram_dq     = ~16'b0;

   // RS232
   assign		    uart_txd    = 1'b1;

   // Ethernet
   assign                   e_rst_n     = 1'b0; // Hold in reset
   assign                   e_mdc       = 1'b0;
   assign                   e_mdio      = 1'bz;
   assign                   e_gtxc      = 1'b0;
   assign                   e_txen      = 1'b0;
   assign                   e_txer      = 1'b0;
   assign                   e_txd       = 8'b0;

endmodule // abc806addon template