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# -*- tcl -*-

# Clock constraints

create_clock -name "clock_50" -period 20ns [get_ports {clock_50}]

# Automatically constrain PLL and other generated clocks
derive_pll_clocks

# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

# Generated video clock; this lets Quartus know it is synchronous with the 360 MHz clock.
# The divide is nominally by 5, so it can vary between 4 and 6 in real life;
# if it is not, the PLL is not in sync and we don't really care...

create_generated_clock -name "vid_clk_4" -edges {1 5 9} -source [get_nodes "pll1\|*\|clk[1]"]      [get_registers "swpll:*\|out_clk_q"]
create_generated_clock -name "vid_clk_5a" -edges {1 5 11} -source [get_nodes "pll1\|*\|clk[1]"] -add [get_registers "swpll:*\|out_clk_q"]
create_generated_clock -name "vid_clk_5b" -edges {1 7 11} -source [get_nodes "pll1\|*\|clk[1]"] -add [get_registers "swpll:*\|out_clk_q"]
create_generated_clock -name "vid_clk_6" -edges {1 7 13} -source [get_nodes "pll1\|*\|clk[1]"] -add [get_registers "swpll:*\|out_clk_q"]
set_clock_groups -exclusive -group {vid_clk_4} -group {vid_clk_5a} -group {vid_clk_5b} -group {vid_clk_6}


# Multicycle paths

# 2*64 here is massively sandbagging...
set_multicycle_path -setup -from [get_registers "*swpll_loop_filter:*\|acc[*]"] -to [get_registers "*swpll_loop_filter:*\|acc[*]"] 64
set_multicycle_path -hold  -from [get_registers "*swpll_loop_filter:*\|acc[*]"] -to [get_registers "*swpll_loop_filter:*\|acc[*]"] 63
set_multicycle_path -setup -from [get_registers "*swpll_loop_filter:*\|acc[*]"] -to [get_registers "*swpll_loop_filter:*\|p2[*]"] 64
set_multicycle_path -hold  -from [get_registers "*swpll_loop_filter:*\|acc[*]"] -to [get_registers "*swpll_loop_filter:*\|p2[*]"] 63
set_multicycle_path -setup -from [get_registers "*swpll:*\|p1[*]"] -to [get_registers "*swpll_loop_filter:*\|acc[*]"] 4
set_multicycle_path -hold  -from [get_registers "*swpll:*\|p1[*]"] -to [get_registers "*swpll_loop_filter:*\|acc[*]"] 3

# vid_master_clk -> vid_clk crossing: latch in the vid_master_clk domain,
# but only on cycles where vid_clk_stb is high, so after the first
# master clock cycle of the vid_clk cycle
set_multicycle_path -setup -from [get_registers "abc_rgbs_mc[*]"] -to [get_registers "abc_rgbs[*]"] -start 1
set_multicycle_path -hold -from [get_registers "abc_rgbs_mc[*]"] -to [get_registers "abc_rgbs[*]"] -start 1

# tsu/th constraints

# tco constraints

# tpd constraints