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* swpll: works reasonalby well now. Still some very small glitches...H. Peter Anvin2019-10-121-8/+61
* swpll: actually extract the hsync signals from the composite syncH. Peter Anvin2019-10-091-14/+3
* vid_master_clk: fix commentH. Peter Anvin2019-10-091-1/+1
* Now meets timing with a 360 MHz video master clock!H. Peter Anvin2019-10-091-33/+56
* Implement Altera's recommendation of async-assert sync-deassert resetH. Peter Anvin2019-10-041-10/+12
* Implement a software PLL to generate a synchronized clock for videoH. Peter Anvin2019-10-021-11/+42
* Initial version; good enough to give a somewhat shaky output pictureH. Peter Anvin2019-09-261-0/+299