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masterswpll: break the NCO counter into 3-bit(!) chunks; parameterizeH. Peter Anvin11 months
 
 
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2019-10-12swpll: break the NCO counter into 3-bit(!) chunks; parameterizeHEADmasterH. Peter Anvin1-47/+80
2019-10-12Even better parameters; proper ramstyle annotationsH. Peter Anvin1-4/+8
2019-10-12swpll: works reasonalby well now. Still some very small glitches...H. Peter Anvin14-91/+533
2019-10-09scanconv: clean up; 72 MHz PLL-synchronized clock for usH. Peter Anvin1-104/+33
2019-10-09swpll: actually extract the hsync signals from the composite syncH. Peter Anvin2-16/+61
2019-10-09vid_master_clk: fix commentH. Peter Anvin1-1/+1
2019-10-09abc806addon.sdc: remove obsolete commentH. Peter Anvin1-1/+0
2019-10-09More timing optimizations. Now pass even hold constraints.H. Peter Anvin3-14/+19
2019-10-09Now meets timing with a 360 MHz video master clock!H. Peter Anvin7-127/+256
2019-10-04Implement Altera's recommendation of async-assert sync-deassert resetH. Peter Anvin5-22/+30
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