fpga/abc800/abc806-addon.git - ABC806 FPGA add-on card

Branch	Commit message	Author	Age
master	swpll: break the NCO counter into 3-bit(!) chunks; parameterize	H. Peter Anvin	5 years
pllstep	hdmi: improve pad timing, combinatorial logic version of TMDS encoder	H. Peter Anvin	3 years


Age	Commit message	Author	Files	Lines
2019-10-12	swpll: break the NCO counter into 3-bit(!) chunks; parameterizeHEAD master	H. Peter Anvin	1	-47/+80
2019-10-12	Even better parameters; proper ramstyle annotations	H. Peter Anvin	1	-4/+8
2019-10-12	swpll: works reasonalby well now. Still some very small glitches...	H. Peter Anvin	14	-91/+533
2019-10-09	scanconv: clean up; 72 MHz PLL-synchronized clock for us	H. Peter Anvin	1	-104/+33
2019-10-09	swpll: actually extract the hsync signals from the composite sync	H. Peter Anvin	2	-16/+61
2019-10-09	vid_master_clk: fix comment	H. Peter Anvin	1	-1/+1
2019-10-09	abc806addon.sdc: remove obsolete comment	H. Peter Anvin	1	-1/+0
2019-10-09	More timing optimizations. Now pass even hold constraints.	H. Peter Anvin	3	-14/+19
2019-10-09	Now meets timing with a 360 MHz video master clock!	H. Peter Anvin	7	-127/+256
2019-10-04	Implement Altera's recommendation of async-assert sync-deassert reset	H. Peter Anvin	5	-22/+30
[...]

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