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// -----------------------------------------------------------------------
//
// Copyright 2016 H. Peter Anvin - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
// Boston MA 02110-1301, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
//
// neopixel.v
//
// Driver for WS2812 (neopixel) LED chains
//
// This drives 32 output channels and expects a 25 MHz clock.
// As long as the external RAM can keep up, the number of channels
// should scale with clock frequency.
//
module neopixel (
// System signals
input rst_n,
input clk,
input enable,
// CPU interface to the config RAM
input [7:0] cpu_do,
input [6:0] cpu_a,
input cpu_wr_n,
input cpu_rd_n,
output [7:0] cpu_di,
// SRAM interface
output [18:0] ram_a, // BIT address into system RAM
input ram_q, // Expected one cycle later
// Neopixel pulse output
output reg [31:0] npout
);
// Pipeline stages:
// A - generate address for config/status RAM
// B - generate address for SRAM, advance staus RAM
// D - process and latch output
// E - pulse shaping
reg g_enable; // Global enable, latched on word boundaries
// Bit/channel counters
// 32 channels x 24 bits
reg [9:0] a_ctr;
reg [9:0] b_ctr;
reg [9:0] d_ctr;
reg [9:0] e_ctr;
wire [9:0] a_ctr_p1 = a_ctr + 1'b1;
always @(negedge rst_n or posedge clk)
if (~rst_n)
begin
a_ctr <= 10'd0;
b_ctr <= 10'd1;
d_ctr <= 10'd2;
e_ctr <= 10'd3;
g_enable <= 1'b0;
end
else
begin
// a_ctr[9:5] counts from 0 to 23 (bits per word)
if (&a_ctr_p1[9:8])
begin
a_ctr <= 10'b0;
g_enable <= enable;
end
else
begin
a_ctr <= a_ctr_p1;
end
b_ctr <= a_ctr;
d_ctr <= b_ctr;
e_ctr <= d_ctr;
end // else: !if(~rst_n)
// A stage, counter fed to RAMs
wire [7:0] conf_cpu_q;
wire [31:0] b_conf_q;
// Configuration RAM
npconfram npconfram (
.clock ( clk ),
.address_a ( a_ctr[4:0] ),
.data_a ( 32'bx ),
.wren_a ( 1'b0 ), // Readonly port
.q_a ( b_conf_q ),
.address_b ( cpu_a ),
.data_b ( cpu_do ),
.wren_b ( ~cpu_wr_n ),
.q_b ( conf_cpu_q )
);
assign cpu_di = ~cpu_rd_n ? conf_cpu_q : ~8'b0;
wire [35:0] b_stat_q;
reg [35:0] b_stat_d;
// Status RAM
npstatram npstatram (
.clock ( clk ),
.rdaddress ( a_ctr[4:0] ),
.q ( b_stat_q ),
.wraddress ( b_ctr[4:0] ),
.wren ( 1'b1 ),
.data ( b_stat_d )
);
// B stage, SRAM address generation
wire [15:0] b_conf_addr = b_conf_q[15:0];
wire [7:0] b_conf_plen = b_conf_q[23:16]; // Pattern len
wire [7:0] b_conf_clen = b_conf_q[31:24]; // Chain len
wire [15:0] b_stat_addr = b_stat_q[15:0];
wire [7:0] b_stat_pctr = b_stat_q[23:16];
wire [8:0] b_stat_cctr = b_stat_q[32:24];
// Output: are we in chain reset?
reg b_in_rst;
// Channel is enabled if plen > 0 or global disable
wire b_ena = |b_conf_plen & g_enable;
// True before stat ctr wrap. Cycles -1 and -2 are for reset
wire b_stat_end = b_stat_cctr[8] & ~b_stat_cctr[0];
always @(*)
begin
b_stat_d[35:33] = 3'bxxx;
b_stat_d[32:0] = b_stat_q[32:0];
if ( ~b_ena )
begin
b_stat_d[15:0] = b_conf_addr;
b_stat_d[32:24] = ~9'b0;
end
else
begin
if (&b_ctr[7:5]) // New byte?
begin
b_stat_d[15:0] = b_stat_addr + 1'b1;
if ( b_ctr[9] ) // New word?
begin
if ( b_stat_end | ~|b_stat_pctr )
b_stat_d[15:0] = b_conf_addr;
b_stat_d[23:16] =
(( b_stat_end | ~|b_stat_pctr ) ?
b_conf_plen : b_stat_pctr) - 1'b1;
b_stat_d[32:24] =
(b_stat_end ?
{1'b0, b_conf_clen} : b_stat_cctr) - 1'b1;
end // if ( b_ctr[9] )
end // if ( &b_ctr[7:5] )
end // else: !if( ~b_ena )
end // always @ (*)
always @(negedge rst_n or posedge clk)
if (~rst_n)
b_in_rst <= 1'b1;
else
b_in_rst <= ~b_ena | b_stat_cctr[8];
// b_ctr[7:5] is inverted as bit order is bigendian
assign ram_a = { b_stat_addr, ~b_ctr[7:5] };
// D stage, data out from SRAM, parallel out
reg [31:0] d_in_rst;
reg [31:0] d_data;
reg [1:0] pulse;
always @(negedge rst_n or posedge clk)
if (~rst_n)
begin
d_in_rst <= ~32'b0;
d_data <= 32'bx;
pulse <= 2'b0;
end
else
begin
d_in_rst[d_ctr[4:0]] <= b_in_rst;
d_data[d_ctr[4:0]] <= ram_q;
pulse[0] <= (d_ctr[4:0] < 5'd8);
pulse[1] <= (d_ctr[4:0] < 5'd20);
end
// E stage, pulse generation (all channels loaded in parallel)
reg [31:0] e_in_rst;
reg [31:0] e_data;
always @(negedge rst_n or posedge clk)
if (~rst_n)
begin
e_in_rst <= ~32'b0;
e_data <= 32'bx;
end
else if (&e_ctr[4:0])
begin
// Parallel load of all channels
e_in_rst <= d_in_rst;
e_data <= d_data;
end
genvar i;
generate
for (i = 0; i < 32; i = i + 1)
begin: gen_npout
always @(negedge rst_n or posedge clk)
if (~rst_n)
npout[i] <= 1'b0;
else
npout[i] <= ~e_in_rst[i] & pulse[e_data[i]];
end
endgenerate
endmodule // neopixel
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