fpga/abc80/abc80.git - ABC80 in an FPGA

	Commit message (Collapse)	Author	Age	Files	Lines
*	Finally: a functional version of the 200 MHz SRAM	H. Peter Anvin	2016-11-10	1	-3/+3
\| \| \| \| \| \|	The 200 MHz SRAM seems to finally work. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
*	sync.v: work around Quartus problem with generate if	H. Peter Anvin	2016-11-05	1	-39/+49
\| \| \| \| \| \| \| \| \| \| \|	Apparently generate if statements with declarations in both branches can make Quartus II think that the register is unused (duplicate?) Thus drop it and (suboptimally) always disable design rule D104. It would still be possible to fix this by duplicating the synchronizer code, but that's for later. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
*	sync.v: remove unused altera_attribute	H. Peter Anvin	2016-11-04	1	-2/+2
\| \| \| \| \| \| \| \|	No need to have a filter that will only used for a synchronizer at the top level, now when synchronizer should only be used from the synchronize wrapper module. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
*	sync.v: include both synchronizer and stabilizer support	H. Peter Anvin	2016-11-04	1	-14/+104
\| \| \| \| \| \| \|	Add appropriate modules for both synchronizer and stabilizer, with the appropriate attribute magic for both. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
*	WIP: adjust SRAM timing to be able to share with another device	H. Peter Anvin	2016-10-31	1	-0/+61
	Infrastructure for changing the SRAM timing to add another shared device (intended to be the Neopixel driver.) This means upping the SRAM state machine clock to 200 MHz; move video_clk to pll2 to be able to generate that output. It actually gets closer to proper VGA timing, but at the expense of needing a synchronizing FIFO for the fg unit. This also clears a lot of timing warnings. Signed-off-by: H. Peter Anvin <hpa@zytor.com>