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-rw-r--r--enc28j60.v34
1 files changed, 19 insertions, 15 deletions
diff --git a/enc28j60.v b/enc28j60.v
index abfe5bd..08e613f 100644
--- a/enc28j60.v
+++ b/enc28j60.v
@@ -65,14 +65,10 @@ module enc28j60 (
// Write commands:
// OUT - send data byte, leave CS# asserted
// C1 - send data byte, deassert CS#
- // C2 - send FF byte, leave CS# asserted
// C3 - reset
// Read commands:
// INP - read input shift register, output FF, leave CS# asserted
- // STATUS - read input shift register, output FF, deassert CS#
- //
- // If CS# is already deasserted, input simply returns the shift
- // register contents.
+ // STATUS - read input shift register, deassert CS#
// ------------------------------------------------------------------------
parameter selectcode = 6'd9;
@@ -94,10 +90,11 @@ module enc28j60 (
assign eth_sck = spi_clk;
assign eth_mosi = spi_shr_out[7];
- wire abc_active =
- selected & (~abc_out_n | ~abc_c1_n | ~abc_c2_n |
- ~abc_inp_n | ~abc_status_n);
-
+ wire abc_start = selected & (~abc_out_n | ~abc_c1_n | ~abc_inp_n );
+ wire abc_endread = selected & ~abc_status_n;
+ wire abc_active = abc_start | abc_endread;
+ wire abc_read = selected & (~abc_inp_n | ~abc_status_n);
+
assign abc_rdy = ~(abc_active & ~spi_cmd_ok);
reg [1:0] spi_state;
@@ -140,13 +137,13 @@ module enc28j60 (
begin
spi_cmd_ok <= 1'b1;
- if (abc_active)
+ if (abc_start)
begin
spi_cs_n <= 1'b0;
spi_state <= st_data;
spi_shr_out <= cpu_to_spi_data;
spi_ctr <= 4'd7;
- spi_finish <= ~abc_c1_n | ~abc_status_n;
+ spi_finish <= ~abc_c1_n;
end
end // case: spi_idle
@@ -167,11 +164,18 @@ module enc28j60 (
spi_ctr <= 4'd8;
spi_state <= st_cshold0;
end
- else if (abc_active)
+ else if (abc_endread)
+ begin
+ // After STATUS# we raise CS# immediately
+ spi_state <= st_cshold1;
+ spi_cs_n <= 1'b1;
+ spi_cmd_ok <= 1'b1;
+ end
+ else if (abc_start)
begin
spi_shr_out <= cpu_to_spi_data;
spi_ctr <= 4'd7;
- spi_finish <= ~abc_c1_n | ~abc_status_n;
+ spi_finish <= ~abc_c1_n;
spi_cmd_ok <= 1'b1;
end
else
@@ -200,6 +204,7 @@ module enc28j60 (
st_cshold1:
begin
+ spi_cs_n <= 1'b1;
spi_state <= st_idle;
spi_cmd_ok <= 1'b1;
end
@@ -210,7 +215,6 @@ module enc28j60 (
//
// Output data
//
- assign abc_di = (selected & (~abc_inp_n | ~abc_status_n))
- ? spi_shr_in : 8'hff;
+ assign abc_di = abc_read ? spi_shr_in : 8'hff;
endmodule // enc28j60